[all-commits] [llvm/llvm-project] b6e4d2: [MLIR][Mem2Reg] Extract shared utilities for Promo...
Ehsan Amiri via All-commits
all-commits at lists.llvm.org
Wed Apr 1 10:34:18 PDT 2026
Branch: refs/heads/users/amehsan/weakc-delta-overflow
Home: https://github.com/llvm/llvm-project
Commit: b6e4d27c485af711214b3dafc96fa287e2fe33f6
https://github.com/llvm/llvm-project/commit/b6e4d27c485af711214b3dafc96fa287e2fe33f6
Author: Berke Ates <berke at ates.ch>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
A mlir/include/mlir/Interfaces/Utils/MemorySlotUtils.h
M mlir/lib/Dialect/SCF/IR/CMakeLists.txt
M mlir/lib/Dialect/SCF/IR/MemorySlot.cpp
M mlir/lib/Interfaces/Utils/CMakeLists.txt
A mlir/lib/Interfaces/Utils/MemorySlotUtils.cpp
M mlir/unittests/Interfaces/CMakeLists.txt
A mlir/unittests/Interfaces/MemorySlotUtilsTest.cpp
Log Message:
-----------
[MLIR][Mem2Reg] Extract shared utilities for PromotableRegionOpInterface (#188514)
The `PromotableRegionOpInterface` implementations use two helpers that
are likely useful for other dialects implementing this interface as
well:
- `updateTerminator`: Appends the reaching definition as an operand to a
block's terminator, falling back to a default when the block has no
entry (e.g. dead code).
- `replaceWithNewResults`: Clones an operation with additional result
types while preserving its regions, then replaces the original.
This PR extracts them into a common utility header so that downstream
dialects can reuse them directly.
I'm open to discussion about the location of these utilities.
Commit: f7329189c01d86434c08fd5cd791c7d1e791e6dc
https://github.com/llvm/llvm-project/commit/f7329189c01d86434c08fd5cd791c7d1e791e6dc
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M clang/docs/ClangIRCleanupAndEHDesign.md
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/Dialect/Transforms/EHABILowering.cpp
M clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp
A clang/test/CIR/CodeGen/cleanup-throwing-dtor.cpp
M clang/test/CIR/Transforms/eh-abi-lowering-itanium.cir
M clang/test/CIR/Transforms/flatten-cleanup-scope-nyi.cir
A clang/test/CIR/Transforms/flatten-throwing-in-cleanup.cir
Log Message:
-----------
[CIR] Handle throwing calls inside EH cleanup (#188341)
This implements handling for throwing calls inside an EH cleanup
handler. When such a call occurs, the CFG flattening pass replaces it
with a cir.try_call op that unwinds to a terminate block.
A new CIR operation, cir.eh.terminate, is added to facilitate this
handling, and the design document is updated to describe the new
behavior.
Assisted-by: Cursor / claude-4.6-opus-high
Commit: a0ffdf28500e21905cab02d1df28c9cef3581155
https://github.com/llvm/llvm-project/commit/a0ffdf28500e21905cab02d1df28c9cef3581155
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
A clang/test/CIR/CodeGen/ctor-alias-prev-decl.cpp
A clang/test/CIR/CodeGen/dtor-alias-prev-decl.cpp
Log Message:
-----------
[CIR] Allow replacement of a structor declaration with an alias (#188320)
We had an errorNYI diagnostic to trigger when we generated an alias for
a ctor or dtor that had an existing declaration. Because functions are
used via flat symbol references, all that is needed is to erase the old
declaration. This change does that.
Commit: 9d3079a7a975889f20c1ba2aa7301ec005547bfa
https://github.com/llvm/llvm-project/commit/9d3079a7a975889f20c1ba2aa7301ec005547bfa
Author: Bill Wendling <morbo at google.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/InlineAsmPrepare.cpp
Log Message:
-----------
[NFC][CodeGen] Prepare for expansion of InlineAsmPrepare (#189469)
Move some functions around so that the CallBrInst processing is
contained. The 'static' functions don't need to be declared at the top;
just place them before the calls. Fix the naming to use lower-case for
the first letter of function names.
Commit: 19caff444d2e6fc35942fb4cf6b8213d17557fbd
https://github.com/llvm/llvm-project/commit/19caff444d2e6fc35942fb4cf6b8213d17557fbd
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/unittests/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes b6e4d27 (#189473)
This fixes b6e4d27c485af711214b3dafc96fa287e2fe33f6.
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: e50f08b5488346d86f741f20d8d2dd2a7c0f9ec8
https://github.com/llvm/llvm-project/commit/e50f08b5488346d86f741f20d8d2dd2a7c0f9ec8
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToWiDistributeExperimental.cpp
M mlir/test/Dialect/XeGPU/sg-to-wi-experimental-unit.mlir
Log Message:
-----------
[MLIR] [XeGPU] Add distribution patterns for vector transpose, bitcast & mask ops in sg to wi pass (#187392)
This PR adds patterns for following vector ops in the new sg-to-wi pass
1. Transpose
2. BitCast
3. CreateMask
4. ConstantMask
Commit: 5f99854d0151a43d0f20452f58211c9fdde8f154
https://github.com/llvm/llvm-project/commit/5f99854d0151a43d0f20452f58211c9fdde8f154
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/Sema/SemaAMDGPU.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-wmma-w32.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-wmma-w32-param.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
M llvm/test/Bitcode/amdgpu-wmma-drop-ab-mods-upgrade.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/test/Target/LLVMIR/rocdl.mlir
Log Message:
-----------
[AMDGPU] Drop A and B neg modifier from amdgcn_wmma_bf16_16x16x32_bf16 (#189468)
Fixes: LCOMPILER-1673
Commit: 76f5c5d36c06559cf1767f6b2aa021452f2ac0dd
https://github.com/llvm/llvm-project/commit/76f5c5d36c06559cf1767f6b2aa021452f2ac0dd
Author: Baranov Victor <bar.victor.2002 at gmail.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M clang-tools-extra/clang-tidy/readability/ImplicitBoolConversionCheck.cpp
M clang-tools-extra/clang-tidy/readability/ImplicitBoolConversionCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/implicit-bool-conversion.rst
A clang-tools-extra/test/clang-tidy/checkers/readability/implicit-bool-conversion-allow-logical-operators.c
Log Message:
-----------
[clang-tidy] Add AllowLogicalOperatorConversion option to implicit-bool-conversion (#189149)
Fixes https://github.com/llvm/llvm-project/issues/176889.
Commit: ae835dea747da6824b386b4861c330d59af7af6d
https://github.com/llvm/llvm-project/commit/ae835dea747da6824b386b4861c330d59af7af6d
Author: Eric Feng <55723758+efric at users.noreply.github.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp
M mlir/test/Conversion/AMDGPUToROCDL/gfx1250.mlir
M mlir/test/Dialect/AMDGPU/invalid.mlir
M mlir/test/Dialect/AMDGPU/ops.mlir
Log Message:
-----------
[mlir][amdgpu] implement amdgpu.global_load_async_to_lds for gfx1250 (#189279)
This patch introduces an amdgpu wrapper for
`rocdl.global.load.async.to.lds.bN` intrinsics, which were introduced in
gfx1250.
Assisted-by: Claude
---------
Signed-off-by: Eric Feng <Eric.Feng at amd.com>
Commit: 54b723097b39b536eb7d1d6947b65d53a096ed47
https://github.com/llvm/llvm-project/commit/54b723097b39b536eb7d1d6947b65d53a096ed47
Author: Keshav Vinayak Jha <31160700+keshavvinayak01 at users.noreply.github.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/Dialect/Affine/Transforms/Passes.td
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Affine/Transforms/AffineExpandIndexOps.cpp
M mlir/lib/Dialect/Affine/Transforms/AffineExpandIndexOpsAsAffine.cpp
M mlir/test/Dialect/Affine/affine-expand-index-ops-as-affine.mlir
M mlir/test/Dialect/Affine/affine-expand-index-ops.mlir
M mlir/test/Dialect/Affine/canonicalize.mlir
M mlir/test/Dialect/Affine/ops.mlir
Log Message:
-----------
[MLIR][Affine] Add vector support to affine.linearize_index and affine.delinearize_index (#188369)
Allow `affine.delinearize_index` and `affine.linearize_index` to operate
on `vector<...x index>` types in addition to scalar indices.
---------
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Co-authored-by: Claude Opus 4.6 <noreply at anthropic.com>
Commit: 7a3b7f142d8ffd7b3e2a9cf0a065e3ff7bf76241
https://github.com/llvm/llvm-project/commit/7a3b7f142d8ffd7b3e2a9cf0a065e3ff7bf76241
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenCleanup.cpp
M clang/lib/CIR/CodeGen/CIRGenCleanup.h
A clang/test/CIR/CodeGen/new-delete-deactivation.cpp
Log Message:
-----------
[CIR] Implement handling of cleanups with active flag (#187389)
This implements handling of cleanup scopes in cases where a flag is
needed to indicate whether or not the cleanup is active. This happens in
cases where a cleanup is no longer required, but it isn't at the top of
the cleanup stack so it can't be popped. A temporary variable is used to
set the cleanup to an inactive state when it is no longer needed.
Assisted-by: Cursor / claude-4.6-opus-high (implementation)
Assisted-by: Cursor / gpt-5.3-codex (tests)
Commit: 8b21fe60b43fe358321bca904ae307406725c002
https://github.com/llvm/llvm-project/commit/8b21fe60b43fe358321bca904ae307406725c002
Author: Daniel Thornburgh <dthorn at google.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M clang/lib/CodeGen/BackendUtil.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/LTO.cpp
M lld/COFF/LTO.h
M lld/COFF/SymbolTable.cpp
M lld/ELF/Driver.cpp
M lld/ELF/LTO.cpp
M lld/ELF/LTO.h
A lld/test/COFF/lto-libcall-archive-bitcode.test
A lld/test/ELF/lto/libcall-archive-bitcode.test
A lld/test/wasm/lto/libcall-archive-bitcode.ll
M lld/wasm/LTO.cpp
M lld/wasm/LTO.h
M lld/wasm/SymbolTable.cpp
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/LTO/LTO.h
M llvm/include/llvm/LTO/LTOBackend.h
M llvm/lib/LTO/LTO.cpp
M llvm/lib/LTO/LTOBackend.cpp
M llvm/lib/LTO/LTOCodeGenerator.cpp
M llvm/lib/LTO/ThinLTOCodeGenerator.cpp
A llvm/test/LTO/Resolution/X86/libcall-external.ll
A llvm/test/LTO/Resolution/X86/libcall-in-thin-link.ll
A llvm/test/LTO/Resolution/X86/libcall-in-tu.ll
M llvm/tools/llvm-lto2/llvm-lto2.cpp
Log Message:
-----------
[LTO][LLD] Prevent invalid LTO libfunc transforms (#164916)
In LTO, part of LLVM's middle-end runs after linking has finished. LTO's
semantics depend on the complete set of extracted bitcode files being
known at this time. If the middle-end inserts new calls to library
functions (libfuncs) that are implemented in bitcode, this could extract
new bitcode object files into the link. These cannot be compiled,
leading to undefined symbol references.
Additionally, the middle-end in LTO may reason that such library
functions have no references, and it may internalize them, then
manipulate their API or even delete them. Afterwards, it may emit a call
to them, again producing undefined symbol references.
This patch resolves the former issue by ensuring that the middle end
emits no new references to symbols defined in bitcode, and it resolves
the latter issue by ensuring that extracted bitcode for libfuncs is
considered external, since new calls may be emitted to them at any time.
The new semantics are not yet established for MachO LLD, which does not
yet appear to have any special handling for libcalls in LTO. It also
does not yet support distributed ThinLTO; doing so would require
additional (de)serialization work.
This is the patch referenced in @ilovepi's and my talk at the last LLVM
devmeeting: "LT-Uh-Oh"
Gemini 3.1 was used in porting to COFF and WASM LLDs.
Commit: d74f098a305b39f96d5455d301ceea512acadc62
https://github.com/llvm/llvm-project/commit/d74f098a305b39f96d5455d301ceea512acadc62
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
Log Message:
-----------
[DAG] isKnownNeverNaN - fallback to computeKnownFPClass check (#189476)
Remove ConstantFPSDNode handling from isKnownNeverNaN and fallback to
using computeKnownFPClass if there are no opcode matches in
isKnownNeverNaN
The test check changes are due to isKnownNeverNaN not handling
UNDEF/POISON but computeKnownFPClass does (POISON in particular now
returns isKnownNeverNaN == true, preventing a ISD::FCANONICALIZE call in
expandFMINNUM_FMAXNUM).
Commit: 74c42432252de25caa51deaa38458d734622a579
https://github.com/llvm/llvm-project/commit/74c42432252de25caa51deaa38458d734622a579
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/dev/undefined_behavior.rst
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/VISIT.h
A libc/hdr/types/posix_tnode.h
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/__action_closure_fn_t.h
A libc/include/llvm-libc-types/__action_fn_t.h
A libc/include/llvm-libc-types/__free_fn_t.h
A libc/include/llvm-libc-types/posix_tnode.h
M libc/include/search.yaml
M libc/src/__support/weak_avl.h
M libc/src/search/CMakeLists.txt
A libc/src/search/tdelete.cpp
A libc/src/search/tdelete.h
A libc/src/search/tdestroy.cpp
A libc/src/search/tdestroy.h
A libc/src/search/tfind.cpp
A libc/src/search/tfind.h
A libc/src/search/tsearch.cpp
A libc/src/search/tsearch.h
A libc/src/search/twalk.cpp
A libc/src/search/twalk.h
A libc/src/search/twalk_r.cpp
A libc/src/search/twalk_r.h
M libc/test/src/__support/weak_avl_test.cpp
M libc/test/src/search/CMakeLists.txt
A libc/test/src/search/tsearch_test.cpp
Log Message:
-----------
[libc][tsearch] add tsearch functions (#172625)
Commit: 5b00cdf8e18354764c8cdd27a8ad3f858afd76bb
https://github.com/llvm/llvm-project/commit/5b00cdf8e18354764c8cdd27a8ad3f858afd76bb
Author: Jason Molenda <jmolenda at apple.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwinDevice.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwinDevice.h
M lldb/source/Plugins/Platform/MacOSX/PlatformRemoteDarwinDevice.cpp
M lldb/unittests/Platform/PlatformMacOSXTest.cpp
Log Message:
-----------
[lldb][macOS] Recognize new layouts for DeviceSupport directories (#188646)
When debugging a remote Darwin device (iOS, macOS, etc), lldb needs to
find a local copy of all the system libraries (the system's shared
cache) so we don't need to read them over gdb-remote serial protocol at
the start of every debug session.
Xcode etc normally creates these expanded shared caches in
~/Library/Developer/Xcode/<OS> DeviceSupport/<OS VER> (<OS
BUILD>)/Symbols
So when lldb sees a file like /usr/lib/libSystem.B.dylib, it may find a
copy at in
~/L/D/Xcode/iOS DeviceSupport/26.2
(23B87)/Symbols/usr/lib/libSystem.B.dylib
There may be multiple expanded shared caches in these DeviceSupport
directories, so we try to parse the "os version" and "os build" out of
the filepath name, and look in a directory that matches the target
device's OS Version as an optimization, to avoid opening the given file
in other DeviceSupport directories.
There is a new layout where the cpu arch exists as a subdirectory under
the "<OS VER> (<OS BUILD>)" directory. e.g.
~/L/D/Xcode/iOS DeviceSupport/26.2 (23B87)/arm64e/Symbols/...
and it is possible that we could have multiple arch names for a given
build -- for instance, an Apple Watch that can have either arm64e or
arm64_32 shared caches.
The existing code also had a very simplistic way of parsing "<OS VER>
(<OS BUILD>)" from the directory name that hasn't been kept up to date
with how the directory names have changed over the years. We have some
like "Watch4,2 10.0 (21R329)" or "10.0 (21R329) universal" which may not
parse with the older parser.
This PR looks for target arch subdirs under the given directories,
passes the os version/build version string separately because it may not
be the final component in the directory name any more, and updates the
directory parser that finds the version and build numbers.
rdar://171821410
Commit: 18e695890306c6824cc15779e1acb7e5956cbec1
https://github.com/llvm/llvm-project/commit/18e695890306c6824cc15779e1acb7e5956cbec1
Author: Alex Voicu <alexandru.voicu at amd.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/AMDGPUTypes.def
M clang/include/clang/Basic/Builtins.def
M clang/include/clang/Basic/BuiltinsAMDGPU.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/SemaAMDGPU.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/Type.cpp
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CodeGenTypes.cpp
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/Sema/JumpDiagnostics.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaAMDGPU.cpp
M clang/lib/Sema/SemaCast.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaOverload.cpp
A clang/test/CodeGen/amdgpu-builtin-is-invocable.c
A clang/test/CodeGen/amdgpu-builtin-processor-is.c
A clang/test/CodeGen/amdgpu-feature-builtins-invalid-use.cpp
M clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
M clang/test/CodeGenHIP/spirv-amdgcn-dpp-const-fold.hip
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx10.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-vi.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
A clang/test/SemaHIP/amdgpu-feature-builtins-cant-jump.hip
A clang/test/SemaHIP/amdgpu-feature-builtins-return-type-deduction.hip
A clang/test/SemaHIP/amdgpu-feature-predicate.hip
A clang/test/SemaHIP/amdgpu-feature-predicates-guard-use.hip
A clang/test/SemaHIP/amdgpu-is-invocable.hip
A clang/test/SemaHIP/amdgpu-processor-is.hip
M clang/utils/TableGen/ClangBuiltinsEmitter.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
M llvm/lib/Target/SPIRV/SPIRVPrepareGlobals.cpp
A llvm/test/CodeGen/SPIRV/SpecConstants/amdgcnspirv-feature-predicate-specconstant.ll
A llvm/test/CodeGen/SPIRV/passes/SPIRVPrepareGlobals-predicate-id-string.ll
Log Message:
-----------
[SPIRV][AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (#134016)
This change adds two builtins for AMDGPU:
- `__builtin_amdgcn_processor_is`, which is similar in observable
behaviour with `__builtin_cpu_is`, except that it is never "evaluated"
at run time;
- `__builtin_amdgcn_is_invocable`, which is behaviourally similar with
`__has_builtin`, except that it is not a macro (i.e. not evaluated at
preprocessing time).
Neither of these are `constexpr`, even though when compiling for
concrete (i.e. `gfxXXX` / `gfxXXX-generic`) targets they get evaluated
in Clang, so they shouldn't tear the AST too badly / at all for
multi-pass compilation cases like HIP. They can only be used in specific
contexts (as args to control structures).
The motivation for adding these is two-fold:
- as a nice to have, it provides an AST-visible way to incorporate
architecture specific code, rather than having to rely on macros and the
preprocessor, which burn in the choice quite early;
- as a must have, it allows featureful AMDGCN flavoured SPIR-V to be
produced, where target specific capability is guarded and chosen or
discarded when finalising compilation for a concrete target; this is
built atop the Speciali\ation Constant concept which is described in the
SPIR-V specification under section [2.12
Specialization](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#_specialization_2)
I've tried to keep the overall footprint of the change small. The
changes to Sema are a bit unpleasant, but there was a strong desire to
have Clang validate these, and to constrain their uses, and this was the
most compact solution I could come up with (suggestions welcome).
---------
Co-authored-by: Juan Manuel Martinez CaamaƱo <jmartinezcaamao at gmail.com>
Co-authored-by: Voicu <avoicu at amd.com>
Commit: 02402beefec61c5947c9d3bec60626a4afd860a8
https://github.com/llvm/llvm-project/commit/02402beefec61c5947c9d3bec60626a4afd860a8
Author: vporpo <vasileios.porpodas at amd.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
Log Message:
-----------
[SandboxVec][VecUtils] Lane Enumerator (#188355)
This patch introduces an iterator that helps us iterate over lane-value
pairs in a range. For example, given a container `(i32 %v0, <2 x i32>
%v1, i32 %v2)` we get:
```
Lane Value
0 %v0
1 %v1
3 %v2
```
We use this iterator to replace the lane counting logic in
BottomUpVec.cpp.
Commit: c93049ef504f942af0f884ce8a5efc21df21d131
https://github.com/llvm/llvm-project/commit/c93049ef504f942af0f884ce8a5efc21df21d131
Author: Vasileios Porpodas <vasileios.porpodas at amd.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
Log Message:
-----------
Revert "[SandboxVec][VecUtils] Lane Enumerator (#188355)"
This reverts commit 02402beefec61c5947c9d3bec60626a4afd860a8.
Commit: 7ec77f8460e15cf680824d7d95dd11d34eb6bd42
https://github.com/llvm/llvm-project/commit/7ec77f8460e15cf680824d7d95dd11d34eb6bd42
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 54b7230 (#189487)
This fixes 54b723097b39b536eb7d1d6947b65d53a096ed47.
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 9c37e348df91e6aa46c3e472c591b99f7535a79e
https://github.com/llvm/llvm-project/commit/9c37e348df91e6aa46c3e472c591b99f7535a79e
Author: Henry Jiang <henry_jiang2 at apple.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FastISel.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
Log Message:
-----------
[AArch64][NFC] Move `isZExtLoad/isSExtLoad` from `AArch64FastISel` to `AArch64InstrInfo` (#189486)
Move the static function `isZExtLoad` and `isSExtLoad` helper functions
from `AArch64FastISel` into `AArch64InstrInfo` to be reused by other
passes.
Commit: 27b9ea5ea090aa1c64baf7b3f619c72e3e15713f
https://github.com/llvm/llvm-project/commit/27b9ea5ea090aa1c64baf7b3f619c72e3e15713f
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.cpp
Log Message:
-----------
[MLIR][SparseTensor] Fix domination violation in co-iteration for dense iterators (#188959)
In exitWhileLoop, random-accessible (dense) iterators were being located
using whileOp.getResults().back() while the insertion point was still
inside the while loop's after block. This caused a domination violation:
the ADDI created by locate() was inside the after block, but it was
later used (via derefImpl's SUBI) after the while loop exits.
Move the locate() calls for random-accessible iterators to after
builder.setInsertionPointAfter(whileOp), where the while results are
properly in scope.
Fixes 10 failing tests under MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS.
Assisted-by: Claude Code
Co-authored-by: Claude Sonnet 4.6 <noreply at anthropic.com>
Commit: e097875417bc5458e22d594276dd645a137ea91d
https://github.com/llvm/llvm-project/commit/e097875417bc5458e22d594276dd645a137ea91d
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/lib/Dialect/SparseTensor/Transforms/SparseAssembler.cpp
Log Message:
-----------
[MLIR][SparseTensor] Fix fingerprint changes in SparseFuncAssembler (#188958)
SparseFuncAssembler::matchAndRewrite was calling funcOp.setName(),
funcOp.setPrivate(), and funcOp->removeAttr() directly without notifying
the rewriter, causing "operation fingerprint changed" errors under
MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS.
Wrap all in-place funcOp mutations with rewriter.modifyOpInPlace.
Assisted-by: Claude Code
Fix a failure present with MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS=ON.
Co-authored-by: Claude Sonnet 4.6 <noreply at anthropic.com>
Commit: 5da2546594f8555d5d283e3ee3cda14bc5a80eec
https://github.com/llvm/llvm-project/commit/5da2546594f8555d5d283e3ee3cda14bc5a80eec
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/test/Dialect/SCF/canonicalize.mlir
Log Message:
-----------
[mlir][scf] Fix FoldTensorCastOfOutputIntoForallOp write order bug (#189162)
`FoldTensorCastOfOutputIntoForallOp` incorrectly updated the
destinations of `tensor.parallel_insert_slice` ops in the `in_parallel`
block by zipping `getYieldingOps()` with `getRegionIterArgs()`
positionally. This assumed that the i-th yielding op writes to the i-th
shared output, which is not required by the IR semantics. When slices
are written to shared outputs in non-positional order, the
canonicalization would silently reverse the write targets, producing
incorrect output.
Fix by replacing the positional zip with a per-destination check: for
each yielding op's destination operand, if it is a `tensor.cast` result
whose source is one of the new `scf.forall` region iter args (i.e., a
cast we introduced to bridge the type change), replace the destination
with the cast's source directly. This correctly handles all orderings.
Add a regression test that exercises the multi-result case where
`parallel_insert_slice` ops write to shared outputs in non-sequential
order.
Fixes #172981
Assisted-by: Claude Code
Commit: acbf3f318694a4f3c382caf040cf586e1ff02c5f
https://github.com/llvm/llvm-project/commit/acbf3f318694a4f3c382caf040cf586e1ff02c5f
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/lib/Conversion/SCFToControlFlow/SCFToControlFlow.cpp
M mlir/test/Conversion/SCFToControlFlow/convert-to-cfg.mlir
Log Message:
-----------
[MLIR][SCF] Fix scf.index_switch lowering to preserve large case values (#189230)
`IndexSwitchLowering` stored case values as `SmallVector<int32_t>`,
which silently truncated any `int64_t` case value larger than INT32_MAX
(e.g. `4294967296` became `0`). The `cf.switch` flag was also created
via `arith.index_cast index -> i32`, losing the upper 32 bits on 64-bit
platforms.
Fix: store case values as `SmallVector<APInt>` with 64-bit width, cast
the index argument to `i64`, and use the `ArrayRef<APInt>` overload of
`cf::SwitchOp::create` so the resulting switch correctly uses `i64` case
values and flag type.
Fixes #111589
Assisted-by: Claude Code
Commit: 7b52dd6ad9ac16987d1646b651e5b1fd13b7cb41
https://github.com/llvm/llvm-project/commit/7b52dd6ad9ac16987d1646b651e5b1fd13b7cb41
Author: Michael Jones <michaelrj at google.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M libc/src/__support/wchar/CMakeLists.txt
M libc/src/__support/wchar/character_converter.h
M libc/src/__support/wchar/mbrtowc.cpp
M libc/src/__support/wchar/mbrtowc.h
M libc/src/__support/wchar/mbsnrtowcs.h
M libc/src/__support/wchar/string_converter.h
M libc/src/__support/wchar/wcrtomb.h
M libc/src/__support/wchar/wcsnrtombs.h
Log Message:
-----------
[libc][NFC] Add LIBC_INLINE and cleanup wchar internals (#188856)
Some of the functions were missing LIBC_INLINE and some of the variable
names were less descriptive than I liked. This PR fixes both as well as
cleaning up dependencies.
Commit: 89d5d502e88c9fa1de56e066e89b942ee9be20de
https://github.com/llvm/llvm-project/commit/89d5d502e88c9fa1de56e066e89b942ee9be20de
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M llvm/include/llvm/IR/Intrinsics.h
M llvm/lib/IR/Intrinsics.cpp
Log Message:
-----------
[NFC][LLVM] Rename `IITDescriptor` fields to confirm to LLVM CS (#189448)
Rename fields of `IITDescriptor` to conform to LLVM coding standards
naming conventions.
Commit: 8ca1cb7a96217002bd649a95142d981f570faffd
https://github.com/llvm/llvm-project/commit/8ca1cb7a96217002bd649a95142d981f570faffd
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
Log Message:
-----------
[AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (part 2) (#189503)
(This is the change message for 306e86be5, which GitHub unhelpfully discarded
when I enabled "auto-merge" when all tests had passed. It merged my change
and didn't merge the detailed commit message which I had carefully written(!)
So this is an NFC change, for those in the future looking for the lost message,
which explains the changes in 306e86be5)
-------------
Correct the `TLBI` system operand definitions so the emitted aliases are
generated from a single data table per feature group. The TLBI data is now
written once as anonymous `TLBI<...>` entries inside a defvar list, and we
iterate over it with a foreach to define those entries.
Hopefully this is clearer and more future-proof, since it is a complex set of
interactions between `tlbi`/`tlbip` with `*nXS` variants, and differing gating.
The gating was incorrect before. The gating is now:
- `FeatureTLB_RMI`, `FeatureRME`, and `FeatureTLBIW` gate only TLBI aliases
- non-TLBIW `TLBI` ...nXS aliases are `FeatureXS-only`
- `TLBIW` ...nXS aliases are `FeatureTLBIW`-only
- all `TLBIP` aliases, including ...nXS, are `FeatureD128`-only
Update testcases accordingly (`llvm/test/MC/AArch64/armv8.7a-xs.s` had
inconsistent use of hyphen and underscore for error checking)
Commit: b85492b3d38724377186a37925dd3abf3258efcc
https://github.com/llvm/llvm-project/commit/b85492b3d38724377186a37925dd3abf3258efcc
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot8.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for sudot4/sudot8 (#189104)
Commit: 12319b373a5f4b36c09165ed7f8e967bbb14b265
https://github.com/llvm/llvm-project/commit/12319b373a5f4b36c09165ed7f8e967bbb14b265
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M clang/lib/CodeGen/CGCall.cpp
M clang/test/CodeGenCXX/destructor-dead-on-return.cpp
M clang/test/CodeGenCXX/microsoft-vector-deleting-dtors.cpp
M clang/test/CodeGenCXX/microsoft-vector-deleting-dtors2.cpp
M clang/test/CodeGenCXX/ms-vdtors-devirtualization.cpp
M clang/test/OpenMP/for_reduction_codegen_UDR.cpp
M clang/test/utils/update_cc_test_checks/Inputs/explicit-template-instantiation.cpp.expected
Log Message:
-----------
[Clang] More aggressively mark this* dead_on_return in destructors (#183347)
Now also mark the this pointer dead_on_return for classes with a
non-zero number of base classes. We saw a limited number of failures
internally due to this change, so it doesn't seem like there are too
many problems with real world deployment.
Commit: 96bd7b6e152387c6d1ccb4b0e392773aa1bdec1e
https://github.com/llvm/llvm-project/commit/96bd7b6e152387c6d1ccb4b0e392773aa1bdec1e
Author: Demetrius Kanios <demetrius at kanios.net>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AMDGPU/R600ISelLowering.h
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[CodeGen] Add additional params to `TargetLoweringBase::getTruncStoreAction` (#187422)
The truncating store analogue of #181104.
Adds `Alignment` and `AddrSpace` parameters to
`TargetLoweringBase::getTruncStoreAction` and dependents, and introduces
a `getCustomTruncStoreAction` hook for targets to customize legalization
behavior using this new information.
This change is fully backwards compatible from the target's point of
view, with `setTruncStoreAction` having identical functionality. The
change is purely additive.
Commit: b255e78cb9bf40ecc4c4a28ab81887de68b8afc3
https://github.com/llvm/llvm-project/commit/b255e78cb9bf40ecc4c4a28ab81887de68b8afc3
Author: Jim Lin <jim at andestech.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/include/lldb/Target/Process.h
Log Message:
-----------
[lldb] Fix copy-paste error in SetPrivateRunLockToRunning (#189322)
SetPrivateRunLockToRunning incorrectly delegated to
SetPrivateRunLockToStopped instead of SetPrivateRunLockToRunning,
causing the private run lock to never transition to the running state on
process resume.
Co-authored-by: Claude Opus 4.6 (1M context) <noreply at anthropic.com>
Commit: 47e3f42bc75d006ecaf820211cfff560681ab9d9
https://github.com/llvm/llvm-project/commit/47e3f42bc75d006ecaf820211cfff560681ab9d9
Author: Vasileios Porpodas <vasileios.porpodas at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
Log Message:
-----------
Reapply "[SandboxVec][VecUtils] Lane Enumerator (#188355)"
This reverts commit c93049ef504f942af0f884ce8a5efc21df21d131.
Commit: 35f89458fa2871b7590c115c9afea764dfc11c02
https://github.com/llvm/llvm-project/commit/35f89458fa2871b7590c115c9afea764dfc11c02
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M mlir/include/mlir/Interfaces/SideEffectInterfaces.h
M mlir/lib/Transforms/CSE.cpp
M mlir/test/Analysis/test-alias-analysis-modref.mlir
M mlir/test/IR/test-side-effects.mlir
M mlir/test/Transforms/cse.mlir
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/unittests/Interfaces/SideEffectInterfacesTest.cpp
Log Message:
-----------
[mlir] Made DefaultResource the root of memory resource hierarchy. (#187423)
DefaultResource is made the root of the memory resource hierarchy,
so now it overlaps with all resources.
RFC:
https://discourse.llvm.org/t/rfc-mlir-memory-region-hierarchy-for-mlir-side-effects/89811/32
Commit: ac12b327b2cfaaa689e975652320e85b5e37e5b2
https://github.com/llvm/llvm-project/commit/ac12b327b2cfaaa689e975652320e85b5e37e5b2
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
Log Message:
-----------
[RISCV] Check hasVInstructions() rather than hasStdExtZbb() for UMAX/UMIN/SMAX/SMIN combines. (#189506)
The combines are related to combining min/max with vector reductions. I
don't think it matters if Zbb is enabled.
I did not merge this with other hasVInstructions() because I have a P
extension patch coming after this that will need to separate them.
Commit: 9de3ebde1c8c0f5d51fe8906fcb8a88899970031
https://github.com/llvm/llvm-project/commit/9de3ebde1c8c0f5d51fe8906fcb8a88899970031
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Avoid creating unnecessary node. Add missing break to switch. NFC (#189511)
Commit: 227edfb2f406e835b8ec91f0fce44d4f344a808c
https://github.com/llvm/llvm-project/commit/227edfb2f406e835b8ec91f0fce44d4f344a808c
Author: Mingjie Xu <xumingjie.enna1 at bytedance.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
M llvm/include/llvm/Transforms/Utils/BypassSlowDivision.h
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp
M llvm/lib/Transforms/Utils/BypassSlowDivision.cpp
M llvm/test/CodeGen/PowerPC/atomics-regression.ll
M llvm/test/CodeGen/RISCV/branch_zero.ll
M llvm/test/CodeGen/X86/apx/reloc-opt.ll
M llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debug-info-inseltpoison.ll
M llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debug-info.ll
Log Message:
-----------
[CodeGenPrepare][NFC] Reland: Update the dominator tree instead of rebuilding it (#179040)
The original differential revision is https://reviews.llvm.org/D153638
Reverted in
https://github.com/llvm/llvm-project/commit/f5b5a30858f32e237636acd296b6d0f87c1dfe97
because of causing a clang crash.
This patch relands it with the crash fixed. Call `DTU->flush()` in each
iteration of `while (MadeChange)`
loop, flush all awaiting BasicBlocks deletion, and prevent iterator
invalidation.
Commit: e1aef5ed5f0c2a958c76bcff0708803ae0588efb
https://github.com/llvm/llvm-project/commit/e1aef5ed5f0c2a958c76bcff0708803ae0588efb
Author: Feng Zou <feng.zou at intel.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/X86/X86CompressEVEX.cpp
A llvm/test/CodeGen/X86/apx/compress-evex-negative-nf.mir
M llvm/test/TableGen/x86-instr-mapping.inc
M llvm/utils/TableGen/X86InstrMappingEmitter.cpp
Log Message:
-----------
[X86][APX] Remove NF entries in X86CompressEVEXTable (#189308)
NF (No-Flags) instructions should not compress to non-NF instructions,
as this would incorrectly modify flags behavior. The compression table
is only intended for encoding optimizations that preserve semantics.
This removes the incorrect NF entries that could have led to
miscompilation if the compression logic were applied.
Commit: 14ce208a45eb0673f8b28409eec0628ad809923b
https://github.com/llvm/llvm-project/commit/14ce208a45eb0673f8b28409eec0628ad809923b
Author: Shivam Gupta <shivam98.tkg at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lld/ELF/Arch/AArch64.cpp
A lld/test/ELF/aarch64-tls-dtprel.s
Log Message:
-----------
[LLD][AArch64] Handle R_AARCH64_TLS_DTPREL64 in non-alloc sections (#183962)
Clang plan to emit R_AARCH64_TLS_DTPREL64 in .debug_info (see PR
#146572). LLD currently fails to recognize this relocation.
This prevent the debugger from correctly locating TLS variables when
using the DWARF DW_OP_GNU_push_tls_address or DW_AT_location with DTPREL
offsets.
This patch adds support for R_AARCH64_TLS_DTPREL64, adds its mapping to
R_DTPREL.
Commit: 8e20a6dc866c54683f801d1ca041c6b3ba302485
https://github.com/llvm/llvm-project/commit/8e20a6dc866c54683f801d1ca041c6b3ba302485
Author: Shivam Gupta <shivam98.tkg at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp
M llvm/lib/Target/AArch64/AArch64TargetObjectFile.h
M llvm/test/DebugInfo/AArch64/tls-at-location.ll
Log Message:
-----------
[AArch64] Support TLS variables in debug info (#146572)
This adds an implementation of getDebugThreadLocalSymbol for AArch64 by
using AArch::S_DTPREL.
Fixes #83466
Commit: 1ec7e86b3a779df2a0af3f37e58c8f5b3a398d7f
https://github.com/llvm/llvm-project/commit/1ec7e86b3a779df2a0af3f37e58c8f5b3a398d7f
Author: Kewen Meng <kewen.meng at amd.com>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M clang/lib/CodeGen/BackendUtil.cpp
M lld/COFF/InputFiles.cpp
M lld/COFF/LTO.cpp
M lld/COFF/LTO.h
M lld/COFF/SymbolTable.cpp
M lld/ELF/Driver.cpp
M lld/ELF/LTO.cpp
M lld/ELF/LTO.h
R lld/test/COFF/lto-libcall-archive-bitcode.test
R lld/test/ELF/lto/libcall-archive-bitcode.test
R lld/test/wasm/lto/libcall-archive-bitcode.ll
M lld/wasm/LTO.cpp
M lld/wasm/LTO.h
M lld/wasm/SymbolTable.cpp
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/LTO/LTO.h
M llvm/include/llvm/LTO/LTOBackend.h
M llvm/lib/LTO/LTO.cpp
M llvm/lib/LTO/LTOBackend.cpp
M llvm/lib/LTO/LTOCodeGenerator.cpp
M llvm/lib/LTO/ThinLTOCodeGenerator.cpp
R llvm/test/LTO/Resolution/X86/libcall-external.ll
R llvm/test/LTO/Resolution/X86/libcall-in-thin-link.ll
R llvm/test/LTO/Resolution/X86/libcall-in-tu.ll
M llvm/tools/llvm-lto2/llvm-lto2.cpp
Log Message:
-----------
Revert "[LTO][LLD] Prevent invalid LTO libfunc transforms (#164916)"
This reverts commit 8b21fe60b43fe358321bca904ae307406725c002.
to unblock bot: https://lab.llvm.org/buildbot/#/builders/67/builds/1196
Commit: 42cc454777274a06933abcd098ec3281158717f9
https://github.com/llvm/llvm-project/commit/42cc454777274a06933abcd098ec3281158717f9
Author: Fangrui Song <i at maskray.me>
Date: 2026-03-30 (Mon, 30 Mar 2026)
Changed paths:
M lld/ELF/InputSection.cpp
M lld/ELF/InputSection.h
M lld/ELF/SyntheticSections.cpp
M lld/test/ELF/merge-piece-oob.s
Log Message:
-----------
[ELF] Optimize binary search in getSectionPiece (#187916)
Two optimizations to make getSectionPiece O(1) for common cases:
1. For non-string fixed-size merge sections, use direct computation
(offset / entsize) instead of binary search.
2. Pre-resolve piece indices for non-section Defined symbols during
splitSections. The piece index and intra-piece offset are packed
into Defined::value as ((pieceIdx+1) << 32) | intraPieceOffset,
replacing repeated binary searches (MarkLive, includeInSymtab,
getRelocTargetVA) with a single upfront resolution.
On x86-64, references to mergeable strings use local labels:
leaq .LC0(%rip), %rax # R_X86_64_PC32 .LC0-4
The relocations use non-section symbols and benefit from optimization 2.
On many other targets (e.g. AArch64), the addend is 0 and the assembler
adjusts such relocations to reference section symbols, which still use
binary search.
On a clang link (clang-relassert reproduce tarball, x86-64):
- --gc-sections: 1.05x as fast
Commit: 8a0c070309fcdc4f9fc2718b6a350f0de955f053
https://github.com/llvm/llvm-project/commit/8a0c070309fcdc4f9fc2718b6a350f0de955f053
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M libcxx/include/__hash_table
M libcxx/include/ext/hash_map
M libcxx/test/extensions/gnu/hash_map/copy.pass.cpp
R libcxx/test/extensions/gnu/hash_map/non_standard_layout.pass.cpp
R libcxx/test/extensions/gnu/hash_multimap/non_standard_layout.pass.cpp
Log Message:
-----------
[libc++] Revert recent changes to __hash_table and ext/hash_map (#189427)
This reverts commits 30084d74765c and 5b8c17580482. The second commit
was landed without proper review: not by fault of the submitter, but
because I mistakenly thought this was modifying something else entirely
that is unsupported. The first commit must also be reverted because it
is a breaking change without the second commit.
This corresponds to PRs #183223 and #188660, see those for more details.
Commit: d3224dc5da99877602f997c16bc5dffc775c5248
https://github.com/llvm/llvm-project/commit/d3224dc5da99877602f997c16bc5dffc775c5248
Author: NeKon69 <nobodqwe at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/Sema/SemaDeclCXX.cpp
A clang/test/FixIt/fixit-defaulted-comparison.cpp
Log Message:
-----------
[clang][Sema] Fix const FixIt placement after comparison operator member definition (#188093)
Update `InsertLoc` to use the token after the closing parenthesis
when adding `const` qualification to a comparison operator
Fixes #187887
Commit: 2e02135cec6aa56f780ef6b61799b50e6dd0d1a5
https://github.com/llvm/llvm-project/commit/2e02135cec6aa56f780ef6b61799b50e6dd0d1a5
Author: A. Jiang <de34 at live.cn>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M libcxx/docs/ReleaseNotes/23.rst
M libcxx/include/__bit_reference
A libcxx/test/std/containers/sequences/vector.bool/reference/builtin_address_of.pass.cpp
A libcxx/test/std/utilities/template.bitset/bitset.members/reference.builtin_address_of.pass.cpp
Log Message:
-----------
[libc++] Remove non-conforming `__bit_reference::operator&` (#188714)
The overloaded `operator&` caused non-conforming behavior when
- using `operator==` to compare "addresses" of proxy reference objects,
and
- relying on the exact type of `&ref`.
No deprecation warning is added, becaue it should be portable to write
`&ref` where `ref` is a proxy reference variable, and this patch just
corrects the behavior.
`__bit_const_reference::operator&` is kept, because when one defines
`_LIBCPP_ABI_BITSET_VECTOR_BOOL_CONST_SUBSCRIPT_RETURN_BOOL` to make the
libc++ implementation strategy conforming, the `operator&` will never be
exposed to users.
Commit: 3d96b36964e808b14c660bcbf248b9dc856d43a2
https://github.com/llvm/llvm-project/commit/3d96b36964e808b14c660bcbf248b9dc856d43a2
Author: pkarveti <pkarveti at qti.qualcomm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/include/llvm/Target/Target.td
M llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp
M llvm/test/CodeGen/Generic/reloc-none.ll
Log Message:
-----------
[Hexagon] Fix infinite loop in scheduler for RELOC_NONE instruction (#188690)
The llvm.reloc.none intrinsic (introduced in 5f08fb4d72f6) causes an
infinite loop when compiling for Hexagon target. The Hexagon scheduler's
hazard recognizer enters an infinite loop because RELOC_NONE
RELOC_NONE is a pseudo-instruction that doesn't correspond to real
hardware, but the Hexagon hazard recognizer was treating it as a regular
instruction requiring hardware resource allocation.
Mark RELOC_NONE as a meta-instruction and update Hexagon's hazard
recognizer to skip resource checks for meta-instructions, similar to how
it handles zero-cost instructions.
Commit: 035ae0261c7077f97541c662db5f30b6d81d0616
https://github.com/llvm/llvm-project/commit/035ae0261c7077f97541c662db5f30b6d81d0616
Author: Jim Lin <jim at andestech.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
Log Message:
-----------
[RISCV] Fix discarded return value in RISCVOperand::print for FRM (#189530)
The roundingModeToString() return value was not being written to the
output stream, causing FRM operands to print as "<frm: >" with no
rounding mode name in debug output.
Co-authored-by: Claude Opus 4.6 (1M context) <noreply at anthropic.com>
Commit: 5b2363a1027c3a172326d0f43a23fbbe5d70a304
https://github.com/llvm/llvm-project/commit/5b2363a1027c3a172326d0f43a23fbbe5d70a304
Author: Himadhith <79003240+Himadhith at users.noreply.github.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
A lib.out
M libcxx/test/std/thread/futures/futures.async/thread_create_failure.pass.cpp
A tmp.exe
Log Message:
-----------
[libc++][AIX] Fix force_thread_creation_failure by using RLIMIT_THREADS (#188787)
This patch fixes the test `force_thread_creation_failure.cpp` on AIX by
using platform specific `RLIMIT_THREADS` which helps in restricting the
thread creation as `RLIMIT_NPROC` on AIX restricts processes and not
threads.
---------
Co-authored-by: himadhith <himadhith.v at ibm.com>
Commit: f48425edca7ff9f43abb3ec7cb1252e7edfbf163
https://github.com/llvm/llvm-project/commit/f48425edca7ff9f43abb3ec7cb1252e7edfbf163
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/test/CodeGen/AMDGPU/fract-match.ll
Log Message:
-----------
AMDGPU: Match fract pattern with swapped edge case check (#189081)
A fract implementation can equivalently be written as
r = fmin(x - floor(x))
r = isnan(x) ? x : r;
r = isinf(x) ? 0.0 : r;
or:
r = fmin(x - floor(x));
r = isinf(x) ? 0.0 : r;
r = isnan(x) ? x : r;
Previously this only matched the previous form. Match
the case where the isinf check is the inner clamp. There are
a few more ways to write this pattern (e.g., move the clamp of
infinity to the input) but I haven't encountered that in the wild.
The existing code seems to be trying too hard to match noncanonical
variants of the pattern. Only handles the result that all 4 permutations
of compare and select produce out of instcombine.
Commit: 598f3535fa96ee599d670ede3840beeca570ec1f
https://github.com/llvm/llvm-project/commit/598f3535fa96ee599d670ede3840beeca570ec1f
Author: Luke Lau <luke at igalia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll
M llvm/test/CodeGen/AArch64/intrinsic-cttz-elts.ll
M llvm/test/CodeGen/AArch64/sve-mask-partition.ll
A llvm/test/CodeGen/AMDGPU/cttz-elts.ll
A llvm/test/CodeGen/PowerPC/cttz-elts.ll
A llvm/test/CodeGen/RISCV/rvv/cttz-elts-scalarize.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-elts.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-elts.ll
M llvm/test/CodeGen/X86/intrinsic-cttz-elts.ll
Log Message:
-----------
[SelectionDAG] Expand CTTZ_ELTS[_ZERO_POISON] and handle legalization (#188691)
This is a second attempt at "[SelectionDAG] Expand
CTTZ_ELTS[_ZERO_POISON] and handle splitting" (#188220)
That PR had to be reverted in 7d39664a6ae8daaf186b65578492244d96a50bf2
because we had crashes on AMDGPU since we didn't have scalarization
support, and other crashes on PowerPC because we didn't handle the case
when a vector needed widened. Tests for these are added in
AMDGPU/cttz-elts.ll, RISCV/rvv/cttz-elts-scalarize.ll and
PowerPC/cttz-elts.ll.
The former crash has been fixed by adding
DAGTypeLegalizer::ScalarizeVecOp_CTTZ_ELTS.
The second crash has been fixed by reworking
TargetLowering::expandCttzElts. The expansion for CTTZ_ELTS is nearly
identical to VECTOR_FIND_LAST_ACTIVE, except it uses a reverse step
vector and subtracts the result from VF. The easiest way to fix these
crashes without introducing regressions is to reuse the
VECTOR_FIND_LAST_ACTIVE expansion which already handles the case where
the vector needs widened.
This means that the node now needs to take in a boolean vector argument
and uses VSELECT instead of an AND to zero out inactive lanes, so the op
promotion code has also been shared.
Commit: fa136df3e74c1fd0b838352484aa38c471d21cbd
https://github.com/llvm/llvm-project/commit/fa136df3e74c1fd0b838352484aa38c471d21cbd
Author: Shivam Gupta <shivam98.tkg at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Object/RelocationResolver.cpp
M llvm/test/DebugInfo/AArch64/tls-at-location.ll
Log Message:
-----------
[llvm-dwarfdump] Support R_AARCH64_TLS_DTPREL64 in Object/RelocationResolver.cpp (#187649)
In patch https://github.com/llvm/llvm-project/pull/146572 we have plan
to emit R_AARCH64_TLS_DTPREL64. This give us the warning while using
llvm-dwarfdump for the object file which has tls variables -
warning: failed to compute relocation: R_AARCH64_TLS_DTPREL64, Invalid
data was encountered while parsing the file
To fix this warning we have mark the relocation as supported however
final absolute address of a TLS variable is determined at runtime,
resolving to the symbol's section-relative offset in the object file is
mitigate the warning.
Commit: dbad8a1e24c9e63041d91c8d5551225024b983eb
https://github.com/llvm/llvm-project/commit/dbad8a1e24c9e63041d91c8d5551225024b983eb
Author: Max Desiatov <m_desiatov at apple.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp
A llvm/test/CodeGen/WebAssembly/swiftasync-coroutine.ll
A llvm/test/CodeGen/WebAssembly/swifttailcc-musttail-no-tailcall.ll
A llvm/test/CodeGen/WebAssembly/swifttailcc-no-tailcall.ll
A llvm/test/CodeGen/WebAssembly/swifttailcc.ll
Log Message:
-----------
Wasm: add support for `swifttailcc` calling convention (#188296)
Wasm backend already supports tail calls where available, we only need
to enable corresponding branches for this calling convention.
Commit: 7365bfb3e0650918f7272a0817785c6c01d2feda
https://github.com/llvm/llvm-project/commit/7365bfb3e0650918f7272a0817785c6c01d2feda
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir
M llvm/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir
M llvm/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir
M llvm/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir
Log Message:
-----------
[X86][GISel] Avoid creating subreg def operands in emitInsertSubreg (#189408)
emitInsertSubreg builds a COPY with a subregister def operand, but these
probably should not be allowed in SSA MIR. Change it to build an
equivalent use of INSERT_SUBREG instead.
Commit: 6e2e06f98e164be53528ac19c7a307e92caa53eb
https://github.com/llvm/llvm-project/commit/6e2e06f98e164be53528ac19c7a307e92caa53eb
Author: Ruoyu Qiu <cabbaken at outlook.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/include/llvm/Analysis/DependenceAnalysis.h
M llvm/lib/Analysis/DependenceAnalysis.cpp
Log Message:
-----------
[DA] Refactor the signature of the Exact RDIV test (NFCI) (#189535)
Commit: 0f75ecf2326d70394026277d9b40f6e53434c6da
https://github.com/llvm/llvm-project/commit/0f75ecf2326d70394026277d9b40f6e53434c6da
Author: David Spickett <david.spickett at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/include/lldb/Target/Target.h
M lldb/source/Target/Target.cpp
Log Message:
-----------
[lldb] Only create RegisterTypeBuilderClang plugin once (#189393)
This plugin creates types based on information from target XML, which is
parsed only once per session. It has internal logic to reuse created
types, but the plugin itself was being remade every time a type was
requested.
Commit: 0c2c3f05ff688a245caf95af0f6c5e75b8ae27f8
https://github.com/llvm/llvm-project/commit/0c2c3f05ff688a245caf95af0f6c5e75b8ae27f8
Author: Endre FĆ¼lƶp <endre.fulop at sigmatechnology.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/test/Analysis/bstring.cpp
Log Message:
-----------
[analyzer][NFC] Reorganize bstring.cpp tests (#188709)
This change eliminates preprocessor-based suppression of test cases by
introducing multi-prefix verify options to run-lines. This slightly
increases coverage.
Commit: 199e5b71446895204f2912ce5d68b8019d3b78c9
https://github.com/llvm/llvm-project/commit/199e5b71446895204f2912ce5d68b8019d3b78c9
Author: Himadhith <79003240+Himadhith at users.noreply.github.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
R lib.out
R tmp.exe
Log Message:
-----------
[NFC] Remove stray files from top level directory (#189563)
Added untracked files into the top level directory by mistake, reverting
the change in this PR.
Co-authored-by: himadhith <himadhith.v at ibm.com>
Commit: fbfb83978cdc4e22996a26b4319d6df1514f08c6
https://github.com/llvm/llvm-project/commit/fbfb83978cdc4e22996a26b4319d6df1514f08c6
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/MachineVerifier.cpp
Log Message:
-----------
[MachineVerifier] Disallow subregister defs in SSA form (#189403)
Commit: f76f41f7027a4e96bac040f0b1b7f4cead0d2488
https://github.com/llvm/llvm-project/commit/f76f41f7027a4e96bac040f0b1b7f4cead0d2488
Author: Mel Chen <mel.chen at sifive.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dbg-tail-folding-by-evl.ll
M llvm/test/Transforms/LoopVectorize/RISCV/predicated-reverse-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll
M llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Log Message:
-----------
[VPlan] Extract reverse mask from reverse accesses (#155579)
Following #146525, separate the reverse mask from reverse access
recipes.
At the same time, remove the unused member variable `Reverse` from
`VPWidenMemoryRecipe`.
This will help to reduce redundant reverse mask computations by
VPlan-based common subexpression elimination.
Commit: 63e0ab7b4b51db7d93bf247b645c33b63f8ef747
https://github.com/llvm/llvm-project/commit/63e0ab7b4b51db7d93bf247b645c33b63f8ef747
Author: Luke Lau <luke at igalia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
Log Message:
-----------
[RISCV] Explicitly list supported VP intrinsics. NFC (#189547)
In preparation for splitting off #179622, list all vp intrinsics in a
list. Future PRs will remove intrinsics from this list when the
corresponding codegen support is removed.
Commit: f59d6f734e3d18fe37d0a2d7806479ee1be8de37
https://github.com/llvm/llvm-project/commit/f59d6f734e3d18fe37d0a2d7806479ee1be8de37
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/12-12-11-if-conv.ll
M llvm/test/Transforms/LoopVectorize/2012-10-20-infloop.ll
M llvm/test/Transforms/LoopVectorize/2012-10-22-isconsec.ll
M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.ll
M llvm/test/Transforms/LoopVectorize/ARM/arm-unroll.ll
M llvm/test/Transforms/LoopVectorize/ARM/gcc-examples.ll
M llvm/test/Transforms/LoopVectorize/ARM/width-detect.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/reg-usage.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-dot-printing.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-stress-test-no-explict-vf.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i32.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i64.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i8.ll
M llvm/test/Transforms/LoopVectorize/X86/avx1.ll
M llvm/test/Transforms/LoopVectorize/X86/conversion-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/X86/gather_scatter.ll
M llvm/test/Transforms/LoopVectorize/X86/gcc-examples.ll
M llvm/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll
M llvm/test/Transforms/LoopVectorize/X86/int128_no_gather.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave_short_tc.ll
M llvm/test/Transforms/LoopVectorize/X86/min-trip-count-switch.ll
M llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
M llvm/test/Transforms/LoopVectorize/X86/parallel-loops-after-reg2mem.ll
M llvm/test/Transforms/LoopVectorize/X86/parallel-loops.ll
M llvm/test/Transforms/LoopVectorize/X86/tail_folding_and_assume_safety.ll
M llvm/test/Transforms/LoopVectorize/X86/unroll-pm.ll
M llvm/test/Transforms/LoopVectorize/X86/unroll-small-loops.ll
M llvm/test/Transforms/LoopVectorize/X86/unroll_selection.ll
M llvm/test/Transforms/LoopVectorize/X86/veclib-calls.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-profitable.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-store-accesses-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/align.ll
M llvm/test/Transforms/LoopVectorize/bzip_reverse_loops.ll
M llvm/test/Transforms/LoopVectorize/calloc.ll
M llvm/test/Transforms/LoopVectorize/cpp-new-array.ll
M llvm/test/Transforms/LoopVectorize/float-reduction.ll
M llvm/test/Transforms/LoopVectorize/gcc-examples.ll
M llvm/test/Transforms/LoopVectorize/i8-induction.ll
M llvm/test/Transforms/LoopVectorize/if-conv-crash.ll
M llvm/test/Transforms/LoopVectorize/if-conversion-reduction.ll
M llvm/test/Transforms/LoopVectorize/if-conversion.ll
M llvm/test/Transforms/LoopVectorize/increment.ll
M llvm/test/Transforms/LoopVectorize/loop-legality-checks-remarks.ll
M llvm/test/Transforms/LoopVectorize/memdep.ll
M llvm/test/Transforms/LoopVectorize/metadata-unroll.ll
M llvm/test/Transforms/LoopVectorize/metadata-width.ll
M llvm/test/Transforms/LoopVectorize/multiple-address-spaces.ll
M llvm/test/Transforms/LoopVectorize/no_int_induction.ll
M llvm/test/Transforms/LoopVectorize/no_outside_user.ll
M llvm/test/Transforms/LoopVectorize/non-const-n.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_test1.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_test2.ll
M llvm/test/Transforms/LoopVectorize/pr30654-phiscev-sext-trunc.ll
M llvm/test/Transforms/LoopVectorize/pr32859.ll
M llvm/test/Transforms/LoopVectorize/pseudoprobe.ll
M llvm/test/Transforms/LoopVectorize/ptr_loops.ll
M llvm/test/Transforms/LoopVectorize/read-only.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-address-space.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-readonly-address-space.ll
M llvm/test/Transforms/LoopVectorize/runtime-check.ll
M llvm/test/Transforms/LoopVectorize/same-base-access.ll
M llvm/test/Transforms/LoopVectorize/scalar-select.ll
M llvm/test/Transforms/LoopVectorize/simple-unroll.ll
M llvm/test/Transforms/LoopVectorize/small-loop.ll
M llvm/test/Transforms/LoopVectorize/start-non-zero.ll
M llvm/test/Transforms/LoopVectorize/struct_access.ll
M llvm/test/Transforms/LoopVectorize/unroll-novec-memcheck-metadata.ll
M llvm/test/Transforms/LoopVectorize/unroll_novec.ll
M llvm/test/Transforms/LoopVectorize/write-only.ll
Log Message:
-----------
[LV][NFC] Remove more function attributes from tests (#188185)
Following on from PR #188091 I've also removed the following function
attributes from tests:
nounwind uwtable ssp
as they didn't make any difference to the tests.
Commit: a8a659458d4ad9116d652ca4eccb77d6cd673883
https://github.com/llvm/llvm-project/commit/a8a659458d4ad9116d652ca4eccb77d6cd673883
Author: David Spickett <david.spickett at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/include/lldb/Target/MemoryRegionInfo.h
M lldb/unittests/Process/Utility/LinuxProcMapsTest.cpp
M lldb/unittests/Process/Utility/MemoryTagManagerAArch64MTETest.cpp
M lldb/unittests/Process/minidump/MinidumpParserTest.cpp
Log Message:
-----------
[lldb] Change MemoryRegionInfo::SetIsShadowStack into a "builder" method (#189565)
Meaning a method on an object, which returns a reference to self.
I am doing this because it was pointed out to me that MemoryRegionInfo
has lots of construction paramaters, and most of the time, we want the
default value for most of the things.
So now we can do:
MemoryRegionInfo(...); // Shadow stack is "don't know".
MemoryRegionInfo(...).SetIsShadowStack(eNo) // Shadow stack is "no".
Which removes one parameter from every use of the constructor.
Along the way I realised that the shadow stack "ss" flag is only tested
by the Guarded Control Stack tests, which only run on specific Arm
hardware. I've added a new "ss" test to LinuxProcMapsTest, which will
run on any system.
Commit: bb3bf9f94b4235c8b81087ede1af442b5066b075
https://github.com/llvm/llvm-project/commit/bb3bf9f94b4235c8b81087ede1af442b5066b075
Author: Hans Wennborg <hans at hanshq.net>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/include/llvm/MC/MCAssembler.h
M llvm/lib/MC/MCAssembler.cpp
M llvm/test/MC/ELF/relax-branch-align.s
R llvm/test/MC/X86/align-branch-convergence.s
Log Message:
-----------
Revert "[MC] Fuse relaxation and layout into a single forward pass" (#189548)
Reverts llvm/llvm-project#184544 due to build failures and binary size
regressions; see comments on the PR.
Even if the failure to fixup CBZ instructions is due to a previously
existing problem, it was triggered by this PR. And the unnecessary
widening of the LBR instructions seems like a bad regression in itself.
Commit: 64eeafad7090d71f809f8e1806ad3b141f8de026
https://github.com/llvm/llvm-project/commit/64eeafad7090d71f809f8e1806ad3b141f8de026
Author: Ruoyu Qiu <cabbaken at outlook.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/test/Analysis/DependenceAnalysis/exact-rdiv-addrec-wrap.ll
Log Message:
-----------
[DA] Check nsw flags for addrecs in the Exact RDIV test (#189536)
This patch adds a check to ensure that the addrecs have nsw flags at the
beginning of the Exact SIV test. If either of them doesn't have, the
analysis bails out. This check is necessary because the subsequent
process in the Exact SIV test assumes that they don't wrap.
Commit: ad0cd387c0e9458e54db7817b57f822cc4d14dec
https://github.com/llvm/llvm-project/commit/ad0cd387c0e9458e54db7817b57f822cc4d14dec
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/records.cpp
Log Message:
-----------
[clang][bytecode] Fix a crash with void declarations (#189334)
The `chk` decl is erroneous, but we shouldn't crash.
Commit: 7ad564e54b42a921a70cd0d0f712dd86f61a697c
https://github.com/llvm/llvm-project/commit/7ad564e54b42a921a70cd0d0f712dd86f61a697c
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
Log Message:
-----------
[MLIR][MemRef] Fix LoadOpOfExpandShapeOpFolder returning failure after IR change (#188964)
LoadOpOfExpandShapeOpFolder<vector::TransferReadOp>::matchAndRewrite
called resolveSourceIndicesExpandShape (which creates
AffineLinearizeIndexOp ops via the rewriter) before checking whether the
vector::TransferReadOp preconditions hold. When those checks failed
(sourceRank < vectorRank or permutation map mismatch), the pattern
returned failure() after already modifying the IR, triggering "pattern
returned failure but IR did change" under
MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS.
Fix by hoisting the vector::TransferReadOp precondition checks to before
the resolveSourceIndicesExpandShape call. The source rank is derived
from expandShapeOp.getViewSource()'s type (no IR creation needed), and
the permutation map check only uses op attributes. Only if all checks
pass do we proceed to create the linearized-index ops.
Assisted-by: Claude Code
Fix a failure present with MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS=ON.
Commit: c592eba498a2a62101d503b1b32505fb292e6b51
https://github.com/llvm/llvm-project/commit/c592eba498a2a62101d503b1b32505fb292e6b51
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Use RPOT in CSE, fixing potential crash (#187548)
A CSE crash is observed arising from outdated hash values unless we
forbid replacements in successor phis in blocks that are not dominated
by the def: the crash is observed when there is a block with CSE'able
phis with CSE'able incoming values, with incoming values coming from a
non-dominating block, under the condition that the block with the phis
is visited before the non-dominating block. It is unfortunately
impossible to write a test case showing a crash at present, but crashes
do occur when attempting to CSE DerivedIV recipes. The root cause of the
crash is visiting a non-dominated use before a def, and hence would be
fixed by a reverse post-order traversal.
Fixes #187499.
Co-authored-by: Luke Lau <luke at igalia.com>
Commit: 47f3d90dacb92ac2281ae259bd3be6584b386253
https://github.com/llvm/llvm-project/commit/47f3d90dacb92ac2281ae259bd3be6584b386253
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/test/CodeGen/X86/int-to-fp-demanded.ll
Log Message:
-----------
[X86] int-to-fp-demanded.ll - add f16/bf16 signbit extraction tests (#189570)
Based off original test from #189129
Commit: b544ad57039588d0fe24a1f512202cc5c0bd3a67
https://github.com/llvm/llvm-project/commit/b544ad57039588d0fe24a1f512202cc5c0bd3a67
Author: Sergei Lebedev <185856+superbobry at users.noreply.github.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/docs/Bindings/Python.md
A mlir/include/mlir/Bindings/Python/PythonBindings.td
M mlir/test/mlir-tblgen/op-python-bindings.td
M mlir/tools/mlir-tblgen/OpPythonBindingGen.cpp
Log Message:
-----------
[MLIR] [Python] Added a way to extend MLIR->Python type mappings (#189368)
The idea is to use TableGen records for both custom type constraints and
attributes:
* `PythonTypeName` is for type constraints, while
* `PythonAttrType` is for attributes.
The key types differ between these two records. `PythonTypeName` is
keyed by C++ type because multiple type constraints map to the same C++
type (e.g. `I32` and `I64` both map to `::mlir::IntegerType`), so a
single entry covers all of them. `PythonAttrType` is keyed by TableGen
def name because different attributes can share the same C++ storage
type but need distinct Python types (e.g. `I32ArrayAttr` and
`StrArrayAttr` are both `::mlir::ArrayAttr`).
We could in theory reimplement `getPythonAttrName` using the same
approach, but I decided to leave it for future PRs.
Commit: c1b1a7178399b4fc8b0f777baeee21afbee69efa
https://github.com/llvm/llvm-project/commit/c1b1a7178399b4fc8b0f777baeee21afbee69efa
Author: Guray Ozen <guray.ozen at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M .github/new-prs-labeler.yml
Log Message:
-----------
[MLIR][NVVM] Add label for nvvm (#188216)
Commit: c6b255a693f042214e4f15dd7f69063d8315f0d7
https://github.com/llvm/llvm-project/commit/c6b255a693f042214e4f15dd7f69063d8315f0d7
Author: David Spickett <david.spickett at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/include/lldb/Target/MemoryRegionInfo.h
M lldb/unittests/Process/Utility/LinuxProcMapsTest.cpp
M lldb/unittests/Process/Utility/MemoryTagManagerAArch64MTETest.cpp
M lldb/unittests/Process/minidump/MinidumpParserTest.cpp
Log Message:
-----------
[lldb] Remove stack_memory from MemoryRegionInfo constructor (#189580)
Nothing passes anything but the default value here. Code that wants to
set it is starting with a default constructed info, and filling in the
fields one by one (the gdb-remote client for example).
Commit: ece53d2348a4176787a0648737e4b41f9d31b4b4
https://github.com/llvm/llvm-project/commit/ece53d2348a4176787a0648737e4b41f9d31b4b4
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/test/Analysis/DependenceAnalysis/exact-siv-overflow.ll
Log Message:
-----------
[DA] Update test `exact-siv-overflow.ll` (NFC) (#189572)
Revise the comment and the arguments to `--check-prefixes` in
`Analysis/DependenceAnalysis/exact-siv-overflow.ll` to match the style
of other similar tests in the directory.
Commit: f1b0a84003a03580ed4473e1f4201a415ddaf0fd
https://github.com/llvm/llvm-project/commit/f1b0a84003a03580ed4473e1f4201a415ddaf0fd
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
A llvm/test/Analysis/DependenceAnalysis/exact-rdiv-delta-overflow.ll
Log Message:
-----------
[DA] Add a test where the Exact RDIV test misses a dependency (NFC) (#189577)
Add a test to demonstrate the case where the Exact RDIV test misses a
dependency because the calculation of `Delta` overflows.
Commit: 0546b3f565b9350761f08574471ee3370fd8953c
https://github.com/llvm/llvm-project/commit/0546b3f565b9350761f08574471ee3370fd8953c
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/test/Analysis/DependenceAnalysis/gcd-miv-overflow.ll
Log Message:
-----------
[DA] Add test for GCD MIV missing dependency due to overflow (NFC) (#172002)
Add a test case where the GCD MIV test misses a dependency due to
overflow. This will be fixed by #172003 .
Commit: 2b439327026d45bf53e59159c8e40fccf87930b6
https://github.com/llvm/llvm-project/commit/2b439327026d45bf53e59159c8e40fccf87930b6
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/AST/DeclTemplate.cpp
A clang/test/SemaTemplate/GH188759.cpp
Log Message:
-----------
[clang] fix getReplacedTemplateParameter for function template specializations (#189559)
Commit: d43d9022c189210f0c3c52e34a47f3bd3edd4e43
https://github.com/llvm/llvm-project/commit/d43d9022c189210f0c3c52e34a47f3bd3edd4e43
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
Log Message:
-----------
[LV] Regen vplan-predicate-switch test with UTC (NFC) (#189581)
Commit: 0cecacd971a5471803b79f2b4a976ce75a2539b2
https://github.com/llvm/llvm-project/commit/0cecacd971a5471803b79f2b4a976ce75a2539b2
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/arm/adddf3.S
A compiler-rt/test/builtins/Unit/adddf3new_test.c
A compiler-rt/test/builtins/Unit/subdf3new_test.c
Log Message:
-----------
[compiler-rt][ARM] Optimized double precision FP add/sub (#179921)
The one new assembly source file, `arm/adddf3.S`, implements both
addition and subtraction via cross-branching after flipping signs, since
both operations must provide substantially the same logic. The new cmake
properties introduced in a prior commit are used to arrange that
including `adddf3.S` supersedes the C versions of both addition and
subtraction, and also informs the test suite that both functions are
available to test.
Commit: caecca035ab9fdccd1fd1b1b17452b415f89b366
https://github.com/llvm/llvm-project/commit/caecca035ab9fdccd1fd1b1b17452b415f89b366
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbplatformutil.py
M lldb/test/API/commands/target/create-deps/TestTargetCreateDeps.py
M lldb/test/API/functionalities/breakpoint/break_in_loaded_dylib/TestBreakInLoadedDylib.py
M lldb/test/API/functionalities/executable_first/TestExecutableFirst.py
M lldb/test/API/functionalities/load_after_attach/TestLoadAfterAttach.py
M lldb/test/API/functionalities/load_lazy/TestLoadUsingLazyBind.py
M lldb/test/API/functionalities/load_unload/TestLoadUnload.py
M lldb/test/API/symbol_ondemand/shared_library/TestSharedLibOnDemand.py
Log Message:
-----------
[lldb] add getFullLibName to PlatformContext (#188772)
This patch introduces `PlatformContext.getFullLibName` which returns the
full dylib name for any platform based on the base name of the dylib.
Example:
```
# Windows
PlatformContext.getFullLibName("Foo") -> "Foo.dll"
# Linux
PlatformContext.getFullLibName("Foo") -> "libFoo.so"
```
Commit: 5d2d17957514e682ee53e2512cd5ec7ffff6c1e7
https://github.com/llvm/llvm-project/commit/5d2d17957514e682ee53e2512cd5ec7ffff6c1e7
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/test/Analysis/DependenceAnalysis/gcd-miv-overflow.ll
Log Message:
-----------
[DA] Add overflow check in GCD MIV (#172003)
Add an overflow check in the GCD MIV test. Fix the test case added in #172002 .
Commit: 66c45a3b4964106abfa6388056fba57edfde216d
https://github.com/llvm/llvm-project/commit/66c45a3b4964106abfa6388056fba57edfde216d
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/test/Analysis/DependenceAnalysis/exact-rdiv-delta-overflow.ll
Log Message:
-----------
[DA] Fix overflow in the Exact RDIV test (#189578)
This patch adds an overflow check for the computation of `Delta` in the
Exact RDIV test. If an overflow is detected, the analysis bails out.
Commit: 97b78d6ff3fa1d87fc0ba6a235f1d331990918a3
https://github.com/llvm/llvm-project/commit/97b78d6ff3fa1d87fc0ba6a235f1d331990918a3
Author: Guray Ozen <guray.ozen at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/lib/Dialect/LLVMIR/IR/BasicPtxBuilderInterface.cpp
M mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir
Log Message:
-----------
[MLIR][NVVM] Fix predicate operand index in BasicPtxBuilderInterface (#189552)
Predicate index computation was incorrect, it was not counting
write/readwrite symbols.
Wrong case
```
// CHECK: %{{.*}} = llvm.inline_asm has_side_effects asm_dialect = att "@$1 ex2.approx.ftz.f32 $0, $1;", "=f,f,b" %{{.*}}, %{{.*}} : (f32, i1) -> f32
%1 = nvvm.inline_ptx "ex2.approx.ftz.f32 {$w0}, {$r0};" ro (%input : f32), predicate = %pred -> f32
```
PR fixes, predicate index became `@$2`
```
// CHECK: %{{.*}} = llvm.inline_asm has_side_effects asm_dialect = att "@$2 ex2.approx.ftz.f32 $0, $1;", "=f,f,b" %{{.*}}, %{{.*}} : (f32, i1) -> f32
%1 = nvvm.inline_ptx "ex2.approx.ftz.f32 {$w0}, {$r0};" ro (%input : f32), predicate = %pred -> f32
```
Commit: 95db43fdb4704fd7f177eb257b0f69c1de1dc110
https://github.com/llvm/llvm-project/commit/95db43fdb4704fd7f177eb257b0f69c1de1dc110
Author: eiytoq <eiytoq at outlook.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/AST/ItaniumMangle.cpp
Log Message:
-----------
[clang][NFC] ItaniumMangle: polish comments (#183030)
Commit: 6ddb2be00a95b8ad21168c7264a2d9e549cd24d8
https://github.com/llvm/llvm-project/commit/6ddb2be00a95b8ad21168c7264a2d9e549cd24d8
Author: Fady Farag <com.webkit.iidmsa at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/test/CodeGenObjC/constant-string-class-1.m
Log Message:
-----------
[clang][test] Add missing FileCheck pipe in constant-string-class-1.m (#189514)
The test had a CHECK directive that was never executed because the RUN
line did not pipe output to FileCheck.
Commit: fd43a646fc05758650c5edae15f199221cb1a2e4
https://github.com/llvm/llvm-project/commit/fd43a646fc05758650c5edae15f199221cb1a2e4
Author: eiytoq <eiytoq at outlook.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/AST/ItaniumMangle.cpp
Log Message:
-----------
[clang][NFC] ItaniumMangle: modernize code style (#183027)
- Use structured bindings.
- Use if-init-statements to replace nested `if`.
- Use `using` instead of `typedef`.
---------
Co-authored-by: Timm Baeder <tbaeder at redhat.com>
Commit: c6b3da6b3eef3d49b5704950db052c10aabdcbf7
https://github.com/llvm/llvm-project/commit/c6b3da6b3eef3d49b5704950db052c10aabdcbf7
Author: David Spickett <david.spickett at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/include/lldb/Target/MemoryRegionInfo.h
M lldb/unittests/Process/Utility/LinuxProcMapsTest.cpp
M lldb/unittests/Process/Utility/MemoryTagManagerAArch64MTETest.cpp
M lldb/unittests/Process/minidump/MinidumpParserTest.cpp
Log Message:
-----------
[lldb] Remove memory_tagged from MemoryRegionInfo (#189617)
By turning SetMemoryTagged into a builder method (returns a reference to
self). Then only using that in the tests that need to change the default
of "don't know".
Commit: 20562cefb033b29f5e897d4e74afceb8de8ad9f6
https://github.com/llvm/llvm-project/commit/20562cefb033b29f5e897d4e74afceb8de8ad9f6
Author: eiytoq <eiytoq at outlook.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/MicrosoftMangle.cpp
Log Message:
-----------
[Clang][NFC] Remove redundant DeclContext workaround for local extern decls (#186665)
This patch removes an out-of-date FIXME.
The underlying issue was already fixed by
`Sema::adjustContextForLocalExternDecl` introduced by
https://github.com/llvm/llvm-project/commit/541b38be7bf3afded3269a33586418254d82d7b3
Commit: 68a91f3d36531dbd9d8635f45f53368179361af9
https://github.com/llvm/llvm-project/commit/68a91f3d36531dbd9d8635f45f53368179361af9
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Analysis/DependenceAnalysis.cpp
Log Message:
-----------
[DA] Remove ExtraGCD from GCD MIV (NFC) (#172004)
As some code was removed in #169927, `ExtraGCD` in `gcdMIVtest` is no
longer necessary. This patch removes it and also adjust the comments.
Commit: 914fca472009f8052867704f00b24c27d79ca5d5
https://github.com/llvm/llvm-project/commit/914fca472009f8052867704f00b24c27d79ca5d5
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/tools/llc/llc.cpp
Log Message:
-----------
[llc] Change `TargetMachine` allocation assert to error (#189541)
As we shouldn't assert an allocation (which can fail).
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Commit: f14b865ff54d60901b43e7f7e96d91b9fa82ba9f
https://github.com/llvm/llvm-project/commit/f14b865ff54d60901b43e7f7e96d91b9fa82ba9f
Author: David Spickett <david.spickett at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/include/lldb/Target/MemoryRegionInfo.h
M lldb/unittests/Process/Utility/LinuxProcMapsTest.cpp
M lldb/unittests/Process/Utility/MemoryTagManagerAArch64MTETest.cpp
M lldb/unittests/Process/minidump/MinidumpParserTest.cpp
Log Message:
-----------
[lldb] Remove "flash" and "blocksize" from MemoryRegionInfo constructor (#189636)
These are only set to non-default values after calling a constructor.
Removing them removes noise from many tests that make MemoryRegionInfos.
Commit: 161c53f66ea8044e6618d7c7829ba90196c72a79
https://github.com/llvm/llvm-project/commit/161c53f66ea8044e6618d7c7829ba90196c72a79
Author: David Truby <david.truby at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M openmp/cmake/modules/LibompUtils.cmake
M openmp/runtime/CMakeLists.txt
M openmp/runtime/cmake/LibompGetArchitecture.cmake
M openmp/runtime/src/CMakeLists.txt
M openmp/runtime/src/kmp.h
M openmp/runtime/src/kmp_atomic.cpp
A openmp/runtime/src/kmp_invoke_microtask.cpp
M openmp/runtime/src/kmp_os.h
M openmp/runtime/src/kmp_platform.h
M openmp/runtime/src/kmp_runtime.cpp
M openmp/runtime/src/thirdparty/ittnotify/ittnotify_config.h
M openmp/runtime/src/z_Linux_asm.S
M openmp/runtime/src/z_Linux_util.cpp
M openmp/runtime/src/z_Windows_NT-586_util.cpp
M openmp/runtime/test/misc_bugs/many-microtask-args.c
Log Message:
-----------
[openmp] Add support for arm64ec to libomp (#176151)
This patch adds arm64ec support to libomp.
Note that this support isn't entirely usable on Windows hosts as libomp
requires LLVM_PER_TARGET_RUNTIME_DIR=On for to work correctly when
multiple runtimes are built, which is unsupported on Windows. A
following patch will add arm64x support to the build to rectify this.
Commit: 67d4842910b8cb79f31b9041bdf56c206cd768e9
https://github.com/llvm/llvm-project/commit/67d4842910b8cb79f31b9041bdf56c206cd768e9
Author: ambergorzynski <120007557+ambergorzynski at users.noreply.github.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir
Log Message:
-----------
[NFC][AMDGPU] New test for untested case in SILowerSGPRSpills (#189426)
[This
case](https://github.com/llvm/llvm-project/blob/f380a878d515024fe02662471e81cd72a8b3eb93/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp#L343-L345)
is not covered by any existing tests (checked using code coverage and by
inserting an `abort` at that line). I propose a new test that tests this
line.
This is demonstrated by showing that it is the only test that fails in
the presence of the `abort`.
Commit: a839e500e8a1934d3ad0a346d3789904c2a865a9
https://github.com/llvm/llvm-project/commit/a839e500e8a1934d3ad0a346d3789904c2a865a9
Author: ambergorzynski <120007557+ambergorzynski at users.noreply.github.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
A llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-infer-fnptr-todo-type.ll
Log Message:
-----------
[NFC][SPIRV] Add test for untested case in SPIRVEmitIntrinsics (#189413)
[This
case](https://github.com/llvm/llvm-project/blob/af98e3c2cb07af90029785a78e49c2761f20088e/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp#L1233-L1236)
is not tested by any existing test (checked using code coverage and by
inserting an `abort`). The case marks type deduction as incomplete.
I suggest a new test to cover this case; it's specific to
`-mtriple=spirv64-amd-amdhsa`.
Commit: 5d051f628c61fcec3ef6d23ce09be169454d9f27
https://github.com/llvm/llvm-project/commit/5d051f628c61fcec3ef6d23ce09be169454d9f27
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
Log Message:
-----------
clang: Remove unnecessary isAMDGCN wrapper (#189640)
Commit: d5f7acdbc15fd15244bf6f3e4d4e3ea5a7bd2781
https://github.com/llvm/llvm-project/commit/d5f7acdbc15fd15244bf6f3e4d4e3ea5a7bd2781
Author: Davide Grohmann <davide.grohmann at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td
M mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops.mlir
M mlir/test/Target/SPIRV/tosa-ops.mlir
M mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
Log Message:
-----------
[mlir][spirv] Add Cast/Rescale ops in TOSA Ext Inst Set (#189028)
This patch introduces the following operators:
spirv.Tosa.Cast
spirv.Tosa.Rescale
Also dialect and serialization round-trip tests have been added.
Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
Commit: a30a8e9474f75000d9746b5d02800d2e47903f44
https://github.com/llvm/llvm-project/commit/a30a8e9474f75000d9746b5d02800d2e47903f44
Author: Leandro Lupori <leandro.lupori at linaro.org>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/test/Lower/OpenMP/composite_simd_linear.f90
M flang/test/Lower/OpenMP/distribute-parallel-do-simd.f90
M flang/test/Lower/OpenMP/distribute-simd.f90
M flang/test/Lower/OpenMP/linear_modifier.f90
M flang/test/Lower/OpenMP/loop-pointer-variable.f90
M flang/test/Lower/OpenMP/ordered-simd.f90
M flang/test/Lower/OpenMP/wsloop-simd.f90
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
A mlir/test/Target/LLVMIR/openmp-simd-linear.mlir
Log Message:
-----------
Reland "[flang][OpenMP] Fix lowering of LINEAR iteration variables (#183794)" (#188851)
Linear iteration variables were being treated as private. This fixes
one of the issues reported in #170784.
The regression reported in #188536 occurred because
LinearClauseProcessor was rewriting all basic blocks whose names
contained a given substring, including those that were not part of the
translated SIMD region.
This didn't cause problems before because linear variables were always
privatized, which doesn't happen with this change.
The issue is fixed by rewriting only the basic blocks that correspond to
the omp.simd operation.
Commit: 26e67aeefaed0392fbb365335dd3cc7d8f1f459a
https://github.com/llvm/llvm-project/commit/26e67aeefaed0392fbb365335dd3cc7d8f1f459a
Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/test/MC/AArch64/armv8.9a-prfm-slc.s
M llvm/test/MC/AArch64/basic-a64-instructions.s
M llvm/test/MC/Disassembler/AArch64/armv8.9a-prfm-slc.txt
M llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
M llvm/test/tools/llvm-mca/AArch64/A64FX/A64-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Apple/M1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A320-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A55-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A57-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/HiSilicon/tsv110-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Inputs/basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Olympus/basic-instructions.s
Log Message:
-----------
[AArch64] Always print the PRFM operation name (#182035)
When the encoding in the "Rt" field of the PRFM instruction maps to a
`<prfop>` value, the name of the prefetch operation should be printed
regardless of whether the associated feature (e.g. FEAT_PRFMSLC)
is available. If the feature is not available, the instruction is a nop.
All other encodings are printed as an immediate.
Commit: 76ed0ad3577e0c96406601d23552befb5a250c6a
https://github.com/llvm/llvm-project/commit/76ed0ad3577e0c96406601d23552befb5a250c6a
Author: Nerixyz <nerixdev at outlook.de>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/include/llvm/DebugInfo/CodeView/LazyRandomTypeCollection.h
M llvm/include/llvm/DebugInfo/PDB/Native/TpiStream.h
M llvm/lib/DebugInfo/CodeView/LazyRandomTypeCollection.cpp
M llvm/lib/DebugInfo/PDB/Native/TpiStream.cpp
M llvm/unittests/DebugInfo/PDB/CMakeLists.txt
A llvm/unittests/DebugInfo/PDB/TpiStreamTest.cpp
Log Message:
-----------
[CodeView] Expose fallible type accessors in TpiStream (#188299)
`LazyRandomTypeCollection` already has fallible functions for
`getType(TypeIndex)` this exposes them in `TpiStream` and does a mini
cleanup in `LazyRandomTypeCollection`'s `GetType`.
Context: #186948 saw a crash in LLDB where we call `GetType` without
checking the type index before calling the method. In `GetType` we
called `error(std::move(EC))`, which ignores the error in release mode.
The cause was the type index `0x80000169` in an `S_LOCAL`.
We now do a soft fail in release mode - we already check the error, so
we might as well return an empty value.
Aside: The type index there feels really unusual, the type indices in
other records around the `S_LOCAL` were in a similar range. Almost looks
like some integer over-/underflow.
Commit: 5b010134abd44bfe7543f89bb636852a5fa09a3b
https://github.com/llvm/llvm-project/commit/5b010134abd44bfe7543f89bb636852a5fa09a3b
Author: Max Graey <maxgraey at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/include/llvm/ADT/bit.h
Log Message:
-----------
[ADT] implement countl_zero_constexpr and reuse it for countl_zero & bit_width_constexpr (#189111)
Implement constant evaluated `countl_zero_constexpr` similar to
`countr_zero_constexpr` and use it for `countl_zero` and
`bit_width_constexpr`.
Also, `countl_zero` now use fast intrinsic path for `uint8/uint16` types
(use `sizeof(T) <= 4` instead `sizeof(T) == 4`).
Commit: 74e84c0cf5f1f0df9671090c2e73714f6730ec16
https://github.com/llvm/llvm-project/commit/74e84c0cf5f1f0df9671090c2e73714f6730ec16
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/CodeGen/CGException.cpp
A clang/test/CodeGen/async-exceptions.c
Log Message:
-----------
[Clang] Fix getTerminator() use for -fasync-exceptions (#189644)
Commit: 027475071e73bb72f874652c90f91f4ec483d578
https://github.com/llvm/llvm-project/commit/027475071e73bb72f874652c90f91f4ec483d578
Author: Max Graey <maxgraey at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Support/APInt.cpp
M llvm/unittests/ADT/APIntTest.cpp
Log Message:
-----------
[Support][APint] Fix APInt::urem for edge case. Use `U.pVal[0] instead getZExtValue() (#189441)
Use `U.pVal[0]` instead of `getZExtValue()` in the
`APInt::urem(uint64_t)` power-of-two fast path. `getZExtValue()`
requires the entire APInt to fit into 64 bits, but this code can be
reached for multi-word values, which may trigger assertions
(`assert(getActiveBits() <= 64 && "Too many bits for uint64_t")`) or
otherwise mis-handle wide integers.
Also add simple test for edge cases.
Improvement for https://github.com/llvm/llvm-project/pull/189245
Commit: 935cf7ec2261a0d4c753f0efbbfc9ef3c9f0c409
https://github.com/llvm/llvm-project/commit/935cf7ec2261a0d4c753f0efbbfc9ef3c9f0c409
Author: Max Graey <maxgraey at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/unittests/ADT/APIntTest.cpp
Log Message:
-----------
[Support][APint] Added more unit tests for clearBits / clearBitsSlowCase (#189434)
Commit: 33fc8fca62449130ae98ebbb95f1c33d74ee180d
https://github.com/llvm/llvm-project/commit/33fc8fca62449130ae98ebbb95f1c33d74ee180d
Author: Max Graey <maxgraey at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Support/APInt.cpp
Log Message:
-----------
[Support][APint] Optimize fallback case in APInt::reverseBits (#189291)
Commit: 0ef10d62d756e15e4e49e0603da286bd144e88b7
https://github.com/llvm/llvm-project/commit/0ef10d62d756e15e4e49e0603da286bd144e88b7
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_cooperative_matrix/cooperative_matrix.ll
Log Message:
-----------
[SPIR-V] Fix OpCooperativeMatrixLengthKHR operand type (#189630)
related to #188703
Commit: d08ebbe8eba1dd2453a00ae0a0a6bd04b0d88d51
https://github.com/llvm/llvm-project/commit/d08ebbe8eba1dd2453a00ae0a0a6bd04b0d88d51
Author: BalƔzs Benics <benicsbalazs at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
A clang/include/clang/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphSummary.h
M clang/include/clang/ScalableStaticAnalysisFramework/SSAFBuiltinForceLinker.h
M clang/lib/Driver/CMakeLists.txt
M clang/lib/FrontendTool/CMakeLists.txt
M clang/lib/ScalableStaticAnalysisFramework/Analyses/CMakeLists.txt
A clang/lib/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphExtractor.cpp
M clang/tools/clang-ssaf-format/CMakeLists.txt
M clang/tools/clang-ssaf-linker/CMakeLists.txt
A clang/unittests/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphExtractorTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/CMakeLists.txt
M clang/unittests/ScalableStaticAnalysisFramework/Registries/SummaryExtractorRegistryTest.cpp
M llvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/FrontendTool/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/ScalableStaticAnalysisFramework/Analyses/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/ScalableStaticAnalysisFramework/BUILD.gn
Log Message:
-----------
[clang][ssaf] Add CallGraph summary and extractor (#188753)
rdar://170258016
Commit: e3b6426d737295c8d079c348235a40c94269d0d2
https://github.com/llvm/llvm-project/commit/e3b6426d737295c8d079c348235a40c94269d0d2
Author: Sam Parker <sam.parker at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
A llvm/test/CodeGen/WebAssembly/strided-int-mac.ll
Log Message:
-----------
[NFC][WebAssembly] CodeGen test (#189626)
Commit: 14311077f809afa494ec73d160c6aa719fbea9f2
https://github.com/llvm/llvm-project/commit/14311077f809afa494ec73d160c6aa719fbea9f2
Author: Paul Walker <paul.walker at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/test/Transforms/InstSimplify/constant-fold-fp-denormal.ll
Log Message:
-----------
[LLVM][ConstantFold] Ensure scalar type is queried when determining denormal mode. (#189600)
Fixes https://github.com/llvm/llvm-project/issues/187928
Commit: 9f8fc658abf8548029d2e613279f17fd314fcc74
https://github.com/llvm/llvm-project/commit/9f8fc658abf8548029d2e613279f17fd314fcc74
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/test/Other/new-pm-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
Log Message:
-----------
[Passes] Remove some optsize checks (#189369)
LibCallsShrinkWrapPass and PGOMemOPSizeOpt already check for optsize
attributes internally, so there is no need to handle this in the pass
pipeline.
The context here is that I'd like to make the pass pipeline completely
independent of Os/Oz so that we know for sure that function-level
optsize/minsize attributes behave identically to the pipeline-level
option.
Commit: d5d32d3052d1156947d88787ac425a94a593c622
https://github.com/llvm/llvm-project/commit/d5d32d3052d1156947d88787ac425a94a593c622
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/include/llvm/TargetParser/Triple.h
M llvm/lib/TargetParser/Triple.cpp
Log Message:
-----------
Triple: Expose parseArch as a public method (#189648)
Clang has some code which is doing a direct arch name
string compare which should really be recognizing anything
usable as a triple architecture. It makes more sense to
directly parse the architecture than to construct a temporary
triple just to see what the parsed arch is.
For some reason the existing public parsing method is
getArchTypeForLLVMName. I'm not fully sure what the difference
between the 2 is supposed to be. My current guess is
getArchTypeForLLVMName is only supposed to handle the
canonical architecture name.
Commit: 10ea3deb8702af4a744f92d411513a6f3a5d6dfd
https://github.com/llvm/llvm-project/commit/10ea3deb8702af4a744f92d411513a6f3a5d6dfd
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
A libc/src/__support/OSUtil/linux/syscall_wrappers/raise.h
M libc/src/signal/linux/CMakeLists.txt
M libc/src/signal/linux/raise.cpp
Log Message:
-----------
[libc][syscall] lift raise to syscall wrapper (#189507)
Commit: 7d0bf88581ff03feb3d9dcef6548cf22cd6d1dd9
https://github.com/llvm/llvm-project/commit/7d0bf88581ff03feb3d9dcef6548cf22cd6d1dd9
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPContext.cpp
Log Message:
-----------
OpenMP: Match all Triple recognized arch aliases (#189649)
This liberalizes match(device = {arch(some_arch)} to recognize
other names for some_arch.
Previously this compared against getArchTypeForLLVMName, which
only matches a subset of names (which seems to be the canonical
architecture names). There was a special case hack for "x86_64",
which is one of the "x86-64" aliases accepted by parseArch, but is
not the canonical architecture name.
Commit: 46dd9d6f522d3007b0c5fe121805e09fc58fe012
https://github.com/llvm/llvm-project/commit/46dd9d6f522d3007b0c5fe121805e09fc58fe012
Author: natanelh-mobileye <natanelh at mobileye.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/abds-neg.ll
M llvm/test/CodeGen/AArch64/abdu-neg.ll
M llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
M llvm/test/CodeGen/RISCV/abds-neg.ll
M llvm/test/CodeGen/RISCV/abdu-neg.ll
Log Message:
-----------
[SDAG][abd] Combine abd of small types (#181538)
It is beneficial to combine abd of illegal, small types (types that get promoted to wider scalar size).
Commit: e7483770c71dc502462fa717623b808161b47ad6
https://github.com/llvm/llvm-project/commit/e7483770c71dc502462fa717623b808161b47ad6
Author: John Harrison <harjohn at google.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/test/API/tools/lldb-dap/attach/TestDAP_attach.py
M lldb/tools/lldb-dap/Handler/AttachRequestHandler.cpp
Log Message:
-----------
[lldb-dap] Correct attaching by program basename. (#188886)
Fixes an issue where attaching by program would fail if the program name
was a partial name (e.g. "foobar" instead of "/path/to/foobar").
We failed to create the target which caused the attach to fail. Now we
fallback to the dummy target and update to the real target after the
attach completes.
Here is an example launch configuration that fail:
```
{
"type": "lldb-dap",
"name": "Attach (wait)",
"request": "attach",
"program": "foobar",
"waitFor": true
},
```
Commit: 5a89da7d13e1e9e428db35c28e49c31df8f10996
https://github.com/llvm/llvm-project/commit/5a89da7d13e1e9e428db35c28e49c31df8f10996
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/siginfo_t.h
M libc/src/signal/linux/CMakeLists.txt
M libc/src/signal/linux/sigaction.cpp
M libc/src/signal/linux/signal_utils.h
Log Message:
-----------
[libc][signal] cleanup sigaction implementation (#189512)
Commit: aca71454e4f9b970fc3e4065456f277202030ae0
https://github.com/llvm/llvm-project/commit/aca71454e4f9b970fc3e4065456f277202030ae0
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/test/MC/AArch64/armv9.6a-pcdphint.s
Log Message:
-----------
[AArch64][llvm] Fix encoding for `stshh` instruction (#189588)
The encoding for `stshh` was incorrect, and has been fixed. This
has been checked against the Arm ARM.
Commit: efbd59631091fdf4ed3c0f33343ccd63dd896e00
https://github.com/llvm/llvm-project/commit/efbd59631091fdf4ed3c0f33343ccd63dd896e00
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
Log Message:
-----------
[AMDGPU][NFCI] CustomOperand to have a default type (#189584)
Most of the time, we should not need to care about the type at all, so
having it as a mandatory parameter confuses people and invites using
i1/i8/i16 where not necessary.
Commit: acc609bc296e9ddc3c1aff188a4411bc19802043
https://github.com/llvm/llvm-project/commit/acc609bc296e9ddc3c1aff188a4411bc19802043
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M libcxx/docs/ReleaseNotes/23.rst
Log Message:
-----------
[libc++][NFC] Removed an EOL stray white space in Release Notes (#189654)
Commit: bb55c4bcfe30146b50def8bf21617647d6b0167a
https://github.com/llvm/llvm-project/commit/bb55c4bcfe30146b50def8bf21617647d6b0167a
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRCUDAAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Dialect/Transforms/CXXABILowering.cpp
M clang/test/CIR/CodeGen/nonzeroinit-struct.cpp
A clang/test/CIR/Transforms/cxx-abi-lowering-attrs.cir
M clang/tools/cir-opt/cir-opt.cpp
M clang/utils/TableGen/CIRLoweringEmitter.cpp
Log Message:
-----------
[CIR] Implement member-pointer members lowering/CXX ABI lowering (#187327)
Record types with a member pointer as a member require quite a bit of
work to get to function properly. First, we have to wire them through
the AST->CIR lowering to make sure we properly represent them, and
represent them when they're zero initializable. We also have to properly
initialize elements when we're NOT zero initializable.
More importantly, we have to implement the CXXABILowering of record
types. Before this patch, we just assumed that all RecordTypes were
legal, since we didn't have the above lowering. A vast majority of this
patch is around getting RecordTypes to lower properly. There isn't
really a good way to test this without the FE changes, so it wasn't
split off.
We accomplish this in 2 phases: First, we transform each individual
record type along the way, giving it a new cxx-abi specific name. We
have to ensure that recursive evaluation works correctly, so we pulled
the solution from the LLVM-IR dialect for that. Secondly, we rename all
of the RecordType's back. This is safe only after we have 'removed' all
references to the untransformed RecordType due to the way RecordStorage
works, however it'll assert if we get this wrong. We do this second
stage to minimize the impact on tests as well as the IR: otherwise EVERY
RecordType would have their names changed. In addition to massive test
changes, this would be an ugly change everywhere.
One additional concern with RecordType lowering, is that it makes most
of RecordTypes potentially 'illegal'. Thus, any attribute that
'references' a record type is required to be transformed as well, so
this patch implements attribute legalization and transformation.
This quite a few NYIs around lowering of these, though most are probably
not really accessible.
Commit: 2c5af14e9faaf384e2a33544a6e506b928b5211e
https://github.com/llvm/llvm-project/commit/2c5af14e9faaf384e2a33544a6e506b928b5211e
Author: Sam Parker <sam.parker at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/test/CodeGen/WebAssembly/strided-int-mac.ll
Log Message:
-----------
[NFC][WebAssembly] More codegen tests (#189671)
Commit: 09c54a8f7afcd30c83862ab2792eacdb53c77a8f
https://github.com/llvm/llvm-project/commit/09c54a8f7afcd30c83862ab2792eacdb53c77a8f
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/TargetAndABI.h
M mlir/lib/Conversion/SCFToSPIRV/SCFToSPIRV.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
M mlir/lib/Dialect/SPIRV/IR/TargetAndABI.cpp
M mlir/test/Conversion/SCFToSPIRV/for.mlir
M mlir/test/Conversion/SCFToSPIRV/while.mlir
Log Message:
-----------
[mlir][SPIR-V] Support spirv.loop_control attribute on scf.for and scf.while (#189392)
Propagate the `spirv.loop_control` attribute from `scf.for` and
`scf.while` operations to the generated `spirv.mlir.loop` during
SCFToSPIRV conversion
Commit: ff4e229f8c758bc547d8bb42dbd9209306603f94
https://github.com/llvm/llvm-project/commit/ff4e229f8c758bc547d8bb42dbd9209306603f94
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll
M llvm/test/Transforms/LoopVectorize/RISCV/dbg-tail-folding-by-evl.ll
M llvm/test/Transforms/LoopVectorize/RISCV/predicated-reverse-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll
M llvm/test/Transforms/LoopVectorize/VPlan/RISCV/vplan-riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Log Message:
-----------
Revert "[VPlan] Extract reverse mask from reverse accesses" (#189637)
Reverts llvm/llvm-project#155579
Assertion added triggers on some buildbots
clang:
/home/tcwg-buildbot/worker/clang-aarch64-sve2-vla/llvm/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp:3840:
virtual InstructionCost
llvm::VPWidenMemoryRecipe::computeCost(ElementCount, VPCostContext &)
const: Assertion `!IsReverse() && "Inconsecutive memory access should
not have reverse order"' failed.
PLEASE submit a bug report to
https://github.com/llvm/llvm-project/issues/ and include the crash
backtrace, preprocessed source, and associated run script.
Stack dump:
0. Program arguments:
/home/tcwg-buildbot/worker/clang-aarch64-sve2-vla/stage1.install/bin/clang
-DNDEBUG -mcpu=neoverse-v2 -mllvm -scalable-vectorization=preferred -O3
-std=gnu17 -fcommon -Wno-error=incompatible-pointer-types -MD -MT
MultiSource/Benchmarks/Prolangs-C/TimberWolfMC/CMakeFiles/timberwolfmc.dir/finalpin.c.o
-MF CMakeFiles/timberwolfmc.dir/finalpin.c.o.d -o
CMakeFiles/timberwolfmc.dir/finalpin.c.o -c
/home/tcwg-buildbot/worker/clang-aarch64-sve2-vla/test/test-suite/MultiSource/Benchmarks/Prolangs-C/TimberWolfMC/finalpin.c
Commit: 38c0f53a14f41989e7156698e779bb15a3fd95c7
https://github.com/llvm/llvm-project/commit/38c0f53a14f41989e7156698e779bb15a3fd95c7
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/AArch64/fma-conversion-multi-use-guard.ll
Log Message:
-----------
[SLP][NFC] Add a test for incorrect fma-conversion for fmuls with multi uses
Commit: e891812cacde0c6561b73173d24d37309aeb93dc
https://github.com/llvm/llvm-project/commit/e891812cacde0c6561b73173d24d37309aeb93dc
Author: Luke Lau <luke at igalia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
Log Message:
-----------
[RISCV] Remove codegen for vp_minimum, vp_maximum (#189550)
Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999
This splits off two intrinsics from #179622.
Commit: 67c34294a6b3e161a84ed4697c326d04d651d7ff
https://github.com/llvm/llvm-project/commit/67c34294a6b3e161a84ed4697c326d04d651d7ff
Author: AidinT <at.aidin at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/docs/Interfaces.md
M mlir/docs/Tools/mlir-reduce.md
Log Message:
-----------
[mlir][docs] dialect interfaces and mlir reduce documentation fix (#189258)
Two modifications:
1. Reflect newly added dialect interface methods in the documentation
2. Remove the bug in the `MLIR Reduce` documentation
Commit: b66d98afb9e09864f5857ab17ec2e6ee344ee31d
https://github.com/llvm/llvm-project/commit/b66d98afb9e09864f5857ab17ec2e6ee344ee31d
Author: Dave Lee <davelee.com at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/examples/python/formatter_bytecode.py
M lldb/test/Shell/ScriptInterpreter/Python/Inputs/FormatterBytecode/RigidArrayLLDBFormatterSwift.txt
Log Message:
-----------
[lldb][bytecode] Improvements to compiler generated Swift (#189425)
Following feedback from @benrimmington in
https://github.com/apple/swift-collections/pull/607, this changes the
following:
1. Uses `objectFormat()` compiler conditional instead of `os()` (see
"Cross-platform object file format support" in
[SE-0492](https://github.com/swiftlang/swift-evolution/blob/main/proposals/0492-section-control.md#cross-platform-object-file-format-support))
2. Uses a raw identifier for the generated Swift symbol name, instead of
an escaped name (see
[SE-0451](https://github.com/swiftlang/swift-evolution/blob/main/proposals/0451-escaped-identifiers.md))
Commit: 720b8ea893da2168121622bbfb536a78b35ffa32
https://github.com/llvm/llvm-project/commit/720b8ea893da2168121622bbfb536a78b35ffa32
Author: David Truby <david.truby at arm.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/CMakeLists.txt
M llvm/runtimes/CMakeLists.txt
M openmp/runtime/CMakeLists.txt
A openmp/runtime/cmake/arm64x.cmake
Log Message:
-----------
[openmp] Add support for Arm64X to libomp (#176157)
This patch allows building libomp.dll and libomp.lib as Arm64X binaries
containing both arm64 and arm64ec code and useable from applications
compiled for both architectures.
Commit: 4087c5f30d133087b7706db80e27b2d35dd334af
https://github.com/llvm/llvm-project/commit/4087c5f30d133087b7706db80e27b2d35dd334af
Author: Dave Lee <davelee.com at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/examples/python/formatter_bytecode.py
Log Message:
-----------
[lldb][bytecode] Add append mode for compiler output (#189693)
Commit: 6477f3aa166b0af1677cd36300097f088bdff510
https://github.com/llvm/llvm-project/commit/6477f3aa166b0af1677cd36300097f088bdff510
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/lib/Conversion/ArithToSPIRV/ArithToSPIRV.cpp
M mlir/test/Conversion/ArithToSPIRV/arith-to-spirv.mlir
Log Message:
-----------
[mlir][ArithToSPIRV] Fix invalid SPIRV and crashes when lowering integer ops on i1 (#189239)
Several arith integer operations on i1 / vector<Ni1> types were either
crashing or producing invalid SPIRV. The i1 type maps to spirv.bool in
SPIRV, not to a SPIRV integer ā so standard integer SPIRV ops
(spirv.IAdd, spirv.UDiv, spirv.GLSMax, etc.) are illegal on it.
Add dedicated boolean patterns for all affected arith integer ops, each
with benefit=2 to take priority over the generic elementwise patterns.
The semantics for i1 follow from treating true = 1 / false = 0 with
two's complement wrapping:
- addi, subi ā spirv.LogicalNotEqual (XOR on bits)
- muli, divui, divsi ā spirv.LogicalAnd
- remui, remsi, shli, shrui ā spirv.LogicalAnd(a, spirv.LogicalNot(b))
(a & ~b)
- shrsi ā identity (arithmetic right shift of a 1-bit signed value is
always the input)
- maxui, minsi ā spirv.LogicalOr (unsigned max / signed min treats true
as larger)
- maxsi, minui ā spirv.LogicalAnd (signed max / unsigned min treats
false as larger)
Fixes #61162
Assisted-by: Claude Code
Commit: 728de262fcc0320b7dabf2a1ac52940b4fe1f7c0
https://github.com/llvm/llvm-project/commit/728de262fcc0320b7dabf2a1ac52940b4fe1f7c0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/neon-abd.ll
Log Message:
-----------
[NFC][AArch64] neon-abd.ll - remove unnecessary entry labels to reduce diff size in #186659 (#189690)
Commit: c98e4386fc45e35ceacb083f6677622f54f656a9
https://github.com/llvm/llvm-project/commit/c98e4386fc45e35ceacb083f6677622f54f656a9
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/test/mlir-tblgen/BUILD.bazel
Log Message:
-----------
[Bazel] Port b544ad57039588d0fe24a1f512202cc5c0bd3a67
Commit: fce3a66f5e2f247890c57ac01a2c9847358c0f27
https://github.com/llvm/llvm-project/commit/fce3a66f5e2f247890c57ac01a2c9847358c0f27
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M flang/lib/Semantics/mod-file.cpp
M flang/lib/Semantics/mod-file.h
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Semantics/Inputs/modfile84.f90
A flang/test/Semantics/modfile84.f90
Log Message:
-----------
[flang] Preserve UseErrorDetails in module files (#189423)
When the same name is USE-associated with two or more distinct ultimate
symbols, and they are not both generic procedure interfaces, it's not an
error unless the name is actually referenced in the scope. But when the
scope is itself a module or submodule, our module files don't preserve
the error for later diagnosis -- instead, the UseErrorDetails symbol
that serves as a "poison pill" in case of later use is discarded when
the module file is generated. So emit additional USE statements to the
module file so that a UseErrorDetails symbol is created anew when the
module file is read.
Commit: 7ff0dc4b9fdee840de0901e969ea11880a28d433
https://github.com/llvm/llvm-project/commit/7ff0dc4b9fdee840de0901e969ea11880a28d433
Author: Chi-Chun, Chen <chichun.chen at hpe.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M flang/lib/Optimizer/OpenMP/FunctionFiltering.cpp
M flang/lib/Optimizer/OpenMP/LowerWorkdistribute.cpp
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[mlir][OpenMP] Add iterator support to depend clause (#189090)
Extend the depend clause to support `!omp.iterated<Ty>` handles
alongside plain depend vars, so the IR can represent both forms.
Assisted with copilot
This is part of feature work for
https://github.com/llvm/llvm-project/issues/188061
Commit: 85d7927c08b5563f050d56d2bf88a6c152489c41
https://github.com/llvm/llvm-project/commit/85d7927c08b5563f050d56d2bf88a6c152489c41
Author: Chi-Chun, Chen <chichun.chen at hpe.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
R flang/test/Lower/OpenMP/Todo/depend-clause.f90
A flang/test/Lower/OpenMP/depend-iterator.f90
Log Message:
-----------
[Flang][OpenMP] Support iterator modifier in depend clause (#189412)
Lower the iterator modifier on depend clause to omp.iterator. Iterated
depend objects emit `!omp.iterated<!llvm.ptr>` by using
`getDataOperandBaseAddr` to generate base address and
`genIteratorCoordinate` to get the addr+offset. The non-iterated objects
in depend clause still use existing lowering path.
This patch is part of feature work for #188061.
Assisted with copilot.
Commit: 9e77a4593526a04cd2308a724039e94d8fbe9445
https://github.com/llvm/llvm-project/commit/9e77a4593526a04cd2308a724039e94d8fbe9445
Author: Chi-Chun, Chen <chichun.chen at hpe.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
Log Message:
-----------
[mlir][OpenMP][NFC] Refactor fillAffinityIteratorLoop (#189418)
Extract affinity-specific logic from fillAffinityIteratorLoop into a
callback so that the iterator loop codegen logic can be shared with
other clauses such as depend clause and target clause.
Commit: 65720adc15da80a65817a2bed3a506cf099d2aa7
https://github.com/llvm/llvm-project/commit/65720adc15da80a65817a2bed3a506cf099d2aa7
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToWiDistributeExperimental.cpp
M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
M mlir/test/Dialect/XeGPU/sg-to-wi-experimental-unit.mlir
Log Message:
-----------
[MLIR][XeGPU] Switch to the new sg to wi pass (#188627)
This PR has changes required to switch the pipeline to use the new sg to
wi pass.
Commit: d47190223930ce8379afa2a183ed9c407414b1a3
https://github.com/llvm/llvm-project/commit/d47190223930ce8379afa2a183ed9c407414b1a3
Author: Amr Hesham <amr96 at programmer.net>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/test/CIR/CodeGen/try-catch.cpp
Log Message:
-----------
[CIR] Implement reference type of record ptr in initCatchParam (#185214)
Implement the reference type of record ptr in initCatchParam
Commit: 0e0a0458ce3aeccb27c677b15abe02e72cf18a50
https://github.com/llvm/llvm-project/commit/0e0a0458ce3aeccb27c677b15abe02e72cf18a50
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
[Bazel] Port d08ebbe8eba1dd2453a00ae0a0a6bd04b0d88d51
Commit: c4e6cf0abff628f9c018428e0d4beed8788efdf9
https://github.com/llvm/llvm-project/commit/c4e6cf0abff628f9c018428e0d4beed8788efdf9
Author: Zhen Wang <37195552+wangzpgi at users.noreply.github.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M flang-rt/lib/cuda/registration.cpp
M flang/include/flang/Evaluate/tools.h
M flang/include/flang/Runtime/CUDA/registration.h
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversionLate.cpp
M flang/test/Fir/CUDA/cuda-code-gen.mlir
M flang/test/Fir/CUDA/cuda-constructor-2.f90
M flang/test/Fir/CUDA/cuda-device-address.mlir
M flang/test/Lower/CUDA/cuda-data-transfer.cuf
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/nvvmir.mlir
Log Message:
-----------
[flang][cuda] Support non-allocatable module-level managed variables (#188526)
Add support for non-allocatable module-level CUDA managed variables
using pointer indirection through a companion global in
__nv_managed_data__. The CUDA runtime populates this pointer with the
unified memory address via __cudaRegisterManagedVar and
__cudaInitModule.
1. Create a .managed.ptr companion global in the __nv_managed_data__
section and register it with _FortranACUFRegisterManagedVariable
(CUFAddConstructor.cpp)
2. Call __cudaInitModule after registration to populate the managed
pointer (registration.cpp)
3. Annotate managed globals in gpu.module with nvvm.managed for PTX
.attribute(.managed) generation (cuda-code-gen.mlir)
4. Suppress cuf.data_transfer for assignments to/from non-allocatable
module managed variables, since cudaMemcpy would target the shadow
address rather than the actual unified memory (tools.h)
5. Preserve cuf.data_transfer for device_var = managed_var assignments
where explicit transfer is still required
Commit: 9c64cb6dca0693b8ae873ba6e40025a554d15c39
https://github.com/llvm/llvm-project/commit/9c64cb6dca0693b8ae873ba6e40025a554d15c39
Author: Medha Tiwari <medhavns1 at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/LowerEmuTLS.cpp
M llvm/test/CodeGen/AArch64/emutls.ll
A llvm/test/CodeGen/ARM/emutls-alignment.ll
Log Message:
-----------
Fix emulated TLS alignment for large variables (#171037)
Fix emulated TLS alignment for larger variables (>= 32 bytes) to use
preferred alignment.
Fixes #167219
Commit: 8a5e029072f75d6097031f9f102483881027a392
https://github.com/llvm/llvm-project/commit/8a5e029072f75d6097031f9f102483881027a392
Author: Steven Perron <stevenperron at google.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/test/SemaHLSL/Texture2D-mips-errors.hlsl
Log Message:
-----------
[HLSL] Fix test writing to an output files (#189684)
The Texture2D-mips-errors.hlsl test was writing it output to a file, but
that is not needed.
Commit: f74f32b529c35531198621fd104cde5d2cf77e0c
https://github.com/llvm/llvm-project/commit/f74f32b529c35531198621fd104cde5d2cf77e0c
Author: Dave Lee <davelee.com at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/examples/python/formatter_bytecode.py
M lldb/test/Shell/ScriptInterpreter/Python/python-bytecode.test
Log Message:
-----------
[lldb][bytecode] Remove "Generated with" comment (#189704)
In most cases, some other script/tool will call the compiler, and it's
the invocation of that script that ought to be documented in the output.
Commit: e04f8bb754bb783279822cb77ff3505c073b7b1d
https://github.com/llvm/llvm-project/commit/e04f8bb754bb783279822cb77ff3505c073b7b1d
Author: Jan Leyonberg <jan_sjodin at yahoo.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
A clang/test/CIR/CodeGenOpenMP/omp-module-attrs.c
Log Message:
-----------
[CIR] Add OMP module attributes to MLIR module (#189394)
This patch adds OpenMP attributes to the MLIR module op used to
communicate various settings e.g. thread options and offloading
information.
Co-authored-by: Claude Opus 4.6 <noreply at anthropic.com>
Commit: 293623ce99d4d6819378311c1506c5ab08d1d860
https://github.com/llvm/llvm-project/commit/293623ce99d4d6819378311c1506c5ab08d1d860
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
A llvm/test/CodeGen/X86/known-fpclass.ll
Log Message:
-----------
[X86] Add initial computeKnownFPClass test case (#189707)
Example test case for #137943 / #189583 / #189585 - failure to recognise ISD::SQRT is never neginf
Commit: ec45f95799f39f92ec22828abb9be9cd80bd0f1f
https://github.com/llvm/llvm-project/commit/ec45f95799f39f92ec22828abb9be9cd80bd0f1f
Author: lntue <lntue at google.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M libc/cmake/modules/LLVMLibCCompileOptionRules.cmake
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/src/__support/CMakeLists.txt
M libc/src/__support/HashTable/CMakeLists.txt
M libc/src/__support/threads/linux/CMakeLists.txt
M libc/src/setjmp/aarch64/CMakeLists.txt
M libc/src/stdio/CMakeLists.txt
M libc/src/stdio/printf_core/CMakeLists.txt
M libc/src/stdio/scanf_core/CMakeLists.txt
M libc/test/src/stdio/CMakeLists.txt
M libc/test/src/stdio/scanf_core/CMakeLists.txt
M libc/test/src/stdlib/CMakeLists.txt
Log Message:
-----------
[libc] Add libc_set_definition and libc_add_definition to properly pass definitions to MSVC. (#189664)
Commit: 42d5fdd47fc62169671f84cf8896c80e29a1cb15
https://github.com/llvm/llvm-project/commit/42d5fdd47fc62169671f84cf8896c80e29a1cb15
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/test/CodeGen/X86/addcarry.ll
M llvm/test/CodeGen/X86/subcarry.ll
Log Message:
-----------
[X86] Add i686 32-bit coverage to addcarry.ll/subcarry.ll tests (#189713)
Inspired by #189018
Commit: 28efe7b554f8d9fbd2405542c27919a612d8288e
https://github.com/llvm/llvm-project/commit/28efe7b554f8d9fbd2405542c27919a612d8288e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
Log Message:
-----------
OpenMP: Reimplement getOffloadArch (#189561)
This function made no sense at all. It was scanning through
the feature map looking for something that parsed as an OffloadArch.
Directly compute the arch from the target device.
I don't know why there isn't just an OffloadArch in TargetOpts,
this shouldn't really require parsing.
Commit: be9b162a795ca362e9dceb945ed2e2618de8cf18
https://github.com/llvm/llvm-project/commit/be9b162a795ca362e9dceb945ed2e2618de8cf18
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors-complex.ll
Log Message:
-----------
[LoadStoreVectorizer] Add tests for mixed-type vectorization (#189716)
Precommitting this test to reflect impact of the mixed-type
vectorization PR #177908. NFC.
Commit: 5c71351cf79471845aaa94fff187b9c9d0ac145f
https://github.com/llvm/llvm-project/commit/5c71351cf79471845aaa94fff187b9c9d0ac145f
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/source/Core/Module.cpp
Log Message:
-----------
[lldb][Module] Add logging when script import fails (#189695)
We already log the import attempt. This patch logs the failure to load
the script since otherwise the log may be misleading. Didn't think it
was worth adding a test-case for this.
Commit: 07893e30f4a64a176601fe2ab1e2d327e19dd1e1
https://github.com/llvm/llvm-project/commit/07893e30f4a64a176601fe2ab1e2d327e19dd1e1
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
Log Message:
-----------
[RISCV] Fix typo STD_RISCVPackedShift->SDT_RISCVPackedShift. NFC (#189678)
Commit: 49dbeca38d8faeef42d7cb03db649fbfb4c195c4
https://github.com/llvm/llvm-project/commit/49dbeca38d8faeef42d7cb03db649fbfb4c195c4
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
A clang/test/CIR/CodeGen/return-in-if-with-cleanups.cpp
Log Message:
-----------
[CIR] Fix missing terminators in regions with cleanup (#187604)
When a cleanup scope was created within an if operation's then or else
region and the source scope ended with a return, we would fail to
terminate the region following the cleanup scope, which surrounded the
return operation, resulting in an MLIR verification error. This change
forces the addition of terminators in the if's then and else regions.
Commit: a7438859265548c8443436d9c0c996338976ad85
https://github.com/llvm/llvm-project/commit/a7438859265548c8443436d9c0c996338976ad85
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/test/CIR/CodeGen/throws.cpp
Log Message:
-----------
[CIR] Add support for throwing destructed type (#188644)
This adds handling for throwing an object of a type that has a
non-trivial destructor.
Commit: ccfba7736f2d39434ae768ae9c9c0165b1959c4b
https://github.com/llvm/llvm-project/commit/ccfba7736f2d39434ae768ae9c9c0165b1959c4b
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
A clang/test/CIR/CodeGen/delegating-ctor-exceptions.cpp
Log Message:
-----------
[CIR] Add support for cleanups after calling a delegating ctor (#189513)
This adds support for calling the destructor of types with a non-trivial
destructor if the initialization throws an exception after a delegating
constructor has been called.
Commit: 282fb05292cab555010a645cef88d62c846511d4
https://github.com/llvm/llvm-project/commit/282fb05292cab555010a645cef88d62c846511d4
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/include/llvm/IR/GlobalObject.h
M llvm/include/llvm/IR/Instruction.h
M llvm/include/llvm/IR/Value.h
M llvm/include/llvm/Support/Alignment.h
M llvm/lib/IR/Globals.cpp
M llvm/lib/IR/LLVMContextImpl.cpp
M llvm/lib/IR/LLVMContextImpl.h
M llvm/lib/IR/Metadata.cpp
Log Message:
-----------
[IR] Store Metadata attachments in vector (#189551)
Metadata is accessed rather often, so store metadata attachments in a
vector indexed by a number instead of a map from Value*; inside the
vector, the metadata attachments form a linked list. Instruction and
GlobalObject store the first metadata attachment index directly. Care is
taken that the offset in the structures is identical.
In addition to substantial performance improvements, this also leads to
a measurable reduction in memory usage -- several instructions have
metadata in debug builds (debug metadata) and release builds (primarily
TBAA), causing the hash table to become quite large.
In Instruction, this uses 4 padding bytes (it might be debatable whether
this is the best use for this space); GlobalObject grows by 4 bytes.
However, should we want grow Instruction by 8 bytes in the future, the
additionally used memory will be ~similar to the memory saved here, so
we could do so without causing a release-to-release memory regression.
This also makes the HasMetadata bit redundant, cleanup will follow
separately -- this is a bit annoying, because this should be inline, but
Value can't access subclass members.
Commit: 9e6968b502bc75803238c10a234e935464142cc1
https://github.com/llvm/llvm-project/commit/9e6968b502bc75803238c10a234e935464142cc1
Author: Amr Hesham <amr96 at programmer.net>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/test/CIR/CodeGen/try-catch.cpp
Log Message:
-----------
[CIR][NFC] Add test for catch with MemberPointer type (#185217)
Add test for catch with MemberPointer type
Commit: af6521fb3a36149cd69d83bfdf87ed26e59a14a2
https://github.com/llvm/llvm-project/commit/af6521fb3a36149cd69d83bfdf87ed26e59a14a2
Author: Srividya Sundaram <srividya.sundaram at intel.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/include/clang/Driver/SyclInstallationDetector.h
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/lib/Driver/ToolChains/SYCL.cpp
A clang/test/Driver/Inputs/SYCL/libLLVMSYCL.ll
R clang/test/Driver/Inputs/SYCL/libsycl.ll
M clang/test/Driver/link-device-code.test
M clang/test/Driver/sycl-offload-jit.cpp
Log Message:
-----------
[Driver] Update SYCL runtime library name and path for target-specific directories (#189053)
This patch updates the Clang driver to support the renamed SYCL runtime
library (libsycl.so ā libLLVMSYCL.so) and its new location in
target-specific directories. These changes align with PR
#[188770](https://github.com/llvm/llvm-project/pull/188770), which
standardizes the SYCL runtime library naming and directory structure to
match other LLVM runtime libraries.
**Changes**
**Library Naming**
- **Old**: libsycl.so
- **New**: libLLVMSYCL.so
**Directory Structure**
Both build and install directories now use target-specific
subdirectories:
- **Old:** lib/libsycl.so
- **New:** lib/target-triple/libLLVMSYCL.so
For example, on x86_64-unknown-linux-gnu:
- **Old**: build/lib/libsycl.so ā install/lib/libsycl.so
- **New**: build/lib/x86_64-unknown-linux-gnu/libLLVMSYCL.so ā
install/lib/x86_64-unknown-linux-gnu/libLLVMSYCL.so
Commit: 899a78cbc4b9422e5567f2bfe4f563efed119756
https://github.com/llvm/llvm-project/commit/899a78cbc4b9422e5567f2bfe4f563efed119756
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M offload/test/offloading/target_critical_region.cpp
Log Message:
-----------
[offload][lit] Disable target_critical_region.cpp on Intel GPU (#189682)
Already disabled on other GPU platforms and sporadically failing on our
builder, so this test seems not be doing too hot.
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: 8af44b7867747cd6942688eef5c5324ef859428b
https://github.com/llvm/llvm-project/commit/8af44b7867747cd6942688eef5c5324ef859428b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/include/clang/Driver/ToolChain.h
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Fuchsia.cpp
Log Message:
-----------
clang: Avoid some conversions of Triple to std::string (#189728)
Commit: c6d770fece415d7e8a55dcd495fd24862b3b1ca6
https://github.com/llvm/llvm-project/commit/c6d770fece415d7e8a55dcd495fd24862b3b1ca6
Author: khaki3 <47756807+khaki3 at users.noreply.github.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/FIRToMemRef.cpp
M flang/test/Transforms/FIRToMemRef/array-coor-slice-shift.mlir
Log Message:
-----------
[flang] Fix FIRToMemRef index computation for array_coor with slice and shape_shift (#189496)
Use shift instead of sliceLb only when the array_coor has an explicit
slice (indicesAreFortran case). When the slice comes from an embox,
the indices are 1-based section indices and must subtract 1.
Commit: 78c5d68029c0507123de28ecbe242490ee487b16
https://github.com/llvm/llvm-project/commit/78c5d68029c0507123de28ecbe242490ee487b16
Author: PiJoules <leonardchan at google.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M compiler-rt/lib/asan/asan_allocator.cpp
M compiler-rt/lib/asan/asan_errors.cpp
M compiler-rt/lib/asan/asan_errors.h
M compiler-rt/lib/asan/asan_flags.inc
M compiler-rt/lib/asan/asan_report.cpp
M compiler-rt/lib/asan/asan_report.h
A compiler-rt/test/asan/TestCases/Linux/free_aligned_sized_mismatch.cpp
A compiler-rt/test/asan/TestCases/Linux/free_sized_mismatch.cpp
Log Message:
-----------
[asan] Add size/alignment checks for free_[aligned_]sized (#189216)
Historically, alignment and size weren't taken into account when freeing
allocations since `free` just takes a pointer. With `free_sized` and
`free_aligned_sized`, we can do these size and alignment checks in asan
now. This adds a new report type specifically for these functions.
Checking is hidden behind a new env flag `free_size_mismatch` which is
enabled by default, but downstream users can opt out of it.
The bulk of this PR was generated by gemini but thoroughly reviewed and
edited by me to the best of my ability.
Commit: 05dd3ae10cf26c22eba2e23ecb4e043b9c2576eb
https://github.com/llvm/llvm-project/commit/05dd3ae10cf26c22eba2e23ecb4e043b9c2576eb
Author: Daniel Thornburgh <dthorn at google.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
A llvm/test/Transforms/InstCombine/printf-puts-not-emittable.ll
Log Message:
-----------
[SimplifyLibCalls] Prevent orphaned global string literals (#189502)
When `printf` is simplified to `puts`, `SimplifyLibCalls` would eagerly
create a global string for the argument before checking if `puts` is
emittable. If `puts` is not emittable (e.g. because it's an unextracted
bitcode libfunc), the optimization aborts, leaving an orphaned global
string in the module. Under expensive checks, this triggers a fatal
error because the function pass modified the module without reporting
it.
This change defers the creation of the global string until after
checking if `puts` is emittable.
(This PR was created with the help of Gemini CLI.)
Commit: da173bfbf5a0bcf9450b15998ba454f4a4fbf1f6
https://github.com/llvm/llvm-project/commit/da173bfbf5a0bcf9450b15998ba454f4a4fbf1f6
Author: Laxman Sole <lsole at nvidia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
M llvm/lib/Target/NVPTX/NVPTXDwarfDebug.cpp
M llvm/lib/Target/NVPTX/NVPTXDwarfDebug.h
M llvm/test/DebugInfo/NVPTX/debug-addr-space.ll
M llvm/test/DebugInfo/NVPTX/debug-name-table.ll
Log Message:
-----------
[NVPTX] Do not emit .debug_pubnames and .debug_pubtypes for NVPTX backend (#187328)
This change adds a mechanism to stop emitting `.debug_pubname`,
`.debug_pubtypes` sections for a particular target.
This is particularly useful for cases where IR is generated by frontends
that do not explicitly disable these sections (as `Clang` does for
`NVPTX`), but still use `llc` for code generation.
Currently, only `NVPTX` uses this to disable these sections.
Commit: 6669fa5806c5fbe607abaa307cb06ce89dd972db
https://github.com/llvm/llvm-project/commit/6669fa5806c5fbe607abaa307cb06ce89dd972db
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Transforms/IPO/ExpandVariadics.cpp
A llvm/test/CodeGen/SPIRV/function/variadics-lowering-builtin-substr-in-name.ll
M llvm/test/CodeGen/SPIRV/printf.ll
Log Message:
-----------
[SPIR-V] Don't lower builtin variadic functions (#188517)
In https://github.com/llvm/llvm-project/pull/178980 I tried to remove
the special handling for `printf`, but the fix was wrong, the pass
expects that `printf` abides by the variadic ABI (single buffer passed
in, args extracted by caller), which isn't how it works.
However the root issue is with any builtin, they are just replaced
directly with instructions, and the only place that could generate code
to honor the variadic ABI would bei in the SPIR-V backend, and it would
be pretty complicated for pretty much no benefit.
It's much simpler to teach the pass to skip certain functions, as we did
before, but this time skip all SPIR-V builtin.
---------
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: de84be21ec500a201ede42bc74b51f2913fe8266
https://github.com/llvm/llvm-project/commit/de84be21ec500a201ede42bc74b51f2913fe8266
Author: Demetrius Kanios <demetrius at kanios.net>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp
M llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp
M llvm/lib/Target/WebAssembly/GISel/WebAssemblyRegisterBankInfo.cpp
A llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/bitwise.mir
A llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/int-arithmetic.mir
A llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/add.mir
A llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/bitwise.mir
A llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/int-arithmetic.mir
Log Message:
-----------
[WebAssembly][GlobalISel] `G_ADD` (and in-reg ext/trunc related) legalization & selection (#183694)
This PR enables `G_ADD` and immediate dependencies (relavent ext and
trunc related ops) to be fully legalized and selected.
The most important change made is getting the boilerplate for
RegBankSelect working.
Split from #157161.
Commit: bf76fa758247c712b1b4879e0f0b17b5450ff141
https://github.com/llvm/llvm-project/commit/bf76fa758247c712b1b4879e0f0b17b5450ff141
Author: Yonah Goldberg <ygoldberg at nvidia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/AtomicExpandPass.cpp
Log Message:
-----------
[AtomicExpandPass][NFC] Refactor processAtomicInstr to be more readable (#186547)
While working on
https://discourse.llvm.org/t/rfc-add-elementwise-modifier-to-atomicrmw/90134/5
I found this `processAtomicInstr` to be a little hard to read, with
casing on the instruction type all over the place. I think it reads
nicer to just case on the instruction type once.
Commit: 626f942073b93b427e1c41e22c297becaa7bb9ae
https://github.com/llvm/llvm-project/commit/626f942073b93b427e1c41e22c297becaa7bb9ae
Author: Alex Langford <alangford at apple.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbutil.py
Log Message:
-----------
[lldb] Increase timeout on lldbutil.wait_for_file_on_target (#189471)
I've been tracking sporadic timeouts waiting for a file to appear on
macOS buildbots (and occasionally local development environments). I
believe I've tracked it down to a regression in process launch
performance in macOS.
What I noticed is that running multiple test suites simultaneously
almost always triggered these failures and that the tests were always
waiting on files created by the inferior. Increasing this timeout no
longer triggers the failures on my loaded machine locally.
This timeout moves from about 16 seconds of total wait time to about 127
seconds of total wait time. This may feel a bit extreme, but this is a
performance issue. While I was here, I cleaned up logging code I was
using to investigate the test failures.
rdar://172122213
Commit: cb32b8bffbf32fd7936808ad260764c28e3197db
https://github.com/llvm/llvm-project/commit/cb32b8bffbf32fd7936808ad260764c28e3197db
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
A llvm/test/Transforms/LoopUnroll/RISCV/runtime-unroll-max-trip-count.ll
M llvm/test/Transforms/LoopUnroll/debug.ll
M llvm/test/Transforms/LoopUnroll/runtime-small-upperbound.ll
Log Message:
-----------
[LoopUnrollPass] Don't pre-set `UP.Count` before legality checks in `computeUnrollCount()` (#185979)
We currently set `UP.Count` to `TripCount` and `MaxTripCount` prior to
full and upper bound unrolling, respectively. This was likely done to
ensure that calls to `UCE.getUnrolledLoopSize(UP)` use the appropriate
trip count. However, we can use `UCE.getUnrolledLoopSize(UP,
FullUnrollTripCount)` instead.
To prevent unintentional unrolling, we set `UP.Count = 0` when
early-exiting `computeUnrollCount()`. (Note: this does not occur
[here](https://github.com/llvm/llvm-project/blob/eb687fb10613573b5d60dfbbb146e15f07809d82/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp#L1190-L1198).
This seems like a bug.)
We only perform early exits when evaluating runtime unrolling. At that
point, [we know `TripCount` is
false](https://github.com/justinfargnoli/llvm-project/blob/3fb31e7b06f6f6d08c7310506a2f363d198a6790/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp#L1157-L1158),
and thus we could not have leaked `TripCount`. However, we [could've
leaked
`MaxTripCount`](https://github.com/llvm/llvm-project/blob/eb687fb10613573b5d60dfbbb146e15f07809d82/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp#L1102-L1110).
It seems like:
https://github.com/llvm/llvm-project/blob/eb687fb10613573b5d60dfbbb146e15f07809d82/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp#L1181-L1188
was supposed to handle this case. However:
- It uses `<` instead of `<=`. This breaks the existing convention
[[1]](https://github.com/llvm/llvm-project/blob/eb687fb10613573b5d60dfbbb146e15f07809d82/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp#L869)
[[2]](https://github.com/llvm/llvm-project/blob/eb687fb10613573b5d60dfbbb146e15f07809d82/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp#L1103)
for how `UP.MaxUpperBound` is treated.
- It's ignored when a target sets `UP.Force = true`.
Thus:
- When `UP.Force == false`, we leak `MaxTripCount` into runtime
unrolling when `MaxTripCount && (UP.UpperBound || MaxOrZero) &&
MaxTripCount == UP.MaxUpperBound`
- When `UP.Force == true`, we leak `MaxTripCount` into runtime unrolling
when `MaxTripCount && (UP.UpperBound || MaxOrZero) && MaxTripCount <=
UP.MaxUpperBound`.
This PR:
- Uses `UCE.getUnrolledLoopSize(UP, FullUnrollTripCount)`
- Stops setting `TripCount` and `MaxTripCount` prior to calling
`shouldFullUnroll()`
- Removes the `UP.Count = 0` safeguards
- Swaps `<` with `<=`, to address the `UP.Force == false` case
- Adds a test to document the behavior change (no longer leaking
`MaxTripCount`) in the `UP.Force == true` case.
Commit: cd8a8e953adb6f7ef000d8f67be21cb362d6dc9c
https://github.com/llvm/llvm-project/commit/cd8a8e953adb6f7ef000d8f67be21cb362d6dc9c
Author: Jan Leyonberg <jan_sjodin at yahoo.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/CIR/Dialect/Transforms/CMakeLists.txt
Log Message:
-----------
[CIR] Add OpenMP and OpenACC dialect dependencies (#189726)
This patch adds dependencies on OpenMP and OpenACC dialects to prevent
link errors when compiling with shared libraries.
Commit: 284e5d79cdf292f4693ee835cbcbb6760ac63889
https://github.com/llvm/llvm-project/commit/284e5d79cdf292f4693ee835cbcbb6760ac63889
Author: Jacob Lambert <jacob.lambert at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/include/llvm/BinaryFormat/MsgPackDocument.h
M llvm/lib/BinaryFormat/MsgPackDocument.cpp
M llvm/unittests/BinaryFormat/MsgPackDocumentTest.cpp
Log Message:
-----------
[MsgPackDocument]: Fix DocNode comparison and add copyNode (#189436)
Fix two bugs in DocNode's comparison operators and add a new
Document::copyNode() method:
1. operator== was implemented via operator<, which hits llvm_unreachable
for Array/Map nodes. Implement operator== directly with recursive value
comparison for all node types.
2. operator< compared KindAndDoc pointers, causing cross-document nodes
of the same type and value to silently produce wrong results. Compare by
kind then by value instead.
3. Add Document::copyNode() for deep copying nodes between Documents
with independent memory ownership.
Commit: c97561ced12d8c7bed9f2fe07733a971247333c7
https://github.com/llvm/llvm-project/commit/c97561ced12d8c7bed9f2fe07733a971247333c7
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
A llvm/test/CodeGen/SPIRV/opencl/nofpclass-fastmath-kernel-pre16.ll
A llvm/test/CodeGen/SPIRV/opencl/nofpclass-fastmath-non-extinst.ll
A llvm/test/CodeGen/SPIRV/opencl/nofpclass-fastmath.ll
Log Message:
-----------
[SPIR-V] Derive FPFastMathMode from nofpclass attributes on OpenCL builtins (#188984)
Commit: 6aa2e496489d6309611b3d3c1ec9d0efd6cc81dd
https://github.com/llvm/llvm-project/commit/6aa2e496489d6309611b3d3c1ec9d0efd6cc81dd
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Parse/ParseDeclCXX.cpp
A clang/test/Parser/decltype-gh188014.cpp
Log Message:
-----------
[clang][Parser] Fix an assertion during decltype error recovery with missing ; (#188123)
Fix an assertion failure in `ParseDecltypeSpecifier` when parsing
malformed expressions e.g. `decltype(union { ... )`.
When a class/union definition is missing a semicolon, clang's error
recovery may synthetically set the current token to `tok::semi` without
actually inserting it into the preprocessor's backtrack cache, see
https://github.com/llvm/llvm-project/blob/9096c9cda3df4d09c9c6e4efa1a07a232a9ac8f8/clang/lib/Parse/ParseDeclCXX.cpp#L1920-L1927
If `ParseDecltypeSpecifier` later encounters this synthetic semicolon
during its own error recovery, its attempts to revert the cache and
re-lex the tokens will lead to reading unexpected tokens from the
historical stream, failing the strict
`Tok.is(tok::semi)` assertion.
This patch removes this assertion, acknowledging that during invalid
parses and error recovery, the preprocessor's cache state may not
strictly align with the parser's simulated state.
Fixes: #188014
Commit: fd1a89163ab76c26cf3bfd2e822905cc55eeef97
https://github.com/llvm/llvm-project/commit/fd1a89163ab76c26cf3bfd2e822905cc55eeef97
Author: Florian Mayer <fmayer at google.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/Serialization/ASTReader.cpp
Log Message:
-----------
[NFC] [clang] swap parameters to checkTargetOptions (#187608)
This is the correct order according to the function prototype.
This should be NFC, because for PCH, AllowCompatibleDifferences
is always false: it is only used in isAcceptableASTFile, which
calls readASTFileControlBlock, which explicitely passes false.
We explicitely pass in `nullptr` for Diag, so the incorrect error
message isn't printed.
Commit: f9ded0e30a24d5faf4c810888da1837b41cbe718
https://github.com/llvm/llvm-project/commit/f9ded0e30a24d5faf4c810888da1837b41cbe718
Author: Artemiy <notlebedev at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
A clang/test/CIR/IR/string-trailing-zeros.cir
Log Message:
-----------
[CIR] Fix incorrect ConstArrayAttr trailing_zeros parsing (#188742)
Closes #187699 .
Fix incorrect parsing of `ConstArrayAttr`. `parse` method incorrectly
used type of `elts` parameter as type of the whole array. This means
that when reading back text or bytecode clangir files attribute did not
have correct type and correct `trailingZerosNum`. Type was always of
inner `elts`, meaning smaller then actual type if any trailing zeros
were present and `trailingZerosNum` was always zero.
Commit: 0454de8b54f92b80a4993c1d59c485daa0c176f9
https://github.com/llvm/llvm-project/commit/0454de8b54f92b80a4993c1d59c485daa0c176f9
Author: Artem Gindinson <gindinson at roofline.ai>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
M mlir/test/Dialect/Arith/int-range-narrowing.mlir
Log Message:
-----------
[mlir][Arith] Avoid sign overflow when narrowing signed operations (#189676)
Whether an arith operation can be truncated to a given bitwidth should
also depend on the sign semantics of the operation itself. Consider:
```
%input = /* upper bound > INT32_MAX, <= UINT32_MAX */ : index
%c0 = arith.constant 0 : index
%cmp = arith.cmpi sle, %input, %c0 : index
```
Previously, `checkTruncatability()` would correctly judge that only an
unsigned truncation could be legal, however the narrowing would still
proceed despite the fact that the `sle` predicate treated the MSB as the
sign.
Ensure that the sign is checked for signed comparison predicates and for
signed elementwise operations by enforcing a `CastKind::Signed`
restriction, whereby the narrowing patterns bail out on incompatible
input range/operation signedness.
**AI tooling usage disclaimer**
LIT tests were expanded from manual reproducer examples with LLM
assistance. Those additional test cases were verified to
regression-test, proofread and edited manually in accordance with the
"Human in the loop" policy. LLMs/generative tooling were not used for
implementation/documentation purposes.
---------
Signed-off-by: Artem Gindinson <gindinson at roofline.ai>
Co-authored-by: GPT 5.4 <codex at openai.com>
Commit: 3ed48bf648cb6d94d8385c336bc72aadcd59f4f2
https://github.com/llvm/llvm-project/commit/3ed48bf648cb6d94d8385c336bc72aadcd59f4f2
Author: Zhen Wang <zhenw at nvidia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M flang-rt/lib/cuda/registration.cpp
M flang/include/flang/Evaluate/tools.h
M flang/include/flang/Runtime/CUDA/registration.h
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFAddConstructor.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFOpConversionLate.cpp
M flang/test/Fir/CUDA/cuda-code-gen.mlir
M flang/test/Fir/CUDA/cuda-constructor-2.f90
M flang/test/Fir/CUDA/cuda-device-address.mlir
M flang/test/Lower/CUDA/cuda-data-transfer.cuf
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/nvvmir.mlir
Log Message:
-----------
Revert "[flang][cuda] Support non-allocatable module-level managed variables" (#189745)
Reverts llvm/llvm-project#188526
Commit: c1ebd2f1c07f1dc51df1c1a56891fe564cbadc19
https://github.com/llvm/llvm-project/commit/c1ebd2f1c07f1dc51df1c1a56891fe564cbadc19
Author: Samuel Thibault <samuel.thibault at ens-lyon.org>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M compiler-rt/test/CMakeLists.txt
Log Message:
-----------
[compiler-rt] Disable asan tests on GNU/Hurd (#169209)
Like OpenBSD, asan does not support GNU/Hurd yet.
Commit: f43ee18e988d923ef5529f1df3910bd2af09e825
https://github.com/llvm/llvm-project/commit/f43ee18e988d923ef5529f1df3910bd2af09e825
Author: cmtice <cmtice at google.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/include/lldb/Target/StackFrame.h
M lldb/include/lldb/ValueObject/DILEval.h
M lldb/include/lldb/ValueObject/DILParser.h
M lldb/include/lldb/ValueObject/ValueObject.h
M lldb/source/Commands/CommandObjectFrame.cpp
M lldb/source/Target/StackFrame.cpp
M lldb/source/ValueObject/DILEval.cpp
M lldb/source/ValueObject/DILParser.cpp
M lldb/source/ValueObject/ValueObject.cpp
Log Message:
-----------
[LLDB] Add allow_var_updates to DIL and CanUpdateVar to SetValueFromInteger (#186421)
In preparation for updating DIL to handle assignments, this adds a
member variable to the DIL Interpreter indicating whether or not
updating program variables is allowed. For invocations from the LLDB
command prompt (through "frame variable") we want to allow it, but from
other places we might not. Therefore we also add new StackFrame
ExpressionPathOption, eExpressionPathOptionsAllowVarUpdates, which we
add to calls from CommandObjectFrame, and which is checked in
GetValueForVariableExpressionPath. Finally, we also add a parameter,
can_update_vars, with a default value of true, to
ValueObject::SetValueFromInteger, as that will be the main function used
to by assignment in DIL.
Commit: 96fd2318ee27ffc67ab1c36d67a5d59f387ac33e
https://github.com/llvm/llvm-project/commit/96fd2318ee27ffc67ab1c36d67a5d59f387ac33e
Author: Vineet Kumar <173554+vntkmr at users.noreply.github.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M flang/docs/C++style.md
Log Message:
-----------
[flang] Add guidelines for referencing the Fortran Standard (#188591)
In response to [[RFC] Qualifying syntax rule numbers with Fortran
standard version in
comments](https://discourse.llvm.org/t/rfc-qualifying-syntax-rule-numbers-with-fortran-standard-version-in-comments/90167)
this PR adds a section on guidelines for referencing the Fortran
Standard.
Commit: b813b0b4e485b0323b51071aca7a415b30c3aa6f
https://github.com/llvm/llvm-project/commit/b813b0b4e485b0323b51071aca7a415b30c3aa6f
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/MemRef/IR/MemRef.h
M mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/test/Dialect/Linalg/invalid.mlir
M mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
M mlir/test/Dialect/MemRef/invalid.mlir
Log Message:
-----------
[mlir][MemRef] Migrate memref dialect alias op folding to interface (#187168)
This PR adds code to FoldMemRefAliasOps / --fold-memref-alias-ops to use
the new IndexedMemoryAccessOpInterface and
IndexedMemCopyOpInterface and implement those operations for relevant
operations in the memref dialect.
This is a reordering of the changes planned in #177014 and #177016 to
make them more testable.
There are no behavior changes expected for how memref.load and
memref.store behave within the alias ops folding pass, though support
for new operations, like memref.prefetch, has been added.
Some error messages have been updated because certain laws of
memref.load/memref.store have been moved to IndexedAccessOpInterface.
Assisted-by: Claude 4.6 (helped deal with some of the boilerplate in the
rewrite patterns and with extracting the patch)
Commit: 6e82a24f4cc585c8b2f69b1ff2cbee443f367187
https://github.com/llvm/llvm-project/commit/6e82a24f4cc585c8b2f69b1ff2cbee443f367187
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXAIF.td
Log Message:
-----------
[RISCV][P-ext] Rename simm8_unsigned/simm10_unsigned used PLUI/PLI. NFC (#188808)
Replace unsigned with plui or pli_b to better indicate their usage.
Templatize the render function and rename it addSExtImm instead of
addSImm*Unsigned.
Commit: f2f54b6874a3f2b0635866953e43348b0a746029
https://github.com/llvm/llvm-project/commit/f2f54b6874a3f2b0635866953e43348b0a746029
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rv32p.ll
Log Message:
-----------
[RISCV][P-ext] Support i32 avgfloors/avgflooru on RV32. (#189736)
Commit: 911dc4139dce1999c72144a9656f65caffca555b
https://github.com/llvm/llvm-project/commit/911dc4139dce1999c72144a9656f65caffca555b
Author: PiJoules <leonardchan at google.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M compiler-rt/test/asan/TestCases/Linux/free_aligned_sized_mismatch.cpp
Log Message:
-----------
[compiler-rt][asan] Forward fix for free_aligned_sized_mismatch.cpp (#189760)
Mark this test as UNSUPPORTED for android since android's libc doesn't
seem to support aligned_alloc.
Commit: d8e9e0af1cb6e08659f703697b44895e614a3a21
https://github.com/llvm/llvm-project/commit/d8e9e0af1cb6e08659f703697b44895e614a3a21
Author: vporpo <vasileios.porpodas at amd.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/docs/SandboxVectorizer.md
A llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Transforms/Vectorize/CMakeLists.txt
A llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/PassRegistry.def
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizerPassBuilder.cpp
A llvm/test/Transforms/SandboxVectorizer/load_store_vec.ll
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
Log Message:
-----------
[SandboxVec][LoadStoreVec] Initial pass implementation (#188308)
This patch implements a new simple region pass that can vectorize
store-load chains.
Commit: b7dc4ff0abee9f5210ba225d6e3c83bac338eae3
https://github.com/llvm/llvm-project/commit/b7dc4ff0abee9f5210ba225d6e3c83bac338eae3
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Log Message:
-----------
[TargetLowering] Replace always true if with an assert. NFC (#189750)
We already returned for UADDSAT/USUBSAT leaving SADDSAT/SSUBSAT as the
only opcodes that can get here.
Commit: 89dec12692c7654455977932cf99d643e58b3157
https://github.com/llvm/llvm-project/commit/89dec12692c7654455977932cf99d643e58b3157
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M lldb/include/lldb/Target/Platform.h
M lldb/source/Core/Module.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.h
M lldb/source/Target/Platform.cpp
M lldb/unittests/Platform/PlatformDarwinTest.cpp
M lldb/unittests/Platform/PlatformTest.cpp
Log Message:
-----------
[lldb][Platform] Handle LoadScriptFromSymFile per-module FileSpec (#189696)
This patch changes the `Platform::LocateXXX` to return a map from
`FileSpec` to `LoadScriptFromSymFile` enum.
This is needed for https://github.com/llvm/llvm-project/pull/188722,
where I intend to set `LoadScriptFromSymFile` per-module.
By default the `Platform::LocateXXX` set the value to whatever the
target's current `target.load-script-from-symbol-file` is set to. In
https://github.com/llvm/llvm-project/pull/188722 we'll allow overriding
this per-target setting on a per-module basis.
Drive-by:
* Added logging when we fail to load a script.
Commit: c9bc317d6dea4b5aef40c35a443cc3083aab65c7
https://github.com/llvm/llvm-project/commit/c9bc317d6dea4b5aef40c35a443cc3083aab65c7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rv32p.ll
Log Message:
-----------
[RISCV][P-ext] Support i32 ushlsat on RV32. (#189730)
We have a sshl instruction on RV32 in the 0.21 spec. Unfortunately,
we don't have a SSLLI instruction, but we can put a constant shift
amount in a register.
Commit: cdce9cd4a19f15b9a100b3aeb6b37a79395a0c53
https://github.com/llvm/llvm-project/commit/cdce9cd4a19f15b9a100b3aeb6b37a79395a0c53
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes b813b0b (#189759)
This fixes b813b0b4e485b0323b51071aca7a415b30c3aa6f.
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: c19e28d854e22b336d7aad78b88946864cd6eb13
https://github.com/llvm/llvm-project/commit/c19e28d854e22b336d7aad78b88946864cd6eb13
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/include/llvm/IR/Intrinsics.td
M llvm/test/CMakeLists.txt
M llvm/test/TableGen/intrinsic-arginfo-error.td
A llvm/test/TableGen/intrinsic-overload-dependent-type-validation.td
Log Message:
-----------
[NFC][LLVM] Simplify `TypeInfoGen` in Intrinsics.td (#189278)
Eliminate `MappingRIdx` by making it an identity function. Currently,
`MappingRIdx` is used to map the index of an `llvm_any*` type in an
intrinsic type signature to its overload index. Eliminating this mapping
means that dependent types in LLVM intrinsic definitions (like
`LLVMMatchType` and its subclasses) should use the overload index to
reference the overload type that it depends on (and not the index within
the llvm_any* subset of overloaded types).
See
https://discourse.llvm.org/t/rfc-simplifying-intrinsics-type-signature-iit-info-generation-encoding-in-intrinsicemitter-cpp/90383
Commit: 5d624b5b937ce0965efbd101defbad956d0f8e4d
https://github.com/llvm/llvm-project/commit/5d624b5b937ce0965efbd101defbad956d0f8e4d
Author: Henry Jiang <henry_jiang2 at apple.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
A llvm/test/Transforms/LoopVectorize/noalias-scope-decl-outer-loop.ll
A llvm/test/Transforms/LoopVectorize/non-widenable-intrinsics-outer-loop.ll
Log Message:
-----------
[VPlan] Stop outerloop vectorization from vectorizing nonvector intrinsics (#185347)
In outer-loop VPlan, avoid emitting vector intrinsic calls for intrinsics
without a vector form. In VPRecipeBuilder, detect missing vector intrinsic
mapping and emit scalar handling instead of a vector call.
Also fix assertion when `llvm.pseudoprobe` in VPlan's native path is being
treated as a `WIDEN-INTRINSIC`.
Reproducer: https://godbolt.org/z/GsPYobvYs
Commit: c20e233020c43e87be08f36d0ca5287bb69ea9f4
https://github.com/llvm/llvm-project/commit/c20e233020c43e87be08f36d0ca5287bb69ea9f4
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/constant-based-reductions.ll
Log Message:
-----------
[SLP] Replace TrackedToOrig DenseMap with parallel SmallVector in reduction
Replace the DenseMap<Value*, Value*> TrackedToOrig with a SmallVector<Value*>
indexed in parallel with Candidates. This avoids hash-table overhead for the
tracked-value-to-original-value mapping in horizontal reduction processing.
Fixes #189686
Commit: bf50489eeba2126c526c8d57f73448fa48429d3f
https://github.com/llvm/llvm-project/commit/bf50489eeba2126c526c8d57f73448fa48429d3f
Author: Henry Jiang <henry_jiang2 at apple.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/test/CodeGen/AArch64/O0-pipeline.ll
M llvm/test/CodeGen/AArch64/O3-pipeline.ll
A llvm/test/Transforms/SampleProfile/pseudo-probe-emit-macho.ll
Log Message:
-----------
[Psuedoprobe][MachO] Enable pseudo probes emission for MachO (#185758)
Enable pseudo probes emission for MachO. Due to the 16 character limit
of MachO segment and section, the file sections will be
`__PSEUDO_PROBE,__probes` and `__PSEUDO_PROBE,__probe_descs`.
Commit: 3f2a9c6f5486e4202ec01e61fbef0e7d094e2371
https://github.com/llvm/llvm-project/commit/3f2a9c6f5486e4202ec01e61fbef0e7d094e2371
Author: jinge90 <ge.jin at intel.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M compiler-rt/lib/builtins/int_math.h
M compiler-rt/lib/builtins/muldc3.c
Log Message:
-----------
[NFC][compiler-rt] Use __builtin_huge_val for CRT_INFINITY for double precision (#188197)
Commit: 2f8c0cbac0d755240112e3b62a628c59655be317
https://github.com/llvm/llvm-project/commit/2f8c0cbac0d755240112e3b62a628c59655be317
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.cpp
Log Message:
-----------
[RISCV] Use a switch default+llvm_unreachable instead of an assert. NFC (#189770)
Commit: 2b98f7fc3db5f99c6b1c152affb5d5906896154d
https://github.com/llvm/llvm-project/commit/2b98f7fc3db5f99c6b1c152affb5d5906896154d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Log Message:
-----------
[RISCV] Slightly optimize insertVSETMTK. NFC (#189771)
Sink the hasTKOp and hasTMOp checks into the switch.
Commit: f8b0a8c631eb3d88c990fb96b4488e4e02e137fc
https://github.com/llvm/llvm-project/commit/f8b0a8c631eb3d88c990fb96b4488e4e02e137fc
Author: Sirui Mu <msrlancern at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/test/CIR/CodeGen/atomic-scoped.c
Log Message:
-----------
[CIR] Scoped atomic fetch uinc/dec (#189688)
Commit: 9085f74018a4f465afa84815d64af850f09b733f
https://github.com/llvm/llvm-project/commit/9085f74018a4f465afa84815d64af850f09b733f
Author: Fangrui Song <i at maskray.me>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/Support/Parallel.h
M llvm/lib/Support/Parallel.cpp
Log Message:
-----------
[Support] Optimize parallel `TaskGroup` (#189196)
Two improvements to reduce `TaskGroup::spawn()` overhead:
1. Replace mutex-based `Latch::inc()` with atomic `fetch_add`. `dec()`
retains the mutex to prevent a race where `sync()` observes Count==0
and destroys the Latch while `dec()` is still running.
2. Pass `Latch&` through `Executor::add()` so the worker calls `dec()`
directly, eliminating the wrapper lambda that previously captured
both the user's callable and the Latch reference. This avoids one
`std::function` construction and potential heap allocation per spawn.
Commit: 7fce7631a0983b09abc968d24038e01ec1d02962
https://github.com/llvm/llvm-project/commit/7fce7631a0983b09abc968d24038e01ec1d02962
Author: Krzysztof Drewniak <krzysdrewniak at gmail.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M mlir/include/mlir/IR/ExtensibleDialect.h
M mlir/include/mlir/IR/OpDefinition.h
M mlir/include/mlir/IR/Operation.h
M mlir/include/mlir/IR/OperationSupport.h
M mlir/include/mlir/Interfaces/InferTypeOpInterface.td
M mlir/lib/AsmParser/Parser.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/lib/CAPI/Interfaces/Interfaces.cpp
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/SMT/IR/SMTOps.cpp
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/WasmSSA/IR/WasmSSAOps.cpp
M mlir/lib/IR/ExtensibleDialect.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/lib/IR/Operation.cpp
M mlir/lib/IR/OperationSupport.cpp
M mlir/lib/Target/IRDLToCpp/Templates/PerOperationDecl.txt
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/lib/Dialect/Test/TestOpsSyntax.cpp
M mlir/test/lib/Dialect/Test/TestOpsSyntax.td
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
M mlir/test/mlir-tblgen/op-decl-and-defs.td
M mlir/test/python/python_test_ops.td
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/unittests/Debug/FileLineColLocBreakpointManagerTest.cpp
M mlir/unittests/IR/OperationSupportTest.cpp
M mlir/unittests/IR/ValueTest.cpp
M mlir/unittests/IR/VerifierTest.cpp
M mlir/unittests/Interfaces/MemorySlotUtilsTest.cpp
M mlir/unittests/Transforms/DialectConversion.cpp
Log Message:
-----------
[mlir] Refactor opaque properties to make them type-safe (#185157)
At its core, this commit changes `OpaqueProperties` (aka a void*) to
`PropertyRef`, which is a {TypeID, void*}, where the TypeID is the ID of
the storage type of the given property (which can, as is often the case
for operations, be a struct of other properties).
Long-term, this change will allow for
1) Some sort of getFooPropertyRef() on property structs, allowing
individual members to be extracted generically
2) By having a property kind that is an OwningProprtyRef, generic
parsing (in combination with a bunch of other changes) 3) Probably a
safer C/Python API because we'll be able to indicate what's supposed to
be under a given void*
---------
Co-authored-by: Claude Opus 4.6 <noreply at anthropic.com>
Commit: 6581d588193ce6c51700b426072da350895b95a2
https://github.com/llvm/llvm-project/commit/6581d588193ce6c51700b426072da350895b95a2
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/test/Analysis/DependenceAnalysis/PR188098.ll
Log Message:
-----------
[DA] Revise test `PR188098.ll` (NFC) (#189564)
This patch revises the test `Analysis/DependenceAnalysis/PR188098.ll`
added in #189428, primary to improve readability. I confirmed that this
test cashes without the change added in #188098.
Commit: d52a5e8a5ac47fea1b1d82669eb7d1bf5283d147
https://github.com/llvm/llvm-project/commit/d52a5e8a5ac47fea1b1d82669eb7d1bf5283d147
Author: AidinT <at.aidin at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/include/mlir/Conversion/CMakeLists.txt
A mlir/include/mlir/Conversion/ConvertToEmitC/CMakeLists.txt
A mlir/include/mlir/Conversion/ConvertToEmitC/ConvertToEmitCPatternInterface.td
M mlir/include/mlir/Conversion/ConvertToEmitC/ToEmitCInterface.h
M mlir/lib/Conversion/ArithToEmitC/ArithToEmitC.cpp
M mlir/lib/Conversion/ConvertToEmitC/CMakeLists.txt
M mlir/lib/Conversion/FuncToEmitC/FuncToEmitC.cpp
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitC.cpp
M mlir/lib/Conversion/SCFToEmitC/SCFToEmitC.cpp
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[MLIR] convert ConvertToEmitCPatternInterface to ODS (#188621)
This PR converts `ConvertToEmitCPatternInterface` dialect interface to ODS. Also makes changes to derived classes.
Commit: 585e2a015b29c1a53c4acddeda1b64b3fb3aac39
https://github.com/llvm/llvm-project/commit/585e2a015b29c1a53c4acddeda1b64b3fb3aac39
Author: AidinT <at.aidin at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
A mlir/include/mlir/Bytecode/BytecodeDialectInterface.td
M mlir/include/mlir/Bytecode/BytecodeImplementation.h
M mlir/include/mlir/Bytecode/CMakeLists.txt
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
[MLIR] Convert BytecodeDialectInterface to ods (#188852)
This PR converts `BytecodeDialectInterface` to ODS.
Commit: aefca764062a8dd0f6a26d94f78f9ef6a3731aa4
https://github.com/llvm/llvm-project/commit/aefca764062a8dd0f6a26d94f78f9ef6a3731aa4
Author: Thurston Dang <thurston at google.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512vl-intrinsics.ll
Log Message:
-----------
[msan] Add missing non-mem PMOV handling (#189768)
This adds support for the remaining non-memory PMOV intrinsics, using
the existing handlers.
handleAVX512VectorDownConvert() is slightly updated to handle cases
where there are fewer than 8 output elements (for which the mask is
still supplied as 8 bits).
Commit: 512071941da849587b8988f7e74c30c46b377a2c
https://github.com/llvm/llvm-project/commit/512071941da849587b8988f7e74c30c46b377a2c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-31 (Tue, 31 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rv32p.ll
M llvm/test/CodeGen/RISCV/rv64p.ll
Log Message:
-----------
[RISCV] Add codegen support for SATI and USATI. (#189532)
Implementation is largely based on ARM which has similar instructions.
Commit: fe6d15ddbfd44d4a95fd2d292b1b0b431377a0dd
https://github.com/llvm/llvm-project/commit/fe6d15ddbfd44d4a95fd2d292b1b0b431377a0dd
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/lib/Serialization/ASTWriterDecl.cpp
A clang/test/Modules/pr189415.cppm
Log Message:
-----------
[C++20] [Modules] Fix thread_local variable handling in modules (#189796)
Close https://github.com/llvm/llvm-project/issues/189415
The function shouldVarGenerateHereOnly should also handle thread_local
variables, not just static variables. This fixes incorrect code
generation for thread_local variables in named modules.
Commit: 1d549d9a777a6faef6d425cb6482ab1fa6b91bb7
https://github.com/llvm/llvm-project/commit/1d549d9a777a6faef6d425cb6482ab1fa6b91bb7
Author: Luke Lau <luke at igalia.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
Log Message:
-----------
[RISCV] Remove codegen for vp_lrint, vp_llrint (#189714)
Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999
This splits off two intrinsics from #179622.
We need to use the other intrinsic constructor in
ExpandVectorPredication.cpp because llrint has multiple overloaded types
Commit: 3068132e32c11839c2626347d5288f16d6623bea
https://github.com/llvm/llvm-project/commit/3068132e32c11839c2626347d5288f16d6623bea
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Use bind_front in tryToOptimizeInductionTruncate (NFC) (#189763)
Commit: 7e8449a96d552e22c927eccc439882464a3f2f28
https://github.com/llvm/llvm-project/commit/7e8449a96d552e22c927eccc439882464a3f2f28
Author: Weibo He <NewSigma at 163.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
Log Message:
-----------
[CoroSplit] Drop assumption that promise alloca is not accessed before coro.begin (NFC) (#189521)
There is an inconsistency in that the code assumes the promise alloca is
not modified before coro.begin, yet it handles such accesses later. This
patch proposes dropping that assumption and analyzing accesses before
coro.begin from the outset, allowing #189295 to erase promise alloca
without analyse it afterwards.
Commit: 8edbf230980a038f120e754439a79cec68ad9356
https://github.com/llvm/llvm-project/commit/8edbf230980a038f120e754439a79cec68ad9356
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/test/AST/ByteCode/codegen-constexpr-unknown.cpp
M clang/test/AST/ByteCode/cxx26.cpp
Log Message:
-----------
[clang][bytecode] Revisit reference variables as constexpr-unknown in C++26 (#187918)
When revisiting `const T& range = f(T());`, we do mark the variable for
`range` as constexpr-unknown, but not the temporary variable we create
for `T()`. Change that.
Then we also need to ignore constexpr-unknown pointers in
`CheckInvoke()`.
Fixes https://github.com/llvm/llvm-project/issues/187775
Commit: 21f94950a8411d0a10eaf3380ae44b411f65a0d3
https://github.com/llvm/llvm-project/commit/21f94950a8411d0a10eaf3380ae44b411f65a0d3
Author: Hans Wennborg <hans at hanshq.net>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M compiler-rt/test/sanitizer_common/TestCases/Linux/soft_rss_limit_mb_test.cpp
Log Message:
-----------
[compiler-rt] Try bumping soft_rss_limit again (#188441)
Previous instance: #171469
Commit: 6a31be68e38e4656354edddfcb137b0c8234a01c
https://github.com/llvm/llvm-project/commit/6a31be68e38e4656354edddfcb137b0c8234a01c
Author: Lukas Sommer <lukas.sommer at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/include/mlir/IR/OperationSupport.h
Log Message:
-----------
[mlir][NFC] Remove conditionally unused type alias (#189894)
The `RawType` type alias is unused (`-Wunused-local-typedef`) in build
with asserts deactivated. In combination with `-Werror`, this causes
builds to fail.
Signed-off-by: Lukas Sommer <lukas.sommer at amd.com>
Commit: 2e51fdaa774be8e0d6b4d6743a2f77cdb3a71e3c
https://github.com/llvm/llvm-project/commit/2e51fdaa774be8e0d6b4d6743a2f77cdb3a71e3c
Author: David Spickett <david.spickett at arm.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M lldb/include/lldb/Target/MemoryRegionInfo.h
M lldb/include/lldb/lldb-private-enumerations.h
M lldb/source/API/SBMemoryRegionInfo.cpp
M lldb/source/Commands/CommandObjectMemory.cpp
M lldb/source/Expression/IRMemoryMap.cpp
M lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp
M lldb/source/Plugins/Process/FreeBSD/NativeProcessFreeBSD.cpp
M lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp
M lldb/source/Plugins/Process/NetBSD/NativeProcessNetBSD.cpp
M lldb/source/Plugins/Process/Utility/LinuxProcMaps.cpp
M lldb/source/Plugins/Process/Utility/MemoryTagManagerAArch64MTE.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.cpp
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp
M lldb/source/Plugins/Process/minidump/MinidumpParser.cpp
M lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp
M lldb/source/Target/MemoryRegionInfo.cpp
M lldb/source/Target/Process.cpp
M lldb/unittests/Process/Utility/LinuxProcMapsTest.cpp
M lldb/unittests/Process/Utility/MemoryTagManagerAArch64MTETest.cpp
M lldb/unittests/Process/gdb-remote/GDBRemoteCommunicationClientTest.cpp
M lldb/unittests/Process/minidump/MinidumpParserTest.cpp
M lldb/unittests/Target/MemoryRegionInfoTest.cpp
Log Message:
-----------
[lldb] Replace OptionalBool with LazyBool (#189652)
The only difference between them is that OptionalBool's third state
is "unknown" and LazyBool's is "calculate". We don't need to tell
the difference in a single context, so I've made a new eLazyBoolDontKnow
which is an alias of eLazyBoolCalculate.
Commit: eeb2fae5c00586e0764be907336e3de27af2b3b1
https://github.com/llvm/llvm-project/commit/eeb2fae5c00586e0764be907336e3de27af2b3b1
Author: David Green <david.green at arm.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/dup.ll
Log Message:
-----------
[AArch64][GISel] Do not bitcast nonpower2 element size G_CONCATs (#189911)
This currently gets stuck in a loop, unable to make progress throught
the
bitcast concat. Limit it to legal element sizes so that we always make
progress
and at least fall back to SDAG as opposed to crashing or getting stuck.
Commit: 2313989499b5ee9befd9865310f6fa02f561cf63
https://github.com/llvm/llvm-project/commit/2313989499b5ee9befd9865310f6fa02f561cf63
Author: VASU SHARMA <44048872+vasu-the-sharma at users.noreply.github.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
A clang/test/CodeGen/ubsan-aggregate-null-align.c
Log Message:
-----------
[UBSAN] [NFC] pre-commit tests for null, alignment, bounds checks (#176210)
PR to add precommit tests to document current UBSAN behavior for
aggregate copy operations.
The test covers:
- Sanitizers: null, alignment, bounds
- Type variants: plain, _Atomic (C), volatile (C)
- Operand forms: arr[idx], *ptr
- Operations: assignment, initialization, initializer list, variadic
args, nested member access
- C++ specific: direct/brace/copy-list init, new expressions, casts,
operator=, virtual base init
- Bounds checking: in-bounds access, past-the-end access (index ==
size), beyond bounds access, dynamic index
---------
Co-authored-by: vasu-ibm <Vasu.Sharma2 at ibm.com>
Co-authored-by: Tony Varghese <tonypalampalliyil at gmail.com>
Commit: b1f8c285597925428d1f110ad7c1accff70eb885
https://github.com/llvm/llvm-project/commit/b1f8c285597925428d1f110ad7c1accff70eb885
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/include/mlir/IR/BuiltinAttributes.td
M mlir/unittests/IR/AttributeTest.cpp
Log Message:
-----------
[MLIR] Validate APInt bitwidth in IntegerAttr::get(Type, APInt) (#188725)
IntegerAttr::get(Type, APInt) did not validate that the APInt's bit
width matched the expected bit width for the given type. For integer
types, the APInt width must equal the integer type's width. For index
types, the APInt width must equal IndexType::kInternalStorageBitWidth
(64 bits).
Passing an APInt with the wrong bit width could cause a
non-deterministic crash in StorageUniquer when comparing two IntegerAttr
instances for the same type but with different APInt widths.
This commit adds assertions in the get(Type, APInt) builder to catch
such misuse early in debug builds, providing a clear error message at
the call site rather than a cryptic crash in the storage uniquer.
Fixes #56401
Assisted-by: Claude Code
Commit: 249e871fa4ef9acc38f8aa02f124322f85635756
https://github.com/llvm/llvm-project/commit/249e871fa4ef9acc38f8aa02f124322f85635756
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
Log Message:
-----------
[MLIR][ArithToLLVM] Fix index_cast on memref types generating invalid LLVM IR (#189227)
`arith.index_cast` and `arith.index_castui` accept memref operands (via
`IndexCastTypeConstraint`), but `IndexCastOpLowering::matchAndRewrite`
did not handle this case. When the operand was a memref, the conversion
framework substituted the converted LLVM struct type, and the lowering
incorrectly attempted to emit `llvm.sext`/`llvm.zext`/`llvm.trunc` on a
struct value, producing invalid LLVM IR.
Since LLVM uses opaque pointers, all memrefs with integer or index
element types lower to the same `\!llvm.struct<(ptr, ptr, i64, ...)>`
type, making `arith.index_cast` on memrefs a no-op at the LLVM level.
Add a check that treats the memref case as an identity conversion (same
as the same-bit-width path).
Fixes #92377
Assisted-by: Claude Code
Commit: 5651490992f3f5da7f39b228f019631725ff9d7f
https://github.com/llvm/llvm-project/commit/5651490992f3f5da7f39b228f019631725ff9d7f
Author: lrzlin <linrunze at loongson.cn>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
A llvm/test/CodeGen/LoongArch/mergestores.ll
Log Message:
-----------
[LoongArch] Implement canMergeStoresTo to avoid crash while NoImplicitFloat attribute is set (#188005)
Currently, when the `NoImplicitFloat` attribute is set, consecutive
64-bit load
and store operations will be combined into 128-bit ones, which is
illegal
because that attribute makes floating point and SIMD unavailable.
By implementing the canMergeStoresTo, we can prevent this incorrect
merging.
Fixes https://github.com/llvm/llvm-project/issues/186645
Commit: 6b2b0da40de1495ace2b100799a35711f7ad7b21
https://github.com/llvm/llvm-project/commit/6b2b0da40de1495ace2b100799a35711f7ad7b21
Author: lonely eagle <2020382038 at qq.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/lib/Transforms/CSE.cpp
Log Message:
-----------
[mlir][CSE] Fix double-counting of numCSE statistic (#189802)
This PR fixes a regression where the numCSE statistic was being
incremented twice for a single operation elimination. The numCSE counter
is already internally incremented within the replaceUsesAndDelete
function. Manually incrementing it again after the function call leads
to an inaccurate total count. This is part of the
https://github.com/llvm/llvm-project/pull/180556.
Commit: 71cc59400c531d1f9c4a928dae62d20cca3690bd
https://github.com/llvm/llvm-project/commit/71cc59400c531d1f9c4a928dae62d20cca3690bd
Author: Ruoyu Qiu <cabbaken at outlook.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Analysis/DependenceAnalysis.cpp
Log Message:
-----------
[DA] add debug log in findGCD (#189537)
Commit: c5363f2166710b0c6e728d5ee11efc99ccf42d87
https://github.com/llvm/llvm-project/commit/c5363f2166710b0c6e728d5ee11efc99ccf42d87
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/IR/Core.cpp
M llvm/tools/llvm-c-test/echo.cpp
Log Message:
-----------
[IR] Fix C API after getTerminator() change (#189922)
The C API function LLVMGetBasicBlockTerminator should return NULL when
the basic block is not well-formed.
Commit: 6bf794a02a509bf051c50fe2f14009e117ef50ed
https://github.com/llvm/llvm-project/commit/6bf794a02a509bf051c50fe2f14009e117ef50ed
Author: Daniil Fukalov <dfukalov at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/test/CodeGenCUDA/fp-contract.cu
M llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/basic-branch.ll
M llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-alloca-issue-155902.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/load-global-invariant.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2x16.ll
M llvm/test/CodeGen/AMDGPU/select-phi-s16-fp.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
M llvm/test/CodeGen/AMDGPU/smfmac_alloc_failure_no_agpr_O0.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr-update-regscavenger.ll
M llvm/test/CodeGen/AMDGPU/spill-wide-sgpr.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
M llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/wait-xcnt-atomic-rmw-optimization.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/zext-lid.ll
Log Message:
-----------
[AMDGPU] Disable generic DAG combines at -O0 to preserve debuggability. (#176304)
Disable generic DAG combines for AMDGPU at -O0 via
disableGenericCombines() to preserve instructions that users may want to
set breakpoints on during debugging.
Assisted-by: Cursor / Claude Opus 4.6
Commit: 97562e7e5cae5d6dc019b8f3275eb9639978c05f
https://github.com/llvm/llvm-project/commit/97562e7e5cae5d6dc019b8f3275eb9639978c05f
Author: Andrew Marshall <planetmarshall at users.noreply.github.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M compiler-rt/cmake/Modules/CheckAssemblerFlag.cmake
Log Message:
-----------
pass target triple to `check_assembler_flag` (#188521)
Target specific flags (Notably `-mimplict=always` for ARM) are not
recognized by the clang assembler unless the target is specified. This
PR passes the value of `CMAKE_C_COMPILER_TARGET` to the assembler so
that target specific flags are recognized.
## Previous behaviour
When configuring builtins for an ARMv7 target:
```
-- Builtin supported architectures: armv7
-- Checking for assembler flag -mimplicit-it=always
-- Checking for assembler flag -mimplicit-it=always - Not accepted
-- Checking for assembler flag -Wa,-mimplicit-it=always
-- Checking for assembler flag -Wa,-mimplicit-it=always - Not accepted
CMake Warning at CMakeLists.txt:462 (message):
Don't know how to set the -mimplicit-it=always flag in this assembler; not
including Arm optimized implementations
```
## New behaviour
```
-- Builtin supported architectures: armv7
-- Checking for assembler flag -mimplicit-it=always
-- Checking for assembler flag -mimplicit-it=always - Accepted
```
## Steps to reproduce:
```
$ cmake -S compiler-rt/lib/builtins -B build \
-DCMAKE_C_COMPILER=clang \
-DCMAKE_C_COMPILER_TARGET=armv7-unknown-linux-gnueabihf \
-DCOMPILER_RT_DEFAULT_TARGET_ONLY=ON
```
Commit: d6cd15901a7b17657687c330afa7ee974e27e3be
https://github.com/llvm/llvm-project/commit/d6cd15901a7b17657687c330afa7ee974e27e3be
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
M llvm/test/MC/AArch64/armv9a-tlbip.s
Log Message:
-----------
[AArch64][llvm] Gate some `tlbip` insns with either +tlbid or +d128 (#178913)
Change the gating of `tlbip` instructions (`sysp` aliases) containing
`*E1IS*`, `*E1OS*`, `*E2IS*` or `*E2OS*` to be used with `+tlbid` or
`+d128`. This is because the 2025 Armv9.7-A MemSys specification says:
```
All TLBIP *E1IS*, TLBIP *E1OS*, TLBIP *E2IS* and TLBIP *E2OS*
instructions that are currently dependent on FEAT_D128 are updated
to be dependent on FEAT_D128 or FEAT_TLBID
```
See also change #178912 where the gating of `+d128` for `sysp` was
removed.
Commit: f6ffdbcbaec23f54a9254c7e19df002f1a0a9425
https://github.com/llvm/llvm-project/commit/f6ffdbcbaec23f54a9254c7e19df002f1a0a9425
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/test/Dialect/Affine/scalrep.mlir
Log Message:
-----------
[MLIR][Affine] Fix dead store elimination for vector stores with different types (#189248)
affine-scalrep's findUnusedStore incorrectly classified an
affine.vector_store as dead when a subsequent store wrote to the same
base index but with a smaller vector type. A vector<1xi64> store at
[0,0] does not fully overwrite a vector<5xi64> store at [0,0], so the
first store must be preserved.
The loadCSE function in the same file already had the correct
type-equality check for loads; this patch adds the analogous check for
stores in findUnusedStore.
Fixes #113687
Assisted-by: Claude Code
Commit: f2685fabc5bbe33a8b95b665dc4e24223c42fdd9
https://github.com/llvm/llvm-project/commit/f2685fabc5bbe33a8b95b665dc4e24223c42fdd9
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
Log Message:
-----------
[clang][bytecode] Disable tail calls on sparc (#189887)
Looks like this causes problems there as well:
https://lab.llvm.org/buildbot/#/builders/114/builds/252
Interp.cpp:2572:21: error: cannot tail-call: target is not able to
optimize the call into a sibling call
2572 | MUSTTAIL return Fn(S, PC);
| ~~^~~~~~~
Commit: effcd181e580c6f83dfc88a0362705ddb6601f5b
https://github.com/llvm/llvm-project/commit/effcd181e580c6f83dfc88a0362705ddb6601f5b
Author: Luke Lau <luke at igalia.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
Log Message:
-----------
[RISCV] Remove codegen for VP float rounding intrinsics (#189896)
Part of the work to remove trivial VP intrinsics from the RISC-V
backend, see
https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999
This splits off seven intrinsics from #179622.
We now generate vfcvt.rtz for llvm.vp.roundtozero. It looks like we
should have been using the codegen for llvm.trunc for it, but we somehow
missed that.
Commit: 0d33a15d3320567639dd8f043c7aa22a55653dab
https://github.com/llvm/llvm-project/commit/0d33a15d3320567639dd8f043c7aa22a55653dab
Author: Hans Wennborg <hans at hanshq.net>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/test/Modules/pr189415.cppm
Log Message:
-----------
Add a target triple to clang/test/Modules/pr189415.cppm (#189937)
Not all targets support thread_local, so in some environments the test
would fail with:
tools/clang/test/Modules/Output/pr189415.cppm.tmp/counter.cppm:6:1:
error: thread-local storage is not supported for the current target
Follow-up to #189796
Commit: 5249f5ad4d91826507fae4b7d776d1eeabc9bb2a
https://github.com/llvm/llvm-project/commit/5249f5ad4d91826507fae4b7d776d1eeabc9bb2a
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h
M llvm/lib/MCA/HardwareUnits/ResourceManager.cpp
Log Message:
-----------
[MCA] Make `ResourceSizeMask` const (#189453)
This patch marks the already effectively constant `ResourceSizeMask` as
`const`. It adds a helper `computeResourceSizeMask()` to initialize it
in the member initializer list.
Commit: 8a06085c610a49739beb0af716a30714f073540c
https://github.com/llvm/llvm-project/commit/8a06085c610a49739beb0af716a30714f073540c
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/CodeGen/Rematerializer.h
M llvm/lib/CodeGen/Rematerializer.cpp
Log Message:
-----------
[CodeGen] Add listener support to the rematerializer (NFC) (#184338)
This change adds support for adding listeners to the target-independent
rematerializer; listeners can catch certain rematerialization-related
events to implement some additional functionality on top of what the
rematerializer already performs.
This is NFC and has no user at the moment, but the plan is to have
listeners start being responsible for secondary/optional functionalities
that are at the moment integrated with the rematerializer itself. Two
examples of that are:
1. rollback support (currently optional), and
2. region tracking (currently mandatory, but not fundamentally necessary
to the rematerializer).
Commit: 042997bd15a52ef435673e9182ed5cd2453f8ab0
https://github.com/llvm/llvm-project/commit/042997bd15a52ef435673e9182ed5cd2453f8ab0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
A llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
Log Message:
-----------
[RISCV] combine-is_fpclass.ll - add initial tests showing failure to constant fold ISD::IS_FPCLASS nodes (#189940)
Commit: 3b1125b1edf997e261ebafdf31b1828f5c458ebb
https://github.com/llvm/llvm-project/commit/3b1125b1edf997e261ebafdf31b1828f5c458ebb
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/lib/Analysis/ScalarEvolution.cpp
Log Message:
-----------
[SCEV] Add canonical SCEV pointer and construct canonical SCEVs (NFC) (#188858)
Add a canonical SCEV pointer to SCEV, to support comparing SCEVs for
equality, even with different use-specific flags.
Currently this should be NFC, as nothing yet sets use flags.
Compile-time impact:
https://llvm-compile-time-tracker.com/compare.php?from=13f1fd006243f756417c3ae992342c0674e3f04e&to=e7f46bcf8bef62c619380fbcccbe6073300b69fe&stat=instructions:u
+0.03% - +0.05% on stage1 configs
-0.03% surprisingly for stage2-O3
PR: https://github.com/llvm/llvm-project/pull/188858
Commit: 26b755c09bfa5b5e31c3cef8d4118316b2937cdd
https://github.com/llvm/llvm-project/commit/26b755c09bfa5b5e31c3cef8d4118316b2937cdd
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/IR/GlobalObject.h
M llvm/include/llvm/IR/Instruction.h
M llvm/include/llvm/IR/Value.h
M llvm/lib/IR/Globals.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/IR/Value.cpp
Log Message:
-----------
[IR] Remove Value::HasMetadata (#189917)
Metadata already has two separate implementations, one for GlobalObject
and one for Instruction. Instruction was already separate due to special
MD_dbg handling, so move the GlobalObject-specific metadata parts from
Value to GlobalObject.
The HasMetadata bit, originally an optimization to avoid the hash table
lookup when a value has no metadata, is no longer needed, because the
information is now stored directly in Instruction/GlobalObject's
MetadataIndex field.
This also fixes MSan builds, currently ~Value clears metadata and
therefore needs to access the subclass's MetadataIndex field, which was
already destructed at this point.
Commit: c67092066e1812bdbec10e4a3628a5f77faa8f9f
https://github.com/llvm/llvm-project/commit/c67092066e1812bdbec10e4a3628a5f77faa8f9f
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/lib/Lex/TokenLexer.cpp
M clang/test/Lexer/gnu-flags.c
A clang/test/Lexer/gnu-zero-variadic-macro-argument-fixit.c
M clang/test/Preprocessor/macro_fn.c
Log Message:
-----------
[clang] Suggest using __VA_OPT__(,) instead of GNU zero variadic macro argument (#188624)
Also provide an appropriate fixit.
Commit: 96db944036a09e773d1e3fff4fa3805a4f75e59e
https://github.com/llvm/llvm-project/commit/96db944036a09e773d1e3fff4fa3805a4f75e59e
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/test/CodeGen/SPIRV/spec_const_decoration.ll
Log Message:
-----------
[NFC][SPIR-V] Remove stale XFAIL for spec_const_decoration.ll (#189934)
The test no longer fails with expensive_checks enabled
```
Unexpectedly Passed Tests (1):
LLVM :: CodeGen/SPIRV/spec_const_decoration.ll
```
after
https://github.com/llvm/llvm-project/commit/18e695890306c6824cc15779e1acb7e5956cbec1
(https://github.com/llvm/llvm-project/pull/134016)
also add `-verify-machineinstrs` as per #188703
Commit: 69b116d07503061026ffddbaf74e4b33615fc205
https://github.com/llvm/llvm-project/commit/69b116d07503061026ffddbaf74e4b33615fc205
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/test/CodeGen/SPIRV/instructions/vector-shuffle.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpVectorExtractDynamic.ll
Log Message:
-----------
[SPIR-V] Fix OpVectorExtractDynamic operand type (#189635)
vID is a register class for integer vector registers only. vfID (float
vector registers) should be also accepted. Aligning the definition with
other instructions of this kind
related to #188703
Commit: ed48aeadf37ad811f5fa999e2de07f1ae05d1e24
https://github.com/llvm/llvm-project/commit/ed48aeadf37ad811f5fa999e2de07f1ae05d1e24
Author: David Spickett <david.spickett at arm.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M lldb/source/Plugins/Architecture/AArch64/ArchitectureAArch64.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
Log Message:
-----------
[lldb][AArch64][Linux] Add support for SME only systems (#165413)
This is the implementation part of #138717, tests and documentation will
be in a separate PR.
SME only systems have SME but not SVE. Previously we assumed that you
would either have SVE, SVE+SME, or neither. On an SME only system, the
SVE register state exists only in streaming mode. SVE instructions may
be used, but only in streaming mode. The Linux kernel will report that
such a processor has SME features but no SVE features.
This means that the non-streaming SVE ptrace register set is
inaccessible (with one exception mentioned below). So the main change
here is around the management of FP registers.
* In non-streaming mode, FP registers must be accessed via the FP
register set. Not the non-streaming SVE register set.
* In streaming mode, FP registers are a subset of the streaming SVE
registers, accessed via the streaming SVE register set.
The one exception the kernel allows is:
> On systems that do not support SVE it is permitted to use SETREGSET to
write SVE_PT_REGS_FPSIMD formatted data via NT_ARM_SVE, in this case the
vector length should be specified as 0. This allows streaming mode to be
disabled on systems with SME but not SVE.
https://docs.kernel.org/arch/arm64/sve.html
This is how we are able to restore to a non-streaming state when an
expression leaves us in streaming mode.
The major changes to LLDB are:
* If we receive only SVG in the expedited registers, we now assume it's
an SME only system and therefore VG == SVG.
* A new state SVEState::StreamingFPSIMD is added to mark the mode where
we are in FPSIMD mode on an SME only system (as opposed to the FPSIMD
state of an SVE or SVE+SME system).
* CalculateFprOffset now returns different results depending on whether
we have only SIMD or we have streaming SVE. In the latter case, the
stored register offsets are relative to the SVE registers, but actual
accesses need to be relative to the ptrace FP register set.
* In WriteAllRegisters, if we have an FP set to restore on an SME only
system we assume we must have been in non-streaming mode at the time of
the save. So we restore it using the previously mentioned non-streaming
SVE write.
* GetSVERegSet and ConfigureRegisterContext were updated to handle the
new StreamingFPSIMDOnly state.
Commit: d14888121db01f9d8f772fa6daaeb4d293085de0
https://github.com/llvm/llvm-project/commit/d14888121db01f9d8f772fa6daaeb4d293085de0
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsInstrInfo.cpp
Log Message:
-----------
[Mips] Correctly report sizes for PATCHABLE_* (#188229)
Report the size of the xray sled.
This came up while working on
https://github.com/llvm/llvm-project/pull/187703.
Commit: 5639c0bb3f721fea802b03aacd531d2a3ac71ac0
https://github.com/llvm/llvm-project/commit/5639c0bb3f721fea802b03aacd531d2a3ac71ac0
Author: David Spickett <david.spickett at arm.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/docs/ReleaseNotes.md
Log Message:
-----------
[llvm][docs] Add release note for LLDB AArch64 Linux SME only support (#189367)
And highlights that some earlier versions have a critical issue on such
systems. This is not something we are able to fix (because the branches
are closed), but users and packagers have some options which are listed
in the issue.
Relates to #138717.
Commit: ab4b689258c21c5e47d1a865b8b980e01395aac7
https://github.com/llvm/llvm-project/commit/ab4b689258c21c5e47d1a865b8b980e01395aac7
Author: Manuel Carrasco <Manuel.Carrasco at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
M llvm/test/CodeGen/AMDGPU/constant-fold-mi-operands.ll
Log Message:
-----------
[AMDGPU][SIFoldOperands] Fix OR -1 fold (#189655)
In SIFoldOperands, folding `or x, -1` to `v_mov_b32 -1` removed
`Src1Idx`, which is incorrect because `-1` is in `Src0Idx` (after
canonicalization).
Closes https://github.com/llvm/llvm-project/issues/189677.
Commit: 2cff995e91c3ff2fe21ae2e5c0bfb7c6746c3029
https://github.com/llvm/llvm-project/commit/2cff995e91c3ff2fe21ae2e5c0bfb7c6746c3029
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
A llvm/lib/Target/AMDGPU/SISpillUtils.cpp
A llvm/lib/Target/AMDGPU/SISpillUtils.h
A llvm/test/CodeGen/AMDGPU/dead-frame-index-dbg-value.ll
Log Message:
-----------
[AMDGPU] Fix crash with dead frame indices in debug values (#183297)
When spill slots are eliminated (VGPR-to-AGPR, SGPR-to-VGPR lanes),
debug values referencing these frame indices were not always properly
cleaned up. This caused an assertion failure in getObjectOffset() when
PrologEpilogInserter tried to access the offset of a dead frame object.
The existing debug fixup code in SIFrameLowering and SILowerSGPRSpills
had two limitations:
1. It only checked one operand position, but DBG_VALUE_LIST instructions
can have multiple debug operands with frame indices.
2. It didn't handle all types of dead frame indices uniformly.
Fix by centralizing debug info cleanup in removeDeadFrameIndices(),
which already knows all frame indices being removed. This iterates over
all debug operands using MI.debug_operands().
Assisted-by: Claude Code.
Commit: 03b5539dd58584e6821e11123d5c8546147a6f41
https://github.com/llvm/llvm-project/commit/03b5539dd58584e6821e11123d5c8546147a6f41
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/ADT/GenericCycleImpl.h
M llvm/unittests/Analysis/CFGTest.cpp
Log Message:
-----------
[ADT] Align `GenericCycle::getExitBlocks`/`getExitingBlocks` methods with LoopBase
Ensure `GenericCycle::getExitBlocks` does not replace the content
of the output vector and behaves as `LoopBase::getExitBlocks`,
previously exposing an issue within `isPotentiallyReachable`.
Fixes: https://github.com/llvm/llvm-project/issues/189800.
Fixes: https://github.com/llvm/llvm-project/issues/189289.
Fixes: https://github.com/llvm/llvm-project/issues/189234.
Fixes: https://github.com/llvm/llvm-project/issues/189180.
Commit: 9d592d9e07509f384c2bc0a29df1a8e4ec516763
https://github.com/llvm/llvm-project/commit/9d592d9e07509f384c2bc0a29df1a8e4ec516763
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Transforms/Scalar/LoopLoadElimination.cpp
M llvm/test/Analysis/LoopAccessAnalysis/invariant-dep-same-ptr.ll
M llvm/test/Analysis/LoopAccessAnalysis/pointer-phis.ll
M llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/loop-distribute.ll.expected
Log Message:
-----------
[LAA] Catch load/store to invariant address in dependency checker. (#187023)
There are some accesses we cannot easily catch with the existing SSA
based tracking of uniform stores.
Extend the dependency checker to reject accesses the same invariant
address for cases SCEV can prove (distance is zero).
For those cases, we would not generate runtime checks for the
problematic pair, as they are part of the same group.
Note that this adds a new InvariantUnsafe kind, similar to
IndirectUnsafe, although maybe it would be sufficient to just have a
single Unsafe kind, with slight loss of precision.
Fixes https://github.com/llvm/llvm-project/issues/186922.
PR: https://github.com/llvm/llvm-project/pull/187023
Commit: bc36746ddfee3ca7724e00311f6371090a43754c
https://github.com/llvm/llvm-project/commit/bc36746ddfee3ca7724e00311f6371090a43754c
Author: David Spickett <david.spickett at arm.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M lldb/docs/use/aarch64-linux.md
Log Message:
-----------
[lldb][docs] Add documentation for AArch64 Linux SME only support (#165415)
As for other features, this is a mixture of user facing decisions and
internal design decisions.
Commit: 23d76784a5aa01140543881f2c27ace6a6545f98
https://github.com/llvm/llvm-project/commit/23d76784a5aa01140543881f2c27ace6a6545f98
Author: David Spickett <david.spickett at arm.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
A lldb/test/API/linux/aarch64/sme_only_registers/Makefile
A lldb/test/API/linux/aarch64/sme_only_registers/TestSMEOnlyRegisters.py
A lldb/test/API/linux/aarch64/sme_only_registers/main.c
Log Message:
-----------
[lldb][AArch64][Linux] Add tests for SME only support (#165414)
This PR is the tests for #138717. I have split it from implementation as
there is a lot of code, and the two don't really overlap. The tests are
checking what a user will see in LLDB, and only indirectly what happens
in lldb-server.
There are two types of tests, the first is register access tests. These
start in a given mode, where a mode is a combination of the streaming
mode on or off, ZA on or off, and a vector length.
For register access tests I have used two states:
* Streaming mode, ZA on, default vector length
* Non-streaming mode, ZA off, default vector length
(changing mode and vector length is tested in existing SVE+SME tests and
the expression tests I'm adding in this same PR)
The test program:
* Sets up the requested mode.
* Allocates a bunch of buffers for LLDB to write expected register
values to.
* Sets initial register values.
Then LLDB looks for those expected values. Assuming they are present, it
then writes a new set of values to the registers, and to the buffers
within the program. The program is then stepped, which runs an
in-process function to check that it now sees those register values. If
that function fails, we have a bug. If it does not, LLDB then checks for
the same values.
This process repeats for several registers. Hence the repeated calls to
check_register_values in the test program.
In this way we make sure that LLDB sends the correct values to ptrace by
validating them in process. Also that LLDB does not write other
registers in the process of writing one register. Which happened to me
several times during development.
The buffer writes are done with memory writes not expression evaluation
becuase at this stage we cannot trust that expressions work (the
expression tests will later prove that they do).
The second type of tests are expression state restoration tests. For
each combination of states we check that we can restore to a given state
if an expression takes us into the other state. This includes between
the same state, and adds an extra vector length to check expanding and
shrinking SVE buffers. This produces roughly 64 tests.
I have written them all as one test case in a loop because these take a
long time (~20 minutes on an FVP) and you almost always want it to fail
fast. When tracing is enabled you'll see the current states logged.
It's possible that we could skip some of these tests as being very
unlikely to ever happen, but in the spirit of
"There are Only Four Billion FloatsāSo Test Them All!" I think it is
simpler to enumerate every possible state change.
I have not added a test for executing an expression incompatible with
the current mode because this leads to SIGILL, which I know we already
handle. At this time LLDB makes no effort to make the expression
compatible with the current mode either.
Commit: 5072c020aae1636f687af797d4082a26a761c721
https://github.com/llvm/llvm-project/commit/5072c020aae1636f687af797d4082a26a761c721
Author: Erick Ochoa Lopez <erick.ochoalopez at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/lib/Dialect/Vector/Transforms/VectorTransferOpTransforms.cpp
M mlir/test/Dialect/Vector/vector-transfer-drop-unit-dims-patterns.mlir
Log Message:
-----------
[mlir][vector] Drop trailing 1-dims from constant_mask (#187383)
Generalize TransferReadDropUnitDimsPattern to also drop unit dimensions
when `vector::ConstantMaskOp` is used.
Previously TransferReadDropUnitDimsPattern would only drop unit
dimensions when `vector::CreateMaskOp` with a statically known operand
was used.
Assisted-by: Cursor
Commit: 9a33125e42925c1e4a9c9f83a2f251b046dd65cd
https://github.com/llvm/llvm-project/commit/9a33125e42925c1e4a9c9f83a2f251b046dd65cd
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/LoongArch/is_fpclass_f32.ll
M llvm/test/CodeGen/LoongArch/is_fpclass_f64.ll
M llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
Log Message:
-----------
[DAG] Add basic ISD::IS_FPCLASS constant/identity folds (#189944)
Attempts to match middle-end implementation in InstructionSimplify/foldIntrinsicIsFPClass
Fixes #189919
Commit: 461a1c51bf0998edc1fd3b9b7197437136c2fb18
https://github.com/llvm/llvm-project/commit/461a1c51bf0998edc1fd3b9b7197437136c2fb18
Author: AidinT <at.aidin at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/tools/mlir-tblgen/CppGenUtilities.cpp
Log Message:
-----------
[mlir][ods] resolve the wrong indent issue (#189277)
The `emitSummaryAndDescComments` is used to generate summary and
description for tablegen generated classes and structs such as Dialects
and Interfaces. The generated summary and description is indented
incorrectly in the output generated file. For example
`NVGPUDialect.h.inc ` looks like the following:
```cpp
namespace mlir::nvgpu {
/// The `NVGPU` dialect provides a bridge between higher-level target-agnostic
/// dialects (GPU and Vector) and the lower-level target-specific dialect
/// (LLVM IR based NVVM dialect) for NVIDIA GPUs. This allow representing PTX
/// specific operations while using MLIR high level dialects such as Memref
/// and Vector for memory and target-specific register operands, respectively.
class NVGPUDialect : public ::mlir::Dialect {
...
};
} // namespace mlir::nvgpu
```
This is because the `emitSummaryAndDescComments` trims the summary and
description from both sides, rendering the re-indentation useless. This
PR resolves this bug.
Commit: 158f10fe24a39208e45d6039dfc6d605967ade2a
https://github.com/llvm/llvm-project/commit/158f10fe24a39208e45d6039dfc6d605967ade2a
Author: Ming Yan <ming.yan at terapines.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/test/Dialect/MemRef/canonicalize.mlir
Log Message:
-----------
[mlir][memref] Fold memref.reinterpret_cast operations with valid offset or size constants. (#189533)
When encountering an invalid offset or size, we only skip the current
invalid value and continue attempting to fold other valid offsets or
sizes.
Commit: b46f8fa622ab8edf00e986eed2350f137b5efc0b
https://github.com/llvm/llvm-project/commit/b46f8fa622ab8edf00e986eed2350f137b5efc0b
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
A clang/test/CodeGen/tbaa-matrix.c
Log Message:
-----------
[Matrix] Add tests checking TBAA emission for matrix types (NFC). (#189953)
PR: https://github.com/llvm/llvm-project/pull/189953
Commit: 15d48c5bbe2189db1b79aca0b4f355d0c7d664b6
https://github.com/llvm/llvm-project/commit/15d48c5bbe2189db1b79aca0b4f355d0c7d664b6
Author: Gergo Stomfai <stomfaig at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/SystemZ/canonicalize-vars.ll
Log Message:
-----------
[X86][DAG] remove LowerFCanonicalize (#188127)
Remove LowerFCanonicalize. Added fallback for cases when the scalar type also has its Custom lowering to avoid regressions on AMDGPU and SystemZ.
Fixes #143862
Commit: d6b8163f3fb5b9fe8262171d9815030ccfc3772a
https://github.com/llvm/llvm-project/commit/d6b8163f3fb5b9fe8262171d9815030ccfc3772a
Author: DaKnig <37626476+DaKnig at users.noreply.github.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/neon-abd.ll
M llvm/test/CodeGen/X86/abds.ll
Log Message:
-----------
Retry "[SDAG] (abs (add nsw a, -b)) -> (abds a, b) (#175801)" (#186659)
A better version of #175801 . see that for more info.
Fixes #185467
The original patch was checking the correctness of the transformation
based on the original Op1 , which was then negated (in the case of
IsAdd). This patch fixes that issue by inverting the sign bit in that
case.
Also pushed a slight nfc there to simplify the code and remove some
duplication.
alive2 proofs:
abds: https://alive2.llvm.org/ce/z/oJQPss
abdu: https://alive2.llvm.org/ce/z/HfPF5q
Note that the regression test is not (wrongly) affected anymore by the
patch (as it did before)
Commit: 5781cc9bf6d4e2b1023162eb7878028e2d21e3d4
https://github.com/llvm/llvm-project/commit/5781cc9bf6d4e2b1023162eb7878028e2d21e3d4
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/IR/Intrinsics.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/MIMGInstructions.td
M llvm/test/TableGen/intrinsic-struct.td
Log Message:
-----------
[LLVM][Intrinsics] Refactor IIT encoding generation (#189790)
Refactor IIT encoding generation. The core change here is that when
generating IIT encodings, we pre-generate all the bits of the IIT
encoding except cases where a type needs to encode its own overload
index, which is patched in later in `TypeInfoGen`. In addition, this
change introduces a class hierarchy for dependent types, so that the
checks in `TypeInfoGen` are more meaningful, and renames/simplifies
several other pieces of code, as listed below.
1. Change the encoding for IIT_ARG's ArgInfo byte to encode the overload
slot index in lower 5 bits and the argument kind in upper 3 bits. This
enabled generating the same packed format for all other dependent types
that need to encode an overload slot index in the IIT encoding. Adjusted
the corresponding C++ code in `IITDescriptor::getArgumentNumber` and
`IIT_Descriptor::getArgumentKind`.
2. Introduce more descriptive classes to handle packing of the overload
index + arg kind into the IIT encoding. `OverloadIndexPlaceholder` is
used to generate a transient value in the type-signature that is patched
in `TypeInfoGen` with that type's overload index. `PackOverloadIndex` is
used to encapsulate the final packing of an overload index and argument
kind in a single byte, and `PatchOverloadIndex` is the class that does
the required patching of a `OverloadIndexPlaceholder` given the type's
overload index.
3. Delete `isAny`, `ArgCode` and `Number` from base `LLVMType` class.
Replace use of `isAny` with `isa<LLVMAnyType>`, `ArgCode` is not used
anymore, and move `Number`, which was used to represent the overload
index for a dependent type to the `LLVMDependentType` class and rename
it to `OverloadIndex`.
4. Introduce `LLVMDependentType` as a base class of all dependent types.
It holds the overload index of the type it depends on in its
`OverloadIndex` field. Also introduce 2 subclasses,
`LLVMFullyDependentType` to represent all fully dependent types (which
encode just the appropriate IIT code and the dependent type's overload
index) and `LLVMPartiallyDependentType` to represent partially dependent
types, that encode the appropriate IIT code and both this type's
overload index and the dependent type's overload index.
5. Change existing dependent type classes to derive from one of these
classes and rename the `num` class argument to `oidx` to better reflect
its meaning.
6. Rename various fields and classes used in `TypeInfoGen` to be more
meaningful. `AssignOverloadIndex` to do overload index assignment,
rename `ACIdxs` to `OverloadIdxs`, `ACTys` to `OverloadTypes` and use
the `DoPatchOverloadIndex` to patch in assigned overload slot indexes.
Commit: ce78c16738f805f8635ce6c575c184b94160fade
https://github.com/llvm/llvm-project/commit/ce78c16738f805f8635ce6c575c184b94160fade
Author: Lewis Crawford <lcrawford at nvidia.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/test/Transforms/SROA/vector-promotion-via-tree-structure-merge.ll
Log Message:
-----------
SROA: Fix tree merge IRBuilder insert point (#189680)
StoreInfos is sorted by slice offset, not program order. Anchoring the
IRBuilder at StoreInfos.back() could emit shufflevectors before SSA
values defined later in the same block (invalid IR).
Insert merged shuffles immediately before TheLoad when the load shares
the store block. When the load is elsewhere, insert before the store
block terminator so the merge runs after every store + any trailing
instructions in that block.
Commit: d95292f67b48666be421afe0a3d919480458a6df
https://github.com/llvm/llvm-project/commit/d95292f67b48666be421afe0a3d919480458a6df
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M lldb/include/lldb/Host/FileAction.h
M lldb/include/lldb/Host/ProcessLaunchInfo.h
A lldb/include/lldb/Host/windows/WindowsFileAction.h
M lldb/source/Host/CMakeLists.txt
M lldb/source/Host/common/ProcessLaunchInfo.cpp
M lldb/source/Host/windows/ProcessLauncherWindows.cpp
A lldb/source/Host/windows/WindowsFileAction.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/tools/lldb-server/lldb-platform.cpp
M lldb/unittests/Host/HostTest.cpp
Log Message:
-----------
[lldb][windows] refactor FileAction (#179274)
Commit: 31edb8fab547eaa76427bf5c62b0c9e58cba3e41
https://github.com/llvm/llvm-project/commit/31edb8fab547eaa76427bf5c62b0c9e58cba3e41
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/test/Transforms/LICM/preheader-safe.ll
M llvm/test/Transforms/LICM/read-only-calls.ll
Log Message:
-----------
[LICM] Generate test checks (NFC) (#189963)
Commit: fd40c606652137706bc336ef80ed1814ab3d3680
https://github.com/llvm/llvm-project/commit/fd40c606652137706bc336ef80ed1814ab3d3680
Author: David Green <david.green at arm.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
M llvm/test/Transforms/VectorCombine/LoongArch/shuffle-identity-miscompile.ll
Log Message:
-----------
[VectorCombine] Fix transitive Uses in foldShuffleToIdentity (#188989)
The Uses in foldShuffleToIdentity is intended to detect where an operand
is used to distinguish between splats, identities and concats of the
same value. When looking through multiple unsimplified shuffles the same
Use could be both a splat and a identity though. This patch changes the
Use to a Value and an original Use, so that even if we are looking
through multiple vectors we recognise the splat vs identity vs concat of
each use correctly.
Fixes #180338
Commit: 1c55313f344ff2189500f87c89cec2a3cf2eb5c9
https://github.com/llvm/llvm-project/commit/1c55313f344ff2189500f87c89cec2a3cf2eb5c9
Author: Tony Allevato <tony.allevato at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Support/CommandLine.cpp
M llvm/unittests/Support/CommandLineTest.cpp
Log Message:
-----------
Treat `''` and `""` in Gnu-tokenized response files as an empty string argument. (#187566)
This matches the behavior of gcc and also fixes an inconsistency with
the way the same arguments would be parsed by the shell. For example,
this command line passed directly on the shell:
`command -option1 '' -option2`
has three arguments: `"-option1"`, `""`, and `"-option2"`. However, if
these are passed in a Gnu-tokenized response file today:
```
-option1
''
-option2
```
The `''` is discarded and the command incorrectly has two arguments:
`"-option1"` and `"-option2"`.
Commit: 86c3abe85e7d323c8b7fbe4b83442ca3794512c9
https://github.com/llvm/llvm-project/commit/86c3abe85e7d323c8b7fbe4b83442ca3794512c9
Author: Pankaj Dwivedi <pankajkumar.divedi at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/ADT/Uniformity.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/UniformityAnalysis.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
Log Message:
-----------
[NFC] Rename InstructionUniformity to ValueUniformity (#189935)
Commit: 9dc8f465a42d7187cfff73e56f525560af4f9349
https://github.com/llvm/llvm-project/commit/9dc8f465a42d7187cfff73e56f525560af4f9349
Author: Steven Perron <stevenperron at google.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
A llvm/test/CodeGen/SPIRV/hlsl-resources/CalculateLevelOfDetail.ll
Log Message:
-----------
[SPIRV] Implement the int_spv_resource_calculate_lod* IntrinsicsSPIRV (#188337)
Implements intrinsics used to get the level-of-detail given a texture,
sampler, and a coordinate. It will be used to implement the
corresponding HLSL methods.
Assisted-by: Gemini
Commit: c6b25b4df3efddcc8ab7b781f299aea2ed682434
https://github.com/llvm/llvm-project/commit/c6b25b4df3efddcc8ab7b781f299aea2ed682434
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M libc/include/llvm-libc-macros/pthread-macros.h
M libc/include/llvm-libc-types/pthread_rwlock_t.h
M libc/src/__support/threads/CMakeLists.txt
M libc/src/__support/threads/linux/CMakeLists.txt
R libc/src/__support/threads/linux/rwlock.h
A libc/src/__support/threads/raw_rwlock.h
A libc/src/__support/threads/unix_rwlock.h
M libc/src/pthread/CMakeLists.txt
M libc/src/pthread/pthread_rwlock_clockrdlock.cpp
M libc/src/pthread/pthread_rwlock_clockwrlock.cpp
M libc/src/pthread/pthread_rwlock_destroy.cpp
M libc/src/pthread/pthread_rwlock_init.cpp
M libc/src/pthread/pthread_rwlock_rdlock.cpp
M libc/src/pthread/pthread_rwlock_timedrdlock.cpp
M libc/src/pthread/pthread_rwlock_timedwrlock.cpp
M libc/src/pthread/pthread_rwlock_tryrdlock.cpp
M libc/src/pthread/pthread_rwlock_trywrlock.cpp
M libc/src/pthread/pthread_rwlock_unlock.cpp
M libc/src/pthread/pthread_rwlock_wrlock.cpp
M libc/test/integration/src/pthread/CMakeLists.txt
M libc/test/integration/src/pthread/pthread_rwlock_test.cpp
M libc/test/src/__support/threads/linux/CMakeLists.txt
A libc/test/src/__support/threads/linux/raw_rwlock_test.cpp
Log Message:
-----------
[libc] separate raw_rwlock and unix_rwlock to make it internally usable (#189773)
Commit: 9b00518419736f698d0a62d0721ee54ceeca4bd7
https://github.com/llvm/llvm-project/commit/9b00518419736f698d0a62d0721ee54ceeca4bd7
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
A llvm/include/llvm/MC/MCAsmStreamer.h
M llvm/lib/MC/MCAsmStreamer.cpp
Log Message:
-----------
[MC] Introduce new base class for MCAsmStreamer (#187083)
The class MCAsmBaseStreamer serves as the common base class for streamers
which emit assembly output. It has the same role as MCObjectStreamer has
for streams which emits object files.
Commit: 5d393aee10810d18e30027e22ace3a856d72c0a2
https://github.com/llvm/llvm-project/commit/5d393aee10810d18e30027e22ace3a856d72c0a2
Author: Victor Chernyakin <chernyakin.victor.j at outlook.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang-tools-extra/docs/clang-tidy/Contributing.rst
M clang-tools-extra/unittests/clang-tidy/CMakeLists.txt
R clang-tools-extra/unittests/clang-tidy/ObjCModuleTest.cpp
M llvm/utils/gn/secondary/clang-tools-extra/unittests/clang-tidy/BUILD.gn
Log Message:
-----------
[clang-tidy][NFC] Remove the `ObjCModuleTest.cpp` unit test (#185832)
These unit tests only duplicate the tests in
`clang-tools-extra/test/clang-tidy/checkers/objc/forbidden-subclassing.m`.
Commit: ed44820f722aae43f1f00bb3e201300966716973
https://github.com/llvm/llvm-project/commit/ed44820f722aae43f1f00bb3e201300966716973
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M flang/test/Lower/Intrinsics/same_type_as.f90
M flang/test/Lower/Intrinsics/scan.f90
M flang/test/Lower/Intrinsics/secnds.f90
M flang/test/Lower/Intrinsics/selected_int_kind.f90
M flang/test/Lower/Intrinsics/selected_real_kind.f90
Log Message:
-----------
[flang][NFC] Converted five tests from old lowering to new lowering (part 40) (#189791)
Tests converted from test/Lower/Intrinsics: same_type_as.f9, scan.f90,
scan.f90, selected_int_kind.f90, selected_real_kind.f90
Commit: 0b61cd39e45ad7e0476740a5ecc455e7461488a4
https://github.com/llvm/llvm-project/commit/0b61cd39e45ad7e0476740a5ecc455e7461488a4
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-factors.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/load-cast-context.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub-epilogue-vec.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-inloop-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-strict-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vscale-fixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/VPlan/dissolve-replicate-regions.ll
M llvm/test/Transforms/LoopVectorize/X86/transform-narrow-interleave-to-widen-memory-epilogue-vec.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
Log Message:
-----------
[LV] Add epilogue minimum iteration check in VPlan as well. (#189372)
Update LV to also use the VPlan-based addMinimumIterationCheck for the
iteration count check for the epilogue.
As the VPlan-based addMinimumIterationCheck uses VPExpandSCEV, those
need to be placed in the entry block for now, moving vscale * VF * IC to
the entry for scalable vectors.
The new logic also fails to simplify some checks involving PtrToInt,
because they were only simplified when going through generated IR, then
folding some PtrToInt in IR, then constructing SCEVs again. But those
should be cleaned up by later combines, and there is not really much we
can do other than trying to go through IR.
PR: https://github.com/llvm/llvm-project/pull/189372
Commit: c7c9b25e8b4efd338aadaa3c2ad744faa6422964
https://github.com/llvm/llvm-project/commit/c7c9b25e8b4efd338aadaa3c2ad744faa6422964
Author: argmaxin <srcydeveloper at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/lib/ExtractAPI/ExtractAPIConsumer.cpp
Log Message:
-----------
Update ExtractAPIConsumer.cpp (#88285)
Fix small spelling mistake.
Co-authored-by: Srcy Dev <88575889+SrcyDev at users.noreply.github.com>
Commit: 54914a4287ca73bb95e42a6cdf19f5d786eb256f
https://github.com/llvm/llvm-project/commit/54914a4287ca73bb95e42a6cdf19f5d786eb256f
Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/include/llvm/CodeGen/Rematerializer.h
M llvm/lib/CodeGen/Rematerializer.cpp
M llvm/unittests/CodeGen/RematerializerTest.cpp
Log Message:
-----------
[CodeGen] Allow rematerializer to rematerialize at the end of a block (#184339)
This makes the rematerializer able to rematerialize MIs at the end of a
basic block. We achieve this by tracking the parent basic block of every
region inside the rematerializer and adding an explicit target region to
some of the class's methods. The latter removes the requirement that we
track the MI of every region (`Rematerializer::MIRegion`) after the
analysis phase; the class member is therefore deleted.
This new ability will be used shortly to improve the design of the
rollback mechanism.
Commit: c245d764b8bd70ff78044f56b2dea619b0d428dc
https://github.com/llvm/llvm-project/commit/c245d764b8bd70ff78044f56b2dea619b0d428dc
Author: LU-JOHN <John.Lu at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/CodeGen/ProcessImplicitDefs.cpp
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/call-constexpr.ll
M llvm/test/CodeGen/AMDGPU/call-skip.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
A llvm/test/CodeGen/AMDGPU/multi-use-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/phi-av-pressure.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
A llvm/test/CodeGen/AMDGPU/subreg-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll
M llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
M llvm/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll
M llvm/test/CodeGen/X86/issue76416.ll
M llvm/test/CodeGen/X86/machine-trace-metrics-crash.ll
A llvm/test/CodeGen/X86/multi-use-implicit-def.mir
M llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
M llvm/test/CodeGen/X86/regalloc-advanced-split-cost.ll
M llvm/test/CodeGen/X86/statepoint-two-results.ll
M llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll
M llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll
Log Message:
-----------
[CodeGen] Do not remove IMPLICIT_DEF unless all uses have undef flag added (#188133)
Do not remove IMPLICIT_DEF of a physreg unless all uses have an undef
flag added. Previously, only the first use instruction had undef flags
added. This will cause a failure in machine instruction verification.
Multi-instruction uses tested in AMDGPU/multi-use-implicit-def.mir and
X86/multi-use-implicit-def.mir.
---------
Signed-off-by: John Lu <John.Lu at amd.com>
Commit: 234b8469e92aa3bfcc08e5b7abd6fcbb11a258a6
https://github.com/llvm/llvm-project/commit/234b8469e92aa3bfcc08e5b7abd6fcbb11a258a6
Author: Sairudra More <sairudra60 at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M flang/lib/Lower/ConvertCall.cpp
A flang/test/Lower/HLFIR/elemental-character-min-max.f90
Log Message:
-----------
[Flang] Compute elemental character MIN/MAX result length in HLFIR (#189464)
This patch fixes lowering of elemental character MIN/MAX in HLFIR.
Previously, these cases could hit a lowering-time TODO
`ElementalIntrinsicCallBuilder::computeDynamicCharacterResultLength` and
abort. This change computes the character result length as the maximum
length of the present actual arguments, allowing valid elemental
character MIN/MAX calls to lower successfully.
Added regression coverage for elemental character MIN/MAX, including
differing-length arguments.
Co-authored-by: Sairudra More <moresair at pe31.hpc.amslabs.hpecorp.net>
Commit: 697ff31fc71fcc895edb077e6fc341761edc0acf
https://github.com/llvm/llvm-project/commit/697ff31fc71fcc895edb077e6fc341761edc0acf
Author: Lei Huang <lei at ca.ibm.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCInstrAltivec.td
M llvm/lib/Target/PowerPC/PPCInstrFuture.td
M llvm/test/CodeGen/PowerPC/vector-rotates.ll
Log Message:
-----------
[PowerPC] Enhance vec_rl() to generate xvrlw (#189023)
Enhance existing builtin vec_rl() to generate the new xvrlw, VSX version
of vrlw, for cpu=future.
Commit: 6f0e961cc2d541e96b1a98c3f196855b0eab2856
https://github.com/llvm/llvm-project/commit/6f0e961cc2d541e96b1a98c3f196855b0eab2856
Author: zGoldthorpe <Zach.Goldthorpe at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
Log Message:
-----------
[WebAssembly] Correct operands for NaN/Zero checks in min/max (#189712)
The `pmin` and `pmax` pattern fragments match `vselect`s, meaning that
the generated operands for `relaxed_min` and `relaxed_max` correspond to
operands 1 and 2 of the `vselect` (rather than operands 0 and 1).
Commit: 046e23fa4adaf4cdee23f4f3416d7d57009f19d5
https://github.com/llvm/llvm-project/commit/046e23fa4adaf4cdee23f4f3416d7d57009f19d5
Author: Roy Shi <royitaqi at users.noreply.github.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/DebugInfo/GSYM/FileWriter.cpp
M llvm/lib/Support/DataExtractor.cpp
Log Message:
-----------
[llvm lib] Fix endian bug in #189098 (#189778)
The bug was added in #189098. Both functions that I added/changed
assumed little-endian host memory layout when reading/writing
non-power-of-two byte sizes (3, 5, 6, 7). On big-endian hosts (SPARC,
s390x), memcpy copies bytes into the MSB end of a uint64_t, leaving the
value in the wrong bit position. Fix by offsetting the memcpy/write
pointer to always target the LSB bytes.
Commit: 364b19322db209f6a465934e7483a6e1dde14043
https://github.com/llvm/llvm-project/commit/364b19322db209f6a465934e7483a6e1dde14043
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.h
Log Message:
-----------
[RISCV] Add assertions to VSETVLIInfo::hasSEWLMULRatioOnly(). NFC (#189799)
Ensure that we can only call this on valid and not unknown.
Commit: 16255e457c9d5d418bd67543c97204448e195597
https://github.com/llvm/llvm-project/commit/16255e457c9d5d418bd67543c97204448e195597
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rv32p.ll
M llvm/test/CodeGen/RISCV/rv64p.ll
Log Message:
-----------
[RISCV] Add RISCVISD::USATI/SATI to computeKnownBitsForTargetNode/ComputeNumSignBitsForTargetNode. (#189702)
Commit: 9506f20b4dccc6334cc36e04c93033d575cfee52
https://github.com/llvm/llvm-project/commit/9506f20b4dccc6334cc36e04c93033d575cfee52
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M flang/include/flang/Optimizer/OpenACC/Support/FIROpenACCUtils.h
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/Analysis/CMakeLists.txt
A flang/test/Analysis/AliasAnalysis/alias-analysis-acc.mlir
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtils.h
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtils.cpp
Log Message:
-----------
[flang][acc] Add AA implementation for acc operations (#189772)
This PR extends flang's alias analysis so it can reason about values
that originate from OpenACC data and privatization operations, including
values passed through block arguments.
Commit: 8a1d6c6f5e421bcade951ce9df4d9d300075cab7
https://github.com/llvm/llvm-project/commit/8a1d6c6f5e421bcade951ce9df4d9d300075cab7
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/test/Driver/linux-ld.c
Log Message:
-----------
clang: driver: update android packed relocation logic (#189758)
Hoist this up from the build system so that users of Android's NDK can
benefit from these various packed relocation encodings depending on
which API level they are targeting.
Link: https://github.com/android/ndk/issues/909
Fixes: https://github.com/android/ndk/issues/2193
Link: https://github.com/android/ndk/issues/2188#issuecomment-3366591142
Link:
https://android.googlesource.com/platform/build/soong/+/d046c2afef086a35d24222b09f4d2c4914e8a2a5/cc/linker.go#548
Commit: b528f6746d4dafdc5975041752b14c0c1714afbc
https://github.com/llvm/llvm-project/commit/b528f6746d4dafdc5975041752b14c0c1714afbc
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M offload/test/CMakeLists.txt
Log Message:
-----------
[Offload] Run liboffload unit tests as a part of check-offload (#189731)
Summary:
These are currently only run with check-offload-unit. Make them a part
of the other tests by putting a dependency on it. We did something like
this previously but it was reverted because the tests failed if there
were no GPUs (like in systems that only checked the CPU case) but I
think that has been fixed.
Commit: 5d9eb0c76aec65c159fb104a241545680483212d
https://github.com/llvm/llvm-project/commit/5d9eb0c76aec65c159fb104a241545680483212d
Author: Mirko BrkuŔanin <Mirko.Brkusanin at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M clang/include/clang/Basic/OffloadArch.h
M clang/lib/Basic/OffloadArch.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11.cl
M clang/test/Driver/amdgpu-macros.cl
M clang/test/Driver/amdgpu-mcpu.cl
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
M clang/test/Misc/target-invalid-cpu-note/nvptx.c
M llvm/docs/AMDGPUUsage.rst
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.def
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
M llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
M llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
Log Message:
-----------
[AMDGPU] Define new targets gfx1171 and gfx1172 (#187735)
Commit: 27c85964006ec45bd8215ec3271c79fbda435735
https://github.com/llvm/llvm-project/commit/27c85964006ec45bd8215ec3271c79fbda435735
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/MC/MCWin64EH.cpp
Log Message:
-----------
[win][x64] Unwind v2: When making headroom leave space for the header (#188368)
When the `ensureHeadroom` call was added during unwind v2 info emission,
it didn't take into account that there is a header of 2-bytes before all
the fixups, so not enough space was actually reserved.
Commit: 1e06cd634e849054d1fe11c1493870b2a7ddf1c9
https://github.com/llvm/llvm-project/commit/1e06cd634e849054d1fe11c1493870b2a7ddf1c9
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC] Fix uninitialized ReductionRoot in getTreeCost
ReductionRoot was initialized to nullptr instead of the RdxRoot
parameter. This caused two ScaleCost calls (for MinBWs cast cost and
ReductionBitWidth resize cost) to pass nullptr as the user instruction,
and suppressed the "Reduction Cost" line in debug output. In practice
the scale factor is the same because the tree root's main op and the
reduction root share the same basic block, so this is NFC.
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/189994
Commit: 015f864215e91d05199fc3c61ef0ee804975d57e
https://github.com/llvm/llvm-project/commit/015f864215e91d05199fc3c61ef0ee804975d57e
Author: Dave Lee <davelee.com at gmail.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
Log Message:
-----------
[lldb] Const some ASTContext pointers in TypeSystemClang (NFC) (#189975)
Commit: f918af7a702f32e35b2fb505de24801d06266ed4
https://github.com/llvm/llvm-project/commit/f918af7a702f32e35b2fb505de24801d06266ed4
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M flang/lib/Semantics/check-omp-atomic.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/openmp-utils.cpp
Log Message:
-----------
[flang][OpenMP] Remove qualification from evaluate::SymbolVector, NFC (#189984)
`SymbolVector` is defined in flang/Semantics/symbol.h, so there is no
need to use a namespace-qualified name for it in lib/Semantics.
Commit: 82e84940701b3e7bba9069e99f8247e7434973bc
https://github.com/llvm/llvm-project/commit/82e84940701b3e7bba9069e99f8247e7434973bc
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/VPlan/dissolve-replicate-regions.ll
Log Message:
-----------
[VPlan] Avoid unnecessary BTC SymbolicValue creation (NFC) (#189929)
Don't unnecessarily create a backedge-taken-count SymbolicValue. This
allows us to simplify some code.
Commit: 5c36ef884321e293714da6e06239345ba2805d3c
https://github.com/llvm/llvm-project/commit/5c36ef884321e293714da6e06239345ba2805d3c
Author: yebinchon <86588366+yebinchon at users.noreply.github.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp
A flang/test/HLFIR/bufferize-associate-block-ordering.fir
Log Message:
-----------
[flang] fix a dangling else in allOtherUsesAreSafeForAssociate (#189748)
Fix a dangling if condition in allOtherUsesAreSafeForAssociate that
caused isBeforeInBlock to be called even when instructions were known to
not be in the same block, triggering an assertion. The condition was
changed to else if and added brackets.
---------
Co-authored-by: Yebin Chon <ychon at nvidia.com>
Commit: 44979bedf0b65db49c7ea67f5d40b0d4c44b06ea
https://github.com/llvm/llvm-project/commit/44979bedf0b65db49c7ea67f5d40b0d4c44b06ea
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
Log Message:
-----------
[VPlan] Strip dead code in isUniformAcrossVFsAndUFs (NFC) (#189687)
Checking a VPInstruction for scalar-cast is equivalent to checking
opcode against Instruction::isCast via preservesUniformity.
Commit: 91adaeceb162357a33e2ea6155cb13a4198a981a
https://github.com/llvm/llvm-project/commit/91adaeceb162357a33e2ea6155cb13a4198a981a
Author: Jan Leyonberg <jan_sjodin at yahoo.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
A clang/include/clang/CIR/Dialect/OpenMP/RegisterOpenMPExtensions.h
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/Dialect/CMakeLists.txt
A clang/lib/CIR/Dialect/OpenMP/CMakeLists.txt
A clang/lib/CIR/Dialect/OpenMP/RegisterOpenMPExtensions.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/CMakeLists.txt
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
A clang/test/CIR/Transforms/omp-mark-declare-target.cir
M clang/tools/cir-opt/CMakeLists.txt
M clang/tools/cir-opt/cir-opt.cpp
M clang/tools/cir-translate/CMakeLists.txt
M clang/tools/cir-translate/cir-translate.cpp
M mlir/lib/Dialect/OpenMP/Transforms/CMakeLists.txt
M mlir/lib/Dialect/OpenMP/Transforms/MarkDeclareTarget.cpp
Log Message:
-----------
[CIR][MLIR][OpenMP] Enable the MarkDeclareTarget pass for ClangIR (#189420)
This patch enables the MarkDeclareTarget for CIR by adding the pass to
the lowerings and attaching the declare target interface to the
cir::FuncOp. The MarkDeclareTarget is also generalized to work on the
FunctionOpInterface instead of func::Op since it needs to be able to
handle cir::FuncOp as well.
Co-authored-by: Claude Opus 4.6 <noreply at anthropic.com>
Commit: 8c9a181e72df0b936f1d9a5ca28fda012697b2d1
https://github.com/llvm/llvm-project/commit/8c9a181e72df0b936f1d9a5ca28fda012697b2d1
Author: Ehsan Amiri <ehsan.amiri at huawei.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M .github/new-prs-labeler.yml
M clang-tools-extra/clang-tidy/readability/ImplicitBoolConversionCheck.cpp
M clang-tools-extra/clang-tidy/readability/ImplicitBoolConversionCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/Contributing.rst
M clang-tools-extra/docs/clang-tidy/checks/readability/implicit-bool-conversion.rst
A clang-tools-extra/test/clang-tidy/checkers/readability/implicit-bool-conversion-allow-logical-operators.c
M clang-tools-extra/unittests/clang-tidy/CMakeLists.txt
R clang-tools-extra/unittests/clang-tidy/ObjCModuleTest.cpp
M clang/docs/ClangIRCleanupAndEHDesign.md
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/AMDGPUTypes.def
M clang/include/clang/Basic/Builtins.def
M clang/include/clang/Basic/BuiltinsAMDGPU.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/OffloadArch.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRCUDAAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
A clang/include/clang/CIR/Dialect/OpenMP/RegisterOpenMPExtensions.h
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Driver/SyclInstallationDetector.h
M clang/include/clang/Driver/ToolChain.h
A clang/include/clang/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphSummary.h
M clang/include/clang/ScalableStaticAnalysisFramework/SSAFBuiltinForceLinker.h
M clang/include/clang/Sema/SemaAMDGPU.h
M clang/include/clang/Serialization/ASTBitCodes.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/MicrosoftMangle.cpp
M clang/lib/AST/Type.cpp
M clang/lib/Basic/OffloadArch.cpp
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Targets/SPIR.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenCleanup.cpp
M clang/lib/CIR/CodeGen/CIRGenCleanup.h
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenStmt.cpp
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/CodeGen/CIRGenerator.cpp
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/Dialect/CMakeLists.txt
M clang/lib/CIR/Dialect/IR/CIRAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
A clang/lib/CIR/Dialect/OpenMP/CMakeLists.txt
A clang/lib/CIR/Dialect/OpenMP/RegisterOpenMPExtensions.cpp
M clang/lib/CIR/Dialect/Transforms/CMakeLists.txt
M clang/lib/CIR/Dialect/Transforms/CXXABILowering.cpp
M clang/lib/CIR/Dialect/Transforms/EHABILowering.cpp
M clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/CMakeLists.txt
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGException.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/lib/CodeGen/CodeGenTypes.cpp
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/Driver/CMakeLists.txt
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Fuchsia.cpp
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/lib/Driver/ToolChains/SYCL.cpp
M clang/lib/ExtractAPI/ExtractAPIConsumer.cpp
M clang/lib/FrontendTool/CMakeLists.txt
M clang/lib/Lex/TokenLexer.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/ScalableStaticAnalysisFramework/Analyses/CMakeLists.txt
A clang/lib/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphExtractor.cpp
M clang/lib/Sema/JumpDiagnostics.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaAMDGPU.cpp
M clang/lib/Sema/SemaCast.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/test/AST/ByteCode/codegen-constexpr-unknown.cpp
M clang/test/AST/ByteCode/cxx26.cpp
M clang/test/AST/ByteCode/records.cpp
M clang/test/Analysis/bstring.cpp
M clang/test/CIR/CodeGen/atomic-scoped.c
A clang/test/CIR/CodeGen/cleanup-throwing-dtor.cpp
A clang/test/CIR/CodeGen/ctor-alias-prev-decl.cpp
A clang/test/CIR/CodeGen/delegating-ctor-exceptions.cpp
A clang/test/CIR/CodeGen/dtor-alias-prev-decl.cpp
A clang/test/CIR/CodeGen/new-delete-deactivation.cpp
M clang/test/CIR/CodeGen/nonzeroinit-struct.cpp
A clang/test/CIR/CodeGen/return-in-if-with-cleanups.cpp
M clang/test/CIR/CodeGen/throws.cpp
M clang/test/CIR/CodeGen/try-catch.cpp
A clang/test/CIR/CodeGenOpenMP/omp-module-attrs.c
A clang/test/CIR/IR/string-trailing-zeros.cir
A clang/test/CIR/Transforms/cxx-abi-lowering-attrs.cir
M clang/test/CIR/Transforms/eh-abi-lowering-itanium.cir
M clang/test/CIR/Transforms/flatten-cleanup-scope-nyi.cir
A clang/test/CIR/Transforms/flatten-throwing-in-cleanup.cir
A clang/test/CIR/Transforms/omp-mark-declare-target.cir
A clang/test/CodeGen/amdgpu-builtin-is-invocable.c
A clang/test/CodeGen/amdgpu-builtin-processor-is.c
A clang/test/CodeGen/amdgpu-feature-builtins-invalid-use.cpp
A clang/test/CodeGen/async-exceptions.c
A clang/test/CodeGen/tbaa-matrix.c
A clang/test/CodeGen/ubsan-aggregate-null-align.c
M clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu
M clang/test/CodeGenCUDA/fp-contract.cu
M clang/test/CodeGenCXX/destructor-dead-on-return.cpp
M clang/test/CodeGenCXX/microsoft-vector-deleting-dtors.cpp
M clang/test/CodeGenCXX/microsoft-vector-deleting-dtors2.cpp
M clang/test/CodeGenCXX/ms-vdtors-devirtualization.cpp
M clang/test/CodeGenHIP/spirv-amdgcn-dpp-const-fold.hip
M clang/test/CodeGenObjC/constant-string-class-1.m
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx10.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-wmma-w32.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-vi.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
A clang/test/Driver/Inputs/SYCL/libLLVMSYCL.ll
R clang/test/Driver/Inputs/SYCL/libsycl.ll
M clang/test/Driver/amdgpu-macros.cl
M clang/test/Driver/amdgpu-mcpu.cl
M clang/test/Driver/link-device-code.test
M clang/test/Driver/linux-ld.c
M clang/test/Driver/sycl-offload-jit.cpp
A clang/test/FixIt/fixit-defaulted-comparison.cpp
M clang/test/Lexer/gnu-flags.c
A clang/test/Lexer/gnu-zero-variadic-macro-argument-fixit.c
M clang/test/Misc/target-invalid-cpu-note/amdgcn.c
M clang/test/Misc/target-invalid-cpu-note/nvptx.c
A clang/test/Modules/pr189415.cppm
M clang/test/OpenMP/for_reduction_codegen_UDR.cpp
A clang/test/Parser/decltype-gh188014.cpp
M clang/test/Preprocessor/macro_fn.c
A clang/test/SemaHIP/amdgpu-feature-builtins-cant-jump.hip
A clang/test/SemaHIP/amdgpu-feature-builtins-return-type-deduction.hip
A clang/test/SemaHIP/amdgpu-feature-predicate.hip
A clang/test/SemaHIP/amdgpu-feature-predicates-guard-use.hip
A clang/test/SemaHIP/amdgpu-is-invocable.hip
A clang/test/SemaHIP/amdgpu-processor-is.hip
M clang/test/SemaHLSL/Texture2D-mips-errors.hlsl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-wmma-w32-param.cl
A clang/test/SemaTemplate/GH188759.cpp
M clang/test/utils/update_cc_test_checks/Inputs/explicit-template-instantiation.cpp.expected
M clang/tools/cir-opt/CMakeLists.txt
M clang/tools/cir-opt/cir-opt.cpp
M clang/tools/cir-translate/CMakeLists.txt
M clang/tools/cir-translate/cir-translate.cpp
M clang/tools/clang-ssaf-format/CMakeLists.txt
M clang/tools/clang-ssaf-linker/CMakeLists.txt
A clang/unittests/ScalableStaticAnalysisFramework/Analyses/CallGraph/CallGraphExtractorTest.cpp
M clang/unittests/ScalableStaticAnalysisFramework/CMakeLists.txt
M clang/unittests/ScalableStaticAnalysisFramework/Registries/SummaryExtractorRegistryTest.cpp
M clang/utils/TableGen/CIRLoweringEmitter.cpp
M clang/utils/TableGen/ClangBuiltinsEmitter.cpp
M compiler-rt/cmake/Modules/CheckAssemblerFlag.cmake
M compiler-rt/lib/asan/asan_allocator.cpp
M compiler-rt/lib/asan/asan_errors.cpp
M compiler-rt/lib/asan/asan_errors.h
M compiler-rt/lib/asan/asan_flags.inc
M compiler-rt/lib/asan/asan_report.cpp
M compiler-rt/lib/asan/asan_report.h
M compiler-rt/lib/builtins/CMakeLists.txt
A compiler-rt/lib/builtins/arm/adddf3.S
M compiler-rt/lib/builtins/int_math.h
M compiler-rt/lib/builtins/muldc3.c
M compiler-rt/test/CMakeLists.txt
A compiler-rt/test/asan/TestCases/Linux/free_aligned_sized_mismatch.cpp
A compiler-rt/test/asan/TestCases/Linux/free_sized_mismatch.cpp
A compiler-rt/test/builtins/Unit/adddf3new_test.c
A compiler-rt/test/builtins/Unit/subdf3new_test.c
M compiler-rt/test/sanitizer_common/TestCases/Linux/soft_rss_limit_mb_test.cpp
M flang/docs/C++style.md
M flang/include/flang/Optimizer/OpenACC/Support/FIROpenACCUtils.h
M flang/lib/Lower/ConvertCall.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/Analysis/CMakeLists.txt
M flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp
M flang/lib/Optimizer/OpenMP/FunctionFiltering.cpp
M flang/lib/Optimizer/OpenMP/LowerWorkdistribute.cpp
M flang/lib/Optimizer/Transforms/FIRToMemRef.cpp
M flang/lib/Semantics/check-omp-atomic.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/mod-file.cpp
M flang/lib/Semantics/mod-file.h
M flang/lib/Semantics/openmp-utils.cpp
M flang/lib/Semantics/resolve-names.cpp
A flang/test/Analysis/AliasAnalysis/alias-analysis-acc.mlir
A flang/test/HLFIR/bufferize-associate-block-ordering.fir
A flang/test/Lower/HLFIR/elemental-character-min-max.f90
M flang/test/Lower/Intrinsics/same_type_as.f90
M flang/test/Lower/Intrinsics/scan.f90
M flang/test/Lower/Intrinsics/secnds.f90
M flang/test/Lower/Intrinsics/selected_int_kind.f90
M flang/test/Lower/Intrinsics/selected_real_kind.f90
R flang/test/Lower/OpenMP/Todo/depend-clause.f90
M flang/test/Lower/OpenMP/composite_simd_linear.f90
A flang/test/Lower/OpenMP/depend-iterator.f90
M flang/test/Lower/OpenMP/distribute-parallel-do-simd.f90
M flang/test/Lower/OpenMP/distribute-simd.f90
M flang/test/Lower/OpenMP/linear_modifier.f90
M flang/test/Lower/OpenMP/loop-pointer-variable.f90
M flang/test/Lower/OpenMP/ordered-simd.f90
M flang/test/Lower/OpenMP/wsloop-simd.f90
A flang/test/Semantics/Inputs/modfile84.f90
A flang/test/Semantics/modfile84.f90
M flang/test/Transforms/FIRToMemRef/array-coor-slice-shift.mlir
M libc/cmake/modules/LLVMLibCCompileOptionRules.cmake
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/dev/undefined_behavior.rst
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/VISIT.h
A libc/hdr/types/posix_tnode.h
A libc/hdr/types/siginfo_t.h
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-macros/pthread-macros.h
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/__action_closure_fn_t.h
A libc/include/llvm-libc-types/__action_fn_t.h
A libc/include/llvm-libc-types/__free_fn_t.h
A libc/include/llvm-libc-types/posix_tnode.h
M libc/include/llvm-libc-types/pthread_rwlock_t.h
M libc/include/search.yaml
M libc/src/__support/CMakeLists.txt
M libc/src/__support/HashTable/CMakeLists.txt
M libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
A libc/src/__support/OSUtil/linux/syscall_wrappers/raise.h
M libc/src/__support/threads/CMakeLists.txt
M libc/src/__support/threads/linux/CMakeLists.txt
R libc/src/__support/threads/linux/rwlock.h
A libc/src/__support/threads/raw_rwlock.h
A libc/src/__support/threads/unix_rwlock.h
M libc/src/__support/wchar/CMakeLists.txt
M libc/src/__support/wchar/character_converter.h
M libc/src/__support/wchar/mbrtowc.cpp
M libc/src/__support/wchar/mbrtowc.h
M libc/src/__support/wchar/mbsnrtowcs.h
M libc/src/__support/wchar/string_converter.h
M libc/src/__support/wchar/wcrtomb.h
M libc/src/__support/wchar/wcsnrtombs.h
M libc/src/__support/weak_avl.h
M libc/src/pthread/CMakeLists.txt
M libc/src/pthread/pthread_rwlock_clockrdlock.cpp
M libc/src/pthread/pthread_rwlock_clockwrlock.cpp
M libc/src/pthread/pthread_rwlock_destroy.cpp
M libc/src/pthread/pthread_rwlock_init.cpp
M libc/src/pthread/pthread_rwlock_rdlock.cpp
M libc/src/pthread/pthread_rwlock_timedrdlock.cpp
M libc/src/pthread/pthread_rwlock_timedwrlock.cpp
M libc/src/pthread/pthread_rwlock_tryrdlock.cpp
M libc/src/pthread/pthread_rwlock_trywrlock.cpp
M libc/src/pthread/pthread_rwlock_unlock.cpp
M libc/src/pthread/pthread_rwlock_wrlock.cpp
M libc/src/search/CMakeLists.txt
A libc/src/search/tdelete.cpp
A libc/src/search/tdelete.h
A libc/src/search/tdestroy.cpp
A libc/src/search/tdestroy.h
A libc/src/search/tfind.cpp
A libc/src/search/tfind.h
A libc/src/search/tsearch.cpp
A libc/src/search/tsearch.h
A libc/src/search/twalk.cpp
A libc/src/search/twalk.h
A libc/src/search/twalk_r.cpp
A libc/src/search/twalk_r.h
M libc/src/setjmp/aarch64/CMakeLists.txt
M libc/src/signal/linux/CMakeLists.txt
M libc/src/signal/linux/raise.cpp
M libc/src/signal/linux/sigaction.cpp
M libc/src/signal/linux/signal_utils.h
M libc/src/stdio/CMakeLists.txt
M libc/src/stdio/printf_core/CMakeLists.txt
M libc/src/stdio/scanf_core/CMakeLists.txt
M libc/test/integration/src/pthread/CMakeLists.txt
M libc/test/integration/src/pthread/pthread_rwlock_test.cpp
M libc/test/src/__support/threads/linux/CMakeLists.txt
A libc/test/src/__support/threads/linux/raw_rwlock_test.cpp
M libc/test/src/__support/weak_avl_test.cpp
M libc/test/src/search/CMakeLists.txt
A libc/test/src/search/tsearch_test.cpp
M libc/test/src/stdio/CMakeLists.txt
M libc/test/src/stdio/scanf_core/CMakeLists.txt
M libc/test/src/stdlib/CMakeLists.txt
M libcxx/docs/ReleaseNotes/23.rst
M libcxx/include/__bit_reference
M libcxx/include/__hash_table
M libcxx/include/ext/hash_map
M libcxx/test/extensions/gnu/hash_map/copy.pass.cpp
R libcxx/test/extensions/gnu/hash_map/non_standard_layout.pass.cpp
R libcxx/test/extensions/gnu/hash_multimap/non_standard_layout.pass.cpp
A libcxx/test/std/containers/sequences/vector.bool/reference/builtin_address_of.pass.cpp
M libcxx/test/std/thread/futures/futures.async/thread_create_failure.pass.cpp
A libcxx/test/std/utilities/template.bitset/bitset.members/reference.builtin_address_of.pass.cpp
M lld/ELF/Arch/AArch64.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/InputSection.h
M lld/ELF/SyntheticSections.cpp
A lld/test/ELF/aarch64-tls-dtprel.s
M lld/test/ELF/merge-piece-oob.s
M lldb/docs/use/aarch64-linux.md
M lldb/examples/python/formatter_bytecode.py
M lldb/include/lldb/Host/FileAction.h
M lldb/include/lldb/Host/ProcessLaunchInfo.h
A lldb/include/lldb/Host/windows/WindowsFileAction.h
M lldb/include/lldb/Target/MemoryRegionInfo.h
M lldb/include/lldb/Target/Platform.h
M lldb/include/lldb/Target/Process.h
M lldb/include/lldb/Target/StackFrame.h
M lldb/include/lldb/Target/Target.h
M lldb/include/lldb/ValueObject/DILEval.h
M lldb/include/lldb/ValueObject/DILParser.h
M lldb/include/lldb/ValueObject/ValueObject.h
M lldb/include/lldb/lldb-private-enumerations.h
M lldb/packages/Python/lldbsuite/test/lldbplatformutil.py
M lldb/packages/Python/lldbsuite/test/lldbutil.py
M lldb/source/API/SBMemoryRegionInfo.cpp
M lldb/source/Commands/CommandObjectFrame.cpp
M lldb/source/Commands/CommandObjectMemory.cpp
M lldb/source/Core/Module.cpp
M lldb/source/Expression/IRMemoryMap.cpp
M lldb/source/Host/CMakeLists.txt
M lldb/source/Host/common/ProcessLaunchInfo.cpp
M lldb/source/Host/windows/ProcessLauncherWindows.cpp
A lldb/source/Host/windows/WindowsFileAction.cpp
M lldb/source/Plugins/Architecture/AArch64/ArchitectureAArch64.cpp
M lldb/source/Plugins/DynamicLoader/POSIX-DYLD/DynamicLoaderPOSIXDYLD.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.h
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwinDevice.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwinDevice.h
M lldb/source/Plugins/Platform/MacOSX/PlatformRemoteDarwinDevice.cpp
M lldb/source/Plugins/Process/FreeBSD/NativeProcessFreeBSD.cpp
M lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
M lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
M lldb/source/Plugins/Process/NetBSD/NativeProcessNetBSD.cpp
M lldb/source/Plugins/Process/Utility/LinuxProcMaps.cpp
M lldb/source/Plugins/Process/Utility/MemoryTagManagerAArch64MTE.cpp
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
M lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
M lldb/source/Plugins/Process/Windows/Common/ProcessDebugger.cpp
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunication.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp
M lldb/source/Plugins/Process/minidump/MinidumpParser.cpp
M lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Target/MemoryRegionInfo.cpp
M lldb/source/Target/Platform.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/StackFrame.cpp
M lldb/source/Target/Target.cpp
M lldb/source/ValueObject/DILEval.cpp
M lldb/source/ValueObject/DILParser.cpp
M lldb/source/ValueObject/ValueObject.cpp
M lldb/test/API/commands/target/create-deps/TestTargetCreateDeps.py
M lldb/test/API/functionalities/breakpoint/break_in_loaded_dylib/TestBreakInLoadedDylib.py
M lldb/test/API/functionalities/executable_first/TestExecutableFirst.py
M lldb/test/API/functionalities/load_after_attach/TestLoadAfterAttach.py
M lldb/test/API/functionalities/load_lazy/TestLoadUsingLazyBind.py
M lldb/test/API/functionalities/load_unload/TestLoadUnload.py
A lldb/test/API/linux/aarch64/sme_only_registers/Makefile
A lldb/test/API/linux/aarch64/sme_only_registers/TestSMEOnlyRegisters.py
A lldb/test/API/linux/aarch64/sme_only_registers/main.c
M lldb/test/API/symbol_ondemand/shared_library/TestSharedLibOnDemand.py
M lldb/test/API/tools/lldb-dap/attach/TestDAP_attach.py
M lldb/test/Shell/ScriptInterpreter/Python/Inputs/FormatterBytecode/RigidArrayLLDBFormatterSwift.txt
M lldb/test/Shell/ScriptInterpreter/Python/python-bytecode.test
M lldb/tools/lldb-dap/Handler/AttachRequestHandler.cpp
M lldb/tools/lldb-server/lldb-platform.cpp
M lldb/unittests/Host/HostTest.cpp
M lldb/unittests/Platform/PlatformDarwinTest.cpp
M lldb/unittests/Platform/PlatformMacOSXTest.cpp
M lldb/unittests/Platform/PlatformTest.cpp
M lldb/unittests/Process/Utility/LinuxProcMapsTest.cpp
M lldb/unittests/Process/Utility/MemoryTagManagerAArch64MTETest.cpp
M lldb/unittests/Process/gdb-remote/GDBRemoteCommunicationClientTest.cpp
M lldb/unittests/Process/minidump/MinidumpParserTest.cpp
M lldb/unittests/Target/MemoryRegionInfoTest.cpp
M llvm/CMakeLists.txt
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/docs/SandboxVectorizer.md
M llvm/include/llvm/ADT/GenericCycleImpl.h
M llvm/include/llvm/ADT/Uniformity.h
M llvm/include/llvm/ADT/bit.h
M llvm/include/llvm/Analysis/DependenceAnalysis.h
M llvm/include/llvm/Analysis/LoopAccessAnalysis.h
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/BinaryFormat/MsgPackDocument.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/Rematerializer.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/DebugInfo/CodeView/LazyRandomTypeCollection.h
M llvm/include/llvm/DebugInfo/PDB/Native/TpiStream.h
M llvm/include/llvm/IR/GlobalObject.h
M llvm/include/llvm/IR/Instruction.h
M llvm/include/llvm/IR/Intrinsics.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/Value.h
A llvm/include/llvm/MC/MCAsmStreamer.h
M llvm/include/llvm/MC/MCAssembler.h
M llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h
M llvm/include/llvm/Support/Alignment.h
M llvm/include/llvm/Support/Parallel.h
M llvm/include/llvm/Target/Target.td
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.def
M llvm/include/llvm/TargetParser/Triple.h
M llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
M llvm/include/llvm/Transforms/Utils/BypassSlowDivision.h
A llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/UniformityAnalysis.cpp
M llvm/lib/BinaryFormat/MsgPackDocument.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/ExpandVectorPredication.cpp
M llvm/lib/CodeGen/InlineAsmPrepare.cpp
M llvm/lib/CodeGen/LowerEmuTLS.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/ProcessImplicitDefs.cpp
M llvm/lib/CodeGen/Rematerializer.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/DebugInfo/CodeView/LazyRandomTypeCollection.cpp
M llvm/lib/DebugInfo/GSYM/FileWriter.cpp
M llvm/lib/DebugInfo/PDB/Native/TpiStream.cpp
M llvm/lib/Frontend/OpenMP/OMPContext.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/Core.cpp
M llvm/lib/IR/Globals.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/Intrinsics.cpp
M llvm/lib/IR/LLVMContextImpl.cpp
M llvm/lib/IR/LLVMContextImpl.h
M llvm/lib/IR/Metadata.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCAssembler.cpp
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/MC/MCWin64EH.cpp
M llvm/lib/MCA/HardwareUnits/ResourceManager.cpp
M llvm/lib/Object/RelocationResolver.cpp
M llvm/lib/Passes/PassBuilderPipelines.cpp
M llvm/lib/Support/APInt.cpp
M llvm/lib/Support/CommandLine.cpp
M llvm/lib/Support/DataExtractor.cpp
M llvm/lib/Support/Parallel.cpp
M llvm/lib/Target/AArch64/AArch64FastISel.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/AArch64/AArch64SystemOperands.td
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp
M llvm/lib/Target/AArch64/AArch64TargetObjectFile.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/GCNProcessors.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/MIMGInstructions.td
M llvm/lib/Target/AMDGPU/R600ISelLowering.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
A llvm/lib/Target/AMDGPU/SISpillUtils.cpp
A llvm/lib/Target/AMDGPU/SISpillUtils.h
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/Mips/MipsInstrInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXDwarfDebug.cpp
M llvm/lib/Target/NVPTX/NVPTXDwarfDebug.h
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/PowerPC/PPCInstrAltivec.td
M llvm/lib/Target/PowerPC/PPCInstrFuture.td
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXAIF.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.cpp
M llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.h
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
M llvm/lib/Target/SPIRV/SPIRVPrepareGlobals.cpp
M llvm/lib/Target/WebAssembly/GISel/WebAssemblyInstructionSelector.cpp
M llvm/lib/Target/WebAssembly/GISel/WebAssemblyLegalizerInfo.cpp
M llvm/lib/Target/WebAssembly/GISel/WebAssemblyRegisterBankInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
M llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/X86CompressEVEX.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/IPO/ExpandVariadics.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Scalar/LoopLoadElimination.cpp
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/BreakCriticalEdges.cpp
M llvm/lib/Transforms/Utils/BypassSlowDivision.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/lib/Transforms/Vectorize/CMakeLists.txt
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
A llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/LoadStoreVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/PassRegistry.def
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/SandboxVectorizerPassBuilder.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/runtimes/CMakeLists.txt
M llvm/test/Analysis/DependenceAnalysis/PR188098.ll
M llvm/test/Analysis/DependenceAnalysis/exact-rdiv-addrec-wrap.ll
A llvm/test/Analysis/DependenceAnalysis/exact-rdiv-delta-overflow.ll
M llvm/test/Analysis/DependenceAnalysis/exact-siv-overflow.ll
M llvm/test/Analysis/DependenceAnalysis/gcd-miv-overflow.ll
M llvm/test/Analysis/LoopAccessAnalysis/invariant-dep-same-ptr.ll
M llvm/test/Analysis/LoopAccessAnalysis/pointer-phis.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
M llvm/test/Bitcode/amdgpu-wmma-drop-ab-mods-upgrade.ll
M llvm/test/CMakeLists.txt
M llvm/test/CodeGen/AArch64/O0-pipeline.ll
M llvm/test/CodeGen/AArch64/O3-pipeline.ll
M llvm/test/CodeGen/AArch64/abds-neg.ll
M llvm/test/CodeGen/AArch64/abdu-neg.ll
M llvm/test/CodeGen/AArch64/dup.ll
M llvm/test/CodeGen/AArch64/emutls.ll
M llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll
M llvm/test/CodeGen/AArch64/intrinsic-cttz-elts.ll
M llvm/test/CodeGen/AArch64/neon-abd.ll
M llvm/test/CodeGen/AArch64/sve-mask-partition.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot8.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/basic-branch.ll
M llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/call-constexpr.ll
M llvm/test/CodeGen/AMDGPU/call-skip.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
M llvm/test/CodeGen/AMDGPU/constant-fold-mi-operands.ll
M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
A llvm/test/CodeGen/AMDGPU/cttz-elts.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll
A llvm/test/CodeGen/AMDGPU/dead-frame-index-dbg-value.ll
M llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
M llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-alloca-issue-155902.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmax.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fmin.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imm.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wmma.imod.gfx1250.w32.ll
M llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll
M llvm/test/CodeGen/AMDGPU/load-global-invariant.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-agent.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-cluster.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-lastuse.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-singlethread.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-system.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-wavefront.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-workgroup.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
A llvm/test/CodeGen/AMDGPU/multi-use-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/phi-av-pressure.ll
M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
M llvm/test/CodeGen/AMDGPU/rem_i128.ll
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2x16.ll
M llvm/test/CodeGen/AMDGPU/select-phi-s16-fp.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir
M llvm/test/CodeGen/AMDGPU/smfmac_alloc_failure_no_agpr_O0.ll
M llvm/test/CodeGen/AMDGPU/sopk-no-literal.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr-update-regscavenger.ll
M llvm/test/CodeGen/AMDGPU/spill-wide-sgpr.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
A llvm/test/CodeGen/AMDGPU/subreg-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/trap-abis.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll
M llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
M llvm/test/CodeGen/AMDGPU/wait-xcnt-atomic-rmw-optimization.ll
M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir
M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/AMDGPU/zext-lid.ll
A llvm/test/CodeGen/ARM/emutls-alignment.ll
M llvm/test/CodeGen/Generic/reloc-none.ll
M llvm/test/CodeGen/LoongArch/is_fpclass_f32.ll
M llvm/test/CodeGen/LoongArch/is_fpclass_f64.ll
A llvm/test/CodeGen/LoongArch/mergestores.ll
M llvm/test/CodeGen/PowerPC/atomics-regression.ll
A llvm/test/CodeGen/PowerPC/cttz-elts.ll
M llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
M llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
M llvm/test/CodeGen/PowerPC/vector-rotates.ll
M llvm/test/CodeGen/RISCV/abds-neg.ll
M llvm/test/CodeGen/RISCV/abdu-neg.ll
M llvm/test/CodeGen/RISCV/branch_zero.ll
A llvm/test/CodeGen/RISCV/combine-is_fpclass.ll
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
M llvm/test/CodeGen/RISCV/rv32p.ll
M llvm/test/CodeGen/RISCV/rv64p.ll
M llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
A llvm/test/CodeGen/RISCV/rvv/cttz-elts-scalarize.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-elts.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-elts.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
M llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
M llvm/test/CodeGen/RISCV/rvv/round-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
M llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
A llvm/test/CodeGen/SPIRV/SpecConstants/amdgcnspirv-feature-predicate-specconstant.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_cooperative_matrix/cooperative_matrix.ll
A llvm/test/CodeGen/SPIRV/function/variadics-lowering-builtin-substr-in-name.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/CalculateLevelOfDetail.ll
M llvm/test/CodeGen/SPIRV/instructions/vector-shuffle.ll
A llvm/test/CodeGen/SPIRV/opencl/nofpclass-fastmath-kernel-pre16.ll
A llvm/test/CodeGen/SPIRV/opencl/nofpclass-fastmath-non-extinst.ll
A llvm/test/CodeGen/SPIRV/opencl/nofpclass-fastmath.ll
A llvm/test/CodeGen/SPIRV/passes/SPIRVEmitIntrinsics-infer-fnptr-todo-type.ll
A llvm/test/CodeGen/SPIRV/passes/SPIRVPrepareGlobals-predicate-id-string.ll
M llvm/test/CodeGen/SPIRV/printf.ll
M llvm/test/CodeGen/SPIRV/spec_const_decoration.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpVectorExtractDynamic.ll
M llvm/test/CodeGen/SystemZ/canonicalize-vars.ll
M llvm/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll
A llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/bitwise.mir
A llvm/test/CodeGen/WebAssembly/GlobalISel/instruction-select/int-arithmetic.mir
A llvm/test/CodeGen/WebAssembly/GlobalISel/legalizer/add.mir
A llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/bitwise.mir
A llvm/test/CodeGen/WebAssembly/GlobalISel/regbankselect/int-arithmetic.mir
A llvm/test/CodeGen/WebAssembly/strided-int-mac.ll
A llvm/test/CodeGen/WebAssembly/swiftasync-coroutine.ll
A llvm/test/CodeGen/WebAssembly/swifttailcc-musttail-no-tailcall.ll
A llvm/test/CodeGen/WebAssembly/swifttailcc-no-tailcall.ll
A llvm/test/CodeGen/WebAssembly/swifttailcc.ll
M llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir
M llvm/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir
M llvm/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir
M llvm/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir
M llvm/test/CodeGen/X86/abds.ll
M llvm/test/CodeGen/X86/addcarry.ll
A llvm/test/CodeGen/X86/apx/compress-evex-negative-nf.mir
M llvm/test/CodeGen/X86/apx/reloc-opt.ll
M llvm/test/CodeGen/X86/int-to-fp-demanded.ll
M llvm/test/CodeGen/X86/intrinsic-cttz-elts.ll
M llvm/test/CodeGen/X86/issue76416.ll
A llvm/test/CodeGen/X86/known-fpclass.ll
M llvm/test/CodeGen/X86/machine-trace-metrics-crash.ll
A llvm/test/CodeGen/X86/multi-use-implicit-def.mir
M llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
M llvm/test/CodeGen/X86/regalloc-advanced-split-cost.ll
M llvm/test/CodeGen/X86/statepoint-two-results.ll
M llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll
M llvm/test/CodeGen/X86/subcarry.ll
M llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll
M llvm/test/DebugInfo/AArch64/tls-at-location.ll
M llvm/test/DebugInfo/NVPTX/debug-addr-space.ll
M llvm/test/DebugInfo/NVPTX/debug-name-table.ll
M llvm/test/Instrumentation/MemorySanitizer/X86/avx512vl-intrinsics.ll
M llvm/test/MC/AArch64/armv8.9a-prfm-slc.s
M llvm/test/MC/AArch64/armv9.6a-pcdphint.s
M llvm/test/MC/AArch64/armv9a-tlbip.s
M llvm/test/MC/AArch64/basic-a64-instructions.s
M llvm/test/MC/Disassembler/AArch64/armv8.9a-prfm-slc.txt
M llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
M llvm/test/MC/ELF/relax-branch-align.s
R llvm/test/MC/X86/align-branch-convergence.s
M llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
M llvm/test/Other/new-pm-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-pgo-defaults.ll
M llvm/test/Other/new-pm-thinlto-prelink-samplepgo-defaults.ll
M llvm/test/TableGen/intrinsic-arginfo-error.td
A llvm/test/TableGen/intrinsic-overload-dependent-type-validation.td
M llvm/test/TableGen/intrinsic-struct.td
M llvm/test/TableGen/x86-instr-mapping.inc
M llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debug-info-inseltpoison.ll
M llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debug-info.ll
A llvm/test/Transforms/InstCombine/printf-puts-not-emittable.ll
M llvm/test/Transforms/InstSimplify/constant-fold-fp-denormal.ll
M llvm/test/Transforms/LICM/preheader-safe.ll
M llvm/test/Transforms/LICM/read-only-calls.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-vectors-complex.ll
A llvm/test/Transforms/LoopUnroll/RISCV/runtime-unroll-max-trip-count.ll
M llvm/test/Transforms/LoopUnroll/debug.ll
M llvm/test/Transforms/LoopUnroll/runtime-small-upperbound.ll
M llvm/test/Transforms/LoopVectorize/12-12-11-if-conv.ll
M llvm/test/Transforms/LoopVectorize/2012-10-20-infloop.ll
M llvm/test/Transforms/LoopVectorize/2012-10-22-isconsec.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-factors.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/load-cast-context.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub-epilogue-vec.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-inloop-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-strict-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vscale-fixed.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/ARM/arm-unroll.ll
M llvm/test/Transforms/LoopVectorize/ARM/gcc-examples.ll
M llvm/test/Transforms/LoopVectorize/ARM/width-detect.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/reg-usage.ll
M llvm/test/Transforms/LoopVectorize/VPlan/dissolve-replicate-regions.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-dot-printing.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-stress-test-no-explict-vf.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i16.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i32.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i64.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i8.ll
M llvm/test/Transforms/LoopVectorize/X86/avx1.ll
M llvm/test/Transforms/LoopVectorize/X86/conversion-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/X86/gather_scatter.ll
M llvm/test/Transforms/LoopVectorize/X86/gcc-examples.ll
M llvm/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll
M llvm/test/Transforms/LoopVectorize/X86/int128_no_gather.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave_short_tc.ll
M llvm/test/Transforms/LoopVectorize/X86/min-trip-count-switch.ll
M llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
M llvm/test/Transforms/LoopVectorize/X86/parallel-loops-after-reg2mem.ll
M llvm/test/Transforms/LoopVectorize/X86/parallel-loops.ll
M llvm/test/Transforms/LoopVectorize/X86/tail_folding_and_assume_safety.ll
M llvm/test/Transforms/LoopVectorize/X86/transform-narrow-interleave-to-widen-memory-epilogue-vec.ll
M llvm/test/Transforms/LoopVectorize/X86/unroll-pm.ll
M llvm/test/Transforms/LoopVectorize/X86/unroll-small-loops.ll
M llvm/test/Transforms/LoopVectorize/X86/unroll_selection.ll
M llvm/test/Transforms/LoopVectorize/X86/veclib-calls.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-profitable.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-store-accesses-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/align.ll
M llvm/test/Transforms/LoopVectorize/bzip_reverse_loops.ll
M llvm/test/Transforms/LoopVectorize/calloc.ll
M llvm/test/Transforms/LoopVectorize/cpp-new-array.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
M llvm/test/Transforms/LoopVectorize/float-reduction.ll
M llvm/test/Transforms/LoopVectorize/gcc-examples.ll
M llvm/test/Transforms/LoopVectorize/i8-induction.ll
M llvm/test/Transforms/LoopVectorize/if-conv-crash.ll
M llvm/test/Transforms/LoopVectorize/if-conversion-reduction.ll
M llvm/test/Transforms/LoopVectorize/if-conversion.ll
M llvm/test/Transforms/LoopVectorize/increment.ll
M llvm/test/Transforms/LoopVectorize/loop-legality-checks-remarks.ll
M llvm/test/Transforms/LoopVectorize/memdep.ll
M llvm/test/Transforms/LoopVectorize/metadata-unroll.ll
M llvm/test/Transforms/LoopVectorize/metadata-width.ll
M llvm/test/Transforms/LoopVectorize/multiple-address-spaces.ll
M llvm/test/Transforms/LoopVectorize/no_int_induction.ll
M llvm/test/Transforms/LoopVectorize/no_outside_user.ll
A llvm/test/Transforms/LoopVectorize/noalias-scope-decl-outer-loop.ll
M llvm/test/Transforms/LoopVectorize/non-const-n.ll
A llvm/test/Transforms/LoopVectorize/non-widenable-intrinsics-outer-loop.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_test1.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_test2.ll
M llvm/test/Transforms/LoopVectorize/pr30654-phiscev-sext-trunc.ll
M llvm/test/Transforms/LoopVectorize/pr32859.ll
M llvm/test/Transforms/LoopVectorize/pseudoprobe.ll
M llvm/test/Transforms/LoopVectorize/ptr_loops.ll
M llvm/test/Transforms/LoopVectorize/read-only.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-address-space.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-readonly-address-space.ll
M llvm/test/Transforms/LoopVectorize/runtime-check.ll
M llvm/test/Transforms/LoopVectorize/same-base-access.ll
M llvm/test/Transforms/LoopVectorize/scalar-select.ll
M llvm/test/Transforms/LoopVectorize/simple-unroll.ll
M llvm/test/Transforms/LoopVectorize/small-loop.ll
M llvm/test/Transforms/LoopVectorize/start-non-zero.ll
M llvm/test/Transforms/LoopVectorize/struct_access.ll
M llvm/test/Transforms/LoopVectorize/unroll-novec-memcheck-metadata.ll
M llvm/test/Transforms/LoopVectorize/unroll_novec.ll
M llvm/test/Transforms/LoopVectorize/write-only.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/fma-conversion-multi-use-guard.ll
A llvm/test/Transforms/SLPVectorizer/X86/constant-based-reductions.ll
M llvm/test/Transforms/SROA/vector-promotion-via-tree-structure-merge.ll
A llvm/test/Transforms/SampleProfile/pseudo-probe-emit-macho.ll
A llvm/test/Transforms/SandboxVectorizer/load_store_vec.ll
M llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
M llvm/test/Transforms/VectorCombine/LoongArch/shuffle-identity-miscompile.ll
M llvm/test/tools/UpdateTestChecks/update_analyze_test_checks/Inputs/loop-distribute.ll.expected
M llvm/test/tools/llvm-mca/AArch64/A64FX/A64-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Apple/M1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A320-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A55-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A57-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/HiSilicon/tsv110-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Inputs/basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Olympus/basic-instructions.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
M llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
M llvm/tools/llc/llc.cpp
M llvm/tools/llvm-c-test/echo.cpp
M llvm/unittests/ADT/APIntTest.cpp
M llvm/unittests/Analysis/CFGTest.cpp
M llvm/unittests/BinaryFormat/MsgPackDocumentTest.cpp
M llvm/unittests/CodeGen/RematerializerTest.cpp
M llvm/unittests/DebugInfo/PDB/CMakeLists.txt
A llvm/unittests/DebugInfo/PDB/TpiStreamTest.cpp
M llvm/unittests/Support/CommandLineTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
M llvm/utils/TableGen/X86InstrMappingEmitter.cpp
M llvm/utils/gn/secondary/clang-tools-extra/unittests/clang-tidy/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Driver/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/FrontendTool/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/ScalableStaticAnalysisFramework/Analyses/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/ScalableStaticAnalysisFramework/BUILD.gn
M mlir/docs/Bindings/Python.md
M mlir/docs/Interfaces.md
M mlir/docs/Tools/mlir-reduce.md
A mlir/include/mlir/Bindings/Python/PythonBindings.td
A mlir/include/mlir/Bytecode/BytecodeDialectInterface.td
M mlir/include/mlir/Bytecode/BytecodeImplementation.h
M mlir/include/mlir/Bytecode/CMakeLists.txt
M mlir/include/mlir/Conversion/CMakeLists.txt
A mlir/include/mlir/Conversion/ConvertToEmitC/CMakeLists.txt
A mlir/include/mlir/Conversion/ConvertToEmitC/ConvertToEmitCPatternInterface.td
M mlir/include/mlir/Conversion/ConvertToEmitC/ToEmitCInterface.h
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/Dialect/Affine/Transforms/Passes.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/include/mlir/Dialect/MemRef/IR/MemRef.h
M mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtils.h
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td
M mlir/include/mlir/Dialect/SPIRV/IR/TargetAndABI.h
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/IR/BuiltinAttributes.td
M mlir/include/mlir/IR/ExtensibleDialect.h
M mlir/include/mlir/IR/OpDefinition.h
M mlir/include/mlir/IR/Operation.h
M mlir/include/mlir/IR/OperationSupport.h
M mlir/include/mlir/Interfaces/InferTypeOpInterface.td
M mlir/include/mlir/Interfaces/SideEffectInterfaces.h
A mlir/include/mlir/Interfaces/Utils/MemorySlotUtils.h
M mlir/lib/AsmParser/Parser.cpp
M mlir/lib/CAPI/IR/IR.cpp
M mlir/lib/CAPI/Interfaces/Interfaces.cpp
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/ArithToEmitC/ArithToEmitC.cpp
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Conversion/ArithToSPIRV/ArithToSPIRV.cpp
M mlir/lib/Conversion/ConvertToEmitC/CMakeLists.txt
M mlir/lib/Conversion/FuncToEmitC/FuncToEmitC.cpp
M mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitC.cpp
M mlir/lib/Conversion/SCFToControlFlow/SCFToControlFlow.cpp
M mlir/lib/Conversion/SCFToEmitC/SCFToEmitC.cpp
M mlir/lib/Conversion/SCFToSPIRV/SCFToSPIRV.cpp
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUOps.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Affine/Transforms/AffineExpandIndexOps.cpp
M mlir/lib/Dialect/Affine/Transforms/AffineExpandIndexOpsAsAffine.cpp
M mlir/lib/Dialect/Affine/Utils/Utils.cpp
M mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
M mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
M mlir/lib/Dialect/LLVMIR/IR/BasicPtxBuilderInterface.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/lib/Dialect/MemRef/Transforms/FoldMemRefAliasOps.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtils.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/OpenMP/Transforms/CMakeLists.txt
M mlir/lib/Dialect/OpenMP/Transforms/MarkDeclareTarget.cpp
M mlir/lib/Dialect/Ptr/IR/PtrDialect.cpp
M mlir/lib/Dialect/SCF/IR/CMakeLists.txt
M mlir/lib/Dialect/SCF/IR/MemorySlot.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/SMT/IR/SMTOps.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
M mlir/lib/Dialect/SPIRV/IR/TargetAndABI.cpp
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseAssembler.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransferOpTransforms.cpp
M mlir/lib/Dialect/WasmSSA/IR/WasmSSAOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToWiDistributeExperimental.cpp
M mlir/lib/Dialect/XeGPU/Utils/XeGPUUtils.cpp
M mlir/lib/IR/ExtensibleDialect.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/lib/IR/Operation.cpp
M mlir/lib/IR/OperationSupport.cpp
M mlir/lib/Interfaces/Utils/CMakeLists.txt
A mlir/lib/Interfaces/Utils/MemorySlotUtils.cpp
M mlir/lib/Target/IRDLToCpp/Templates/PerOperationDecl.txt
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Transforms/CSE.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/Analysis/test-alias-analysis-modref.mlir
M mlir/test/Conversion/AMDGPUToROCDL/gfx1250.mlir
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
M mlir/test/Conversion/ArithToSPIRV/arith-to-spirv.mlir
M mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir
M mlir/test/Conversion/SCFToControlFlow/convert-to-cfg.mlir
M mlir/test/Conversion/SCFToSPIRV/for.mlir
M mlir/test/Conversion/SCFToSPIRV/while.mlir
M mlir/test/Dialect/AMDGPU/invalid.mlir
M mlir/test/Dialect/AMDGPU/ops.mlir
M mlir/test/Dialect/Affine/affine-expand-index-ops-as-affine.mlir
M mlir/test/Dialect/Affine/affine-expand-index-ops.mlir
M mlir/test/Dialect/Affine/canonicalize.mlir
M mlir/test/Dialect/Affine/ops.mlir
M mlir/test/Dialect/Affine/scalrep.mlir
M mlir/test/Dialect/Arith/int-range-narrowing.mlir
M mlir/test/Dialect/Linalg/invalid.mlir
M mlir/test/Dialect/MemRef/canonicalize.mlir
M mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
M mlir/test/Dialect/MemRef/invalid.mlir
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
M mlir/test/Dialect/SCF/canonicalize.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops.mlir
M mlir/test/Dialect/Vector/vector-transfer-drop-unit-dims-patterns.mlir
M mlir/test/Dialect/XeGPU/sg-to-wi-experimental-unit.mlir
M mlir/test/IR/test-side-effects.mlir
A mlir/test/Target/LLVMIR/openmp-simd-linear.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
M mlir/test/Target/SPIRV/tosa-ops.mlir
M mlir/test/Transforms/cse.mlir
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/lib/Dialect/Test/TestOpsSyntax.cpp
M mlir/test/lib/Dialect/Test/TestOpsSyntax.td
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
M mlir/test/mlir-tblgen/op-decl-and-defs.td
M mlir/test/mlir-tblgen/op-python-bindings.td
M mlir/test/python/python_test_ops.td
M mlir/tools/mlir-tblgen/CppGenUtilities.cpp
M mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
M mlir/tools/mlir-tblgen/OpPythonBindingGen.cpp
M mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
M mlir/unittests/Debug/FileLineColLocBreakpointManagerTest.cpp
M mlir/unittests/IR/AttributeTest.cpp
M mlir/unittests/IR/OperationSupportTest.cpp
M mlir/unittests/IR/ValueTest.cpp
M mlir/unittests/IR/VerifierTest.cpp
M mlir/unittests/Interfaces/CMakeLists.txt
A mlir/unittests/Interfaces/MemorySlotUtilsTest.cpp
M mlir/unittests/Interfaces/SideEffectInterfacesTest.cpp
M mlir/unittests/Transforms/DialectConversion.cpp
M offload/test/CMakeLists.txt
M offload/test/offloading/target_critical_region.cpp
M openmp/cmake/modules/LibompUtils.cmake
M openmp/runtime/CMakeLists.txt
M openmp/runtime/cmake/LibompGetArchitecture.cmake
A openmp/runtime/cmake/arm64x.cmake
M openmp/runtime/src/CMakeLists.txt
M openmp/runtime/src/kmp.h
M openmp/runtime/src/kmp_atomic.cpp
A openmp/runtime/src/kmp_invoke_microtask.cpp
M openmp/runtime/src/kmp_os.h
M openmp/runtime/src/kmp_platform.h
M openmp/runtime/src/kmp_runtime.cpp
M openmp/runtime/src/thirdparty/ittnotify/ittnotify_config.h
M openmp/runtime/src/z_Linux_asm.S
M openmp/runtime/src/z_Linux_util.cpp
M openmp/runtime/src/z_Windows_NT-586_util.cpp
M openmp/runtime/test/misc_bugs/many-microtask-args.c
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/mlir-tblgen/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/unittests/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/amehsan/weakc-delta-overflow
Commit: 809239a24af9f17ca21b78f3885cf27acb2d149c
https://github.com/llvm/llvm-project/commit/809239a24af9f17ca21b78f3885cf27acb2d149c
Author: Ehsan Amiri <ehsan.amiri at huawei.com>
Date: 2026-04-01 (Wed, 01 Apr 2026)
Changed paths:
M llvm/lib/Analysis/DependenceAnalysis.cpp
Log Message:
-----------
address the nit command from code review
Compare: https://github.com/llvm/llvm-project/compare/c267c330400d...809239a24af9
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