[all-commits] [llvm/llvm-project] b3fed5: [AMDGPU] Fix setreg handling in the VGPR MSB lowering

[Stanislav Mekhanoshin via All-commits]

  Branch: refs/heads/users/rampitec/fix-msb-setreg-handling
  Home:   https://github.com/llvm/llvm-project
  Commit: b3fed589eb80b813395a63c2d5f4bcea72af8301
      https://github.com/llvm/llvm-project/commit/b3fed589eb80b813395a63c2d5f4bcea72af8301
  Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
  Date:   2026-03-27 (Fri, 27 Mar 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
    M llvm/test/CodeGen/AMDGPU/hazard-setreg-vgpr-msb-gfx1250.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-setreg-mode-swar.mir

  Log Message:
  -----------
  [AMDGPU] Fix setreg handling in the VGPR MSB lowering

There are multiple issues with it:

1. It can skip inserting S_SET_VGPR_MSB if we set the mode via
   piggybacking. We are now relying on the HW bug for correct
   behavior. If/when the bug is fixed lowering will be incorrect.
2. We should just unconditionally update MSBs if immediate allows it.
   We shall set correct bits and keep the rest of the immediate
   (that is done). There is no reasonable way for an user to change
   MSBs nor does it do anything good to set it with SETREG and then
   immediately overwrite with S_SET_VGPR_MSB.
3. We can always update immediate if Offset is zero.
4. Redundant mode changes created as seen in the
   hazard-setreg-vgpr-msb-gfx1250.mir.

With unconditional immediate update most of time and not relying on
the SETREG for setting MSBs there is no good reason to complicate
handling by supporting SETREG as a piggybacking target. Moreover,
piggybacking on SETREG becomes dangerous if offset handling is fixed.

Arguably we shall handle SETREG even w/o SWAR if it targets mask
covering MSB. An user cannot reasonably modify MSBs inside compiler's
workflow.

That said if someone uses non-imm form of setreg and targeting MSB
they are free to go shooting themselves into their foot because that
is non analyzable. But we do actually use imm form for bit 25 in
the compiler itself with non-zero offset.



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