[all-commits] [llvm/llvm-project] 46c47e: [Hexagon] Fix load/store widening to preserve subr...

[pkarveti via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 46c47efd07b6b8faa005e13f84342e38176e3e62
      https://github.com/llvm/llvm-project/commit/46c47efd07b6b8faa005e13f84342e38176e3e62
  Author: pkarveti <pkarveti at qti.qualcomm.com>
  Date:   2026-03-27 (Fri, 27 Mar 2026)

  Changed paths:
    M llvm/lib/Target/Hexagon/HexagonLoadStoreWidening.cpp
    A llvm/test/CodeGen/Hexagon/store-widen-subreg.mir

  Log Message:
  -----------
  [Hexagon] Fix load/store widening to preserve subreg operands (#188181)

HexagonLoadStoreWidening pass was incorrectly using DoubleRegs registers
where IntRegs was required when widening load/store pairs. When the
S2_addasl_rrri instruction used a subreg (e.g., %2.isub_lo), the
widening pass extracted only the base register without preserving the
subreg, causing machine verifier errors.



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