[all-commits] [llvm/llvm-project] e43ce5: [TargetLowering][RISCV] Prefer (S/U)MUL_LOHI over ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e43ce530145ded7028a29ba51091fdef1841ff9b
      https://github.com/llvm/llvm-project/commit/e43ce530145ded7028a29ba51091fdef1841ff9b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2026-03-26 (Thu, 26 Mar 2026)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/RISCV/rv32p.ll

  Log Message:
  -----------
  [TargetLowering][RISCV] Prefer (S/U)MUL_LOHI over MULH(S/U) in expandMULO. (#188870)

The RISC-V P extension adds WMUL and WMULU instruction that produce
a full 64-bit product in 2 GPRs. The base ISA already had MULH and
MULHU.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications