[all-commits] [llvm/llvm-project] 8c2008: [MLIR] Move SFINAE from return type to template ar...
Krzysztof Parzyszek via All-commits
all-commits at lists.llvm.org
Wed Mar 25 06:21:26 PDT 2026
Branch: refs/heads/users/kparzysz/e15-length-reason
Home: https://github.com/llvm/llvm-project
Commit: 8c200875d72fdce54bda82b6f39469d5f59c1701
https://github.com/llvm/llvm-project/commit/8c200875d72fdce54bda82b6f39469d5f59c1701
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M mlir/include/mlir/IR/OpImplementation.h
Log Message:
-----------
[MLIR] Move SFINAE from return type to template argument in OpImplementation.h (NFC) (#188039)
Migrate all template methods that used `std::enable_if_t<cond,
ReturnType>` return-type SFINAE to the `typename =
std::enable_if_t<cond>` default template parameter style. This makes the
actual return type visible at a glance and the constraint readable as
part of the template signature.
Complementary overload pairs that require the `* = nullptr` non-type
parameter trick to remain structurally distinct
(parseCustomAttributeWithFallback, parseCustomTypeWithFallback) are left
unchanged.
Addressing post-merge comment on #186192
Assisted-by: Claude Code
Commit: 61b3b20fd96ea06a32738915771543e0dd49a687
https://github.com/llvm/llvm-project/commit/61b3b20fd96ea06a32738915771543e0dd49a687
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
Log Message:
-----------
[AsmPrinter] Fix some issues with instruction size verification
If the instruction is part of a bundle, then emitInstruction() will
emit the entire bundle. As such, we should be summing up the sizes
of all instructions in the bundle.
Additionally, do not run the verification if an error has already
occurred. In that case, there may be a size mismatch as a result
of the error.
These came up when trying to enable the verification on additional
targets.
Commit: df00c1c00be26bff7d548b6baa5655c5254b601e
https://github.com/llvm/llvm-project/commit/df00c1c00be26bff7d548b6baa5655c5254b601e
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/AArch64/icmp-wrong-bitwidth.ll
Log Message:
-----------
[SLP][NFC]Add a test with the icmp miscompilation, NFC
Commit: af9bc2ab1ecc75e96cc086db18918e95e24b6df5
https://github.com/llvm/llvm-project/commit/af9bc2ab1ecc75e96cc086db18918e95e24b6df5
Author: Xinlong Chen <49522466+Xinlong-Chen at users.noreply.github.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
M llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg-mir.ll
M llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
M llvm/test/CodeGen/PowerPC/mergeable-string-pool-large.ll
M llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll
M llvm/test/CodeGen/PowerPC/pr59074.ll
Log Message:
-----------
[PowerPC] Skip tryBitfieldInsert when an operand is a constant (#187663)
When either operand of an OR node is a constant, bail out of
`tryBitfieldInsert` and let `ORI`/`ORIS`/`ADDI`/`ADDIS` tablegen
patterns handle it.
These patterns produce a single instruction without the tied-register
constraint that RLWIMI requires, avoiding unnecessary LI + RLWIMI
sequences.
Prep work to help with regressions identified on
https://github.com/llvm/llvm-project/pull/186461
Commit: 4a06f38c6b925eb587ac0b6ab51d9e3c5844d33c
https://github.com/llvm/llvm-project/commit/4a06f38c6b925eb587ac0b6ab51d9e3c5844d33c
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/test/Dialect/Linalg/invalid.mlir
Log Message:
-----------
[mlir][linalg] Fix crash in linalg.reduce verifier when inputs \!= inits count (#186278)
Add an early check in `ReduceOp::verify()` that compares the operand
count from the ODS accessor with `getNumDpsInputs()`. A mismatch means
the `SameVariadicOperandSize` invariant is violated and the verifier
emits a clear diagnostic instead of crashing.
Fixes #93973
Assisted-by: Claude Code
Commit: 40f0b312e3b7ab48fbd91360d892cc28e4baba6b
https://github.com/llvm/llvm-project/commit/40f0b312e3b7ab48fbd91360d892cc28e4baba6b
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
Log Message:
-----------
[clang][bytecode] Disable tail calls on MSVC and PPC (#188033)
Disable tail calls on MSVC and PPC.
Commit: 20fe74ebe19c844079f7093eeb945994274737a1
https://github.com/llvm/llvm-project/commit/20fe74ebe19c844079f7093eeb945994274737a1
Author: Adam Siemieniuk <adam.siemieniuk at intel.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/X86/X86.td
M mlir/lib/Dialect/Math/Transforms/PolynomialApproximation.cpp
M mlir/lib/Dialect/X86/IR/X86Dialect.cpp
M mlir/lib/Dialect/X86/Transforms/ShuffleVectorFMAOps.cpp
M mlir/lib/Dialect/X86/Transforms/VectorContractBF16ToFMA.cpp
M mlir/lib/Dialect/X86/Transforms/VectorContractToPackedTypeDotProduct.cpp
Log Message:
-----------
[mlir][x86] Hardware extension namespaces (#184392)
Adds hardware extension C++ namespaces to X86 dialect op definitions to
match their IR mnemonic extensions.
All X86 dialect ops are updated to follow the scheme first introduced
with AMX ops i.e., 'x86::{ext}::{op_name}'.
Nested namespaces improve source code readability by explicitly
indicating which hardware extension each operation requires, and it
aligns naming scheme between code and IR.
Commit: 256a4e03b7f4fb2b3a6865ff75385305e4cc8e73
https://github.com/llvm/llvm-project/commit/256a4e03b7f4fb2b3a6865ff75385305e4cc8e73
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane32.swap.ll
Log Message:
-----------
[AMDGPU][GlobalISel] Add RegBankLegalize rules for permlane16_swap/permlane32_swap (#187810)
Add register bank legalize rules for the amdgcn_permlane16_swap and
amdgcn_permlane32_swap intrinsics. Both results and both source register
operands map to VGPR since these are VALU lane swap operations.
Enable -new-reg-bank-select in the permlane16.swap and permlane32.swap
tests.
Commit: dfb2c773d22e2eb116cc71c6f14eec5dba7fd154
https://github.com/llvm/llvm-project/commit/dfb2c773d22e2eb116cc71c6f14eec5dba7fd154
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M mlir/lib/Dialect/Shard/Transforms/ShardingPropagation.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for misc-use-internal-linkage in ShardingPropagation.cpp (NFC)
Commit: a6caf52908bf499fd7fc3ae96dcd3ef8c41d5ce1
https://github.com/llvm/llvm-project/commit/a6caf52908bf499fd7fc3ae96dcd3ef8c41d5ce1
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/CoreEngine.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/ExplodedGraph.h
M clang/lib/StaticAnalyzer/Core/CoreEngine.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineCXX.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineCallAndReturn.cpp
Log Message:
-----------
[NFC][analyzer] Clean up and document `ExplodedNodeSet` (#187742)
`ExplodedNodeSet` is a simple and useful utility type in the analyzer,
but its insertion methods were a bit confusing, so this commit clarifies
them (and adds doc-comments for this class).
Previously this class had `void Add(ExplodedNode*)` for inserting single
nodes and `void insert(const ExplodedNodeSet &)` for inserting all nodes
from another set; but `ExplodedNode*` is implicitly convertible to
`ExplodedNodeSet`, so it was also possible to insert single nodes with
`insert`. There was also a subtle difference between `Set.Add(Node)` and
`Set.insert(Node)`: `Add` accepted and ignored nullpointers and sink
nodes (which is often useful) while the constructor
`ExplodedNodeSet(ExplodedNode*)` enforced the same invariant in a less
helpful way, with an assertion.
This commit eliminates the name `Add` (because `insert` is more
customary for set types), but standardizes its "null or sink nodes are
silently ignored" behavior which is very useful in practice.
After this commit `insert` has two overloads:
`ExplodedNodeSet::insert(ExplodedNode*)` which inserts a single node (or
does nothing if the argument is null or sink) and
`ExplodedNodeSet::insert(const ExplodedNodeSet&)` which inserts all
nodes from the other set.
Note that around half of the calls to `Add` were recently introduced by
my `NodeBuilder` cleanup commit series; I expect to introduce dozens of
calls in the foreseeable future -- this commit can be considered as
preparation for those.
Commit: f4b523d669faf92d096f335b6c9dc832521dba93
https://github.com/llvm/llvm-project/commit/f4b523d669faf92d096f335b6c9dc832521dba93
Author: Kiva <zengtao at iscas.ac.cn>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/include/llvm/IR/PatternMatch.h
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/unittests/IR/PatternMatch.cpp
Log Message:
-----------
[PatternMatch][NFC] Add `m_IToFP` and `m_FPToI` (#188040)
Added two patterns for IR pattern matching, `m_IToFP` and `m_FPToI`
which are basically shortcuts of `m_CombinedOr(..., ...)`
> if there isn't already one, PatternMatch should have an m_ItoFP which
covers both
_Originally posted by @arsenm in
https://github.com/llvm/llvm-project/pull/185826#discussion_r2967473936_
/cc @arsenm
Commit: 75ac07d3692828ca22b10dce2fc2208d7ea9e840
https://github.com/llvm/llvm-project/commit/75ac07d3692828ca22b10dce2fc2208d7ea9e840
Author: lntue <lntue at google.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M libc/src/__support/math/acosf.h
M libc/src/__support/math/asinf.h
M libc/src/__support/math/inv_trigf_utils.h
Log Message:
-----------
[libc][math] Use Estrin's scheme to improve asinf and acosf performance. (#187885)
Commit: a7efdeb464dd3ccb742a0125621853120c4ca4eb
https://github.com/llvm/llvm-project/commit/a7efdeb464dd3ccb742a0125621853120c4ca4eb
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M flang/include/flang/Parser/openmp-utils.h
M flang/include/flang/Parser/tools.h
M flang/lib/Parser/openmp-utils.cpp
M flang/lib/Parser/tools.cpp
M flang/lib/Semantics/canonicalize-do.cpp
M flang/lib/Semantics/resolve-labels.cpp
A flang/test/Semantics/bug2436.f
A flang/test/Semantics/canondo18.f90
Log Message:
-----------
[flang] Accept label DO loop after !$ACC LOOP (#187581)
Extend Semantics/canonicalize-do.cpp to rewrite a label DO loop into a
DO construct in the parse tree even when its terminal statement is an
OpenACC block construct or atomic construct. Some tools were relocated
from Parser/openmp-utils.{h,cpp} to /tools.{h,cpp}.
Commit: bd46a7d172661d4477737a65b107bf40782c7e40
https://github.com/llvm/llvm-project/commit/bd46a7d172661d4477737a65b107bf40782c7e40
Author: Carlo Cabrera <github at carlo.cab>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M .github/workflows/bazel-checks.yml
M .github/workflows/build-ci-container-tooling.yml
M .github/workflows/build-ci-container-windows.yml
M .github/workflows/build-ci-container.yml
M .github/workflows/build-libc-container.yml
M .github/workflows/build-metrics-container.yml
M .github/workflows/check-ci.yml
M .github/workflows/ci-post-commit-analyzer.yml
M .github/workflows/commit-access-greeter.yml
M .github/workflows/commit-access-review.yml
M .github/workflows/docs.yml
M .github/workflows/email-check.yaml
M .github/workflows/gha-codeql.yml
M .github/workflows/hlsl-test-all.yaml
M .github/workflows/ids-check.yml
M .github/workflows/issue-subscriber.yml
M .github/workflows/issue-write.yml
M .github/workflows/libc-fullbuild-tests.yml
M .github/workflows/libc-overlay-tests.yml
M .github/workflows/libclang-abi-tests.yml
M .github/workflows/libclang-python-tests.yml
M .github/workflows/libcxx-build-and-test.yaml
M .github/workflows/libcxx-build-containers.yml
M .github/workflows/libcxx-check-generated-files.yml
M .github/workflows/libcxx-run-benchmarks.yml
M .github/workflows/lldb-pylint-action.yml
M .github/workflows/llvm-abi-tests.yml
M .github/workflows/merged-prs.yml
M .github/workflows/mlir-spirv-tests.yml
M .github/workflows/new-prs.yml
M .github/workflows/pr-code-format.yml
M .github/workflows/pr-code-lint.yml
M .github/workflows/pr-subscriber.yml
M .github/workflows/premerge.yaml
M .github/workflows/prune-branches.yml
M .github/workflows/release-asset-audit.yml
M .github/workflows/release-binaries.yml
M .github/workflows/release-documentation.yml
M .github/workflows/release-doxygen.yml
M .github/workflows/release-sources.yml
M .github/workflows/release-tasks.yml
M .github/workflows/spirv-tests.yml
M .github/workflows/sycl-tests.yml
M .github/workflows/test-unprivileged-download-artifact.yml
M .github/workflows/version-check.yml
Log Message:
-----------
[Workflows] Set `persist-credentials` (#187951)
This is needed for #187905. Unless we disable the check, Zizmor will
flag uses of `actions/checkout` without an explicit
`persist-credentials` setting.
Of course, some workflows could rely on the credentials persisted by
`actions/checkout`. I asked Claude to check each affected job, and it
flagged only `prune-branches.yml`. The script `prune-unused-branches.py`
relies on the persisted credentials, so I've left that as
`persist-credentials: true` for now.
Commit: a90f583e7a11703aab50bdc5ece8717e089c69da
https://github.com/llvm/llvm-project/commit/a90f583e7a11703aab50bdc5ece8717e089c69da
Author: Carlo Cabrera <github at carlo.cab>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
A .github/workflows/zizmor.yml
Log Message:
-----------
[Workflows] Add Zizmor check (#187905)
The recent Trivy breach[^1] made me consider re-opening #117787.
Trivy was breached using an impostor commit[^2], which Zizmor can flag.
It's also much more widely used since my last PR.[^3]
The new workflow was taken from the example workflow in their
documentation.[^4]
[^1]: https://github.com/aquasecurity/trivy/discussions/10425
[^2]: https://docs.zizmor.sh/audits/#impostor-commit
[^3]: https://docs.zizmor.sh/trophy-case/
[^4]: https://docs.zizmor.sh/integrations/#via-zizmorcorezizmor-action
Commit: 034054431d6cb280c70f51291aa6ec938a0118a6
https://github.com/llvm/llvm-project/commit/034054431d6cb280c70f51291aa6ec938a0118a6
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
Log Message:
-----------
AMDGPU: Fix src2_modifiers for v_dot2_f32_f16/bf16 (#179224)
Commit: 5b7ad38d6ba835e4d4acef538846931fd64a2028
https://github.com/llvm/llvm-project/commit/5b7ad38d6ba835e4d4acef538846931fd64a2028
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/icmp-wrong-bitwidth.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/trunc-insertion.ll
Log Message:
-----------
[SLP]Fix codegen of compares with consts, being trunced
If the const values have more active bits, than requested by the another
operand of the compare, such constants should not be trunced to avoid
miscompilation
Commit: a9775221ae31d626ceacdb72a49550ba7e566d67
https://github.com/llvm/llvm-project/commit/a9775221ae31d626ceacdb72a49550ba7e566d67
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M clang/lib/CodeGen/Targets/NVPTX.cpp
A llvm/include/llvm/Support/NVVMAttributes.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXCtorDtorLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXGenericToNVVM.cpp
M llvm/lib/Target/NVPTX/NVPTXImageOptimizer.cpp
M llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp
M llvm/lib/Target/NVPTX/NVVMProperties.cpp
M llvm/lib/Target/NVPTX/NVVMProperties.h
M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
Log Message:
-----------
[NVPTX] Canonicalize NVVM attribute strings and refactor property queries (NFC) (#187752)
Commit: 7bda811f5a034263a0128a7cacfb4f2827be2b5e
https://github.com/llvm/llvm-project/commit/7bda811f5a034263a0128a7cacfb4f2827be2b5e
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
Log Message:
-----------
[clang][bytecode] Disable tailcalls on aarch64 (#188042)
Apparently it causes problems there, too.
See https://lab.llvm.org/buildbot/#/builders/24/builds/18781
Commit: b16efa69ee5ca67331348e4a41e7304a9d51af42
https://github.com/llvm/llvm-project/commit/b16efa69ee5ca67331348e4a41e7304a9d51af42
Author: Jorn Tuyls <jorn.tuyls at gmail.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M mlir/include/mlir/Bindings/Python/IRCore.h
Log Message:
-----------
[mlir][python] Fix PyObjectRef copy/move assignment for MSVC (#186758)
PyObjectRef has a user-declared move constructor but no explicit
copy/move assignment operators. On at least some version of MSVC,
instantiation of operator= is forced, causing a compile error:
```
In file included from mlir/lib/Bindings/Python/Globals.cpp:9:
In file included from mlir/include/mlir/Bindings/Python/IRCore.h:16:
<MSVC>/include/vector(1461,27): error: object of type 'value_type' (aka 'mlir::python::mlir::PyDiagnostic::DiagnosticInfo') cannot be assigned because its copy assignment operator is implicitly deleted
1461 | *_Mid = *_First;
| ^
<MSVC>/include/vector(1539,9): note: in instantiation of function template specialization 'std::vector<mlir::python::mlir::PyDiagnostic::DiagnosticInfo>::_Assign_counted_range<mlir::python::mlir::PyDiagnostic::DiagnosticInfo *>' requested here
1539 | _Assign_counted_range(_Right_data._Myfirst, static_cast<size_type>(_Right_data._Mylast - _Right_data._Myfirst));
| ^
mlir/include/mlir/Bindings/Python/IRCore.h(1317,33): note: in instantiation of member function 'std::vector<mlir::python::mlir::PyDiagnostic::DiagnosticInfo>::operator=' requested here
1317 | struct MLIR_PYTHON_API_EXPORTED MLIRError {
| ^
mlir/include/mlir/Bindings/Python/IRCore.h(369,16): note: copy assignment operator of 'DiagnosticInfo' is implicitly deleted because field 'location' has a deleted copy assignment operator
369 | PyLocation location;
| ^
mlir/include/mlir/Bindings/Python/IRCore.h(304,45): note: copy assignment operator of 'PyLocation' is implicitly deleted because base class 'BaseContextObject' has a deleted copy assignment operator
304 | class MLIR_PYTHON_API_EXPORTED PyLocation : public BaseContextObject {
| ^
mlir/include/mlir/Bindings/Python/IRCore.h(300,20): note: copy assignment operator of 'BaseContextObject' is implicitly deleted because field 'contextRef' has a deleted copy assignment operator
300 | PyMlirContextRef contextRef;
| ^
mlir/include/mlir/Bindings/Python/IRCore.h(73,3): note: copy assignment operator is implicitly deleted because 'PyObjectRef<mlir::python::mlir::PyMlirContext>' has a user-declared move constructor
73 | PyObjectRef(PyObjectRef &&other) noexcept
| ^
1 error generated.
```
Encountered on this env:
```
Compiler: clang-cl 20.1.8
STL: MSVC 14.44.35207 (Visual Studio 2022 Enterprise)
Runner: windows-2022 (GitHub Actions)
```
Commit: 7152266d80c58201a583d56942b278261f1730b0
https://github.com/llvm/llvm-project/commit/7152266d80c58201a583d56942b278261f1730b0
Author: Marco Elver <elver at google.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/docs/ThreadSafetyAnalysis.rst
M clang/include/clang/Analysis/Analyses/ThreadSafety.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/AST/ASTImporter.cpp
M clang/lib/Analysis/ThreadSafety.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/test/Sema/warn-thread-safety-analysis.c
M clang/test/SemaCXX/thread-safety-annotations.h
M clang/test/SemaCXX/warn-thread-safety-analysis.cpp
M clang/test/SemaCXX/warn-thread-safety-parsing.cpp
M clang/unittests/AST/ASTImporterTest.cpp
Log Message:
-----------
Thread Safety Analysis: Support guarded_by/pt_guarded_by with multiple capabilities (#186838)
Previously, `guarded_by` and `pt_guarded_by` only accepted a single
capability argument. Introduce support for declaring that a variable is
guarded by multiple capabilities, which exploits the following property:
any writer must hold all capabilities, so holding any one of them
(exclusive or shared) guarantees at least shared (read) access.
Therefore, writing requires all listed capabilities to be held
exclusively, while reading only requires at least one to be held.
This synchronization pattern is frequently used where the underlying
lock implementation does not support real reader locking, and instead
several lock "shards" are used to reduce contention for readers. For
example, the Linux kernel makes frequent use of this pattern [1].
Backwards compatibility is not affected by this change: for the time
being we deliberately do not change the semantics of multiple stacked
attributes (this retains existing semantics precisely, while giving a
way to choose the "stricter" semantics if needed).
Previous Version: https://github.com/llvm/llvm-project/pull/185173
Link: https://lore.kernel.org/all/20250307085204.GJ16878@noisy.programming.kicks-ass.net/ [1]
Commit: be31cffb422da20898685aa4c4a572659006f909
https://github.com/llvm/llvm-project/commit/be31cffb422da20898685aa4c4a572659006f909
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M flang/test/Lower/Intrinsics/minval.f90
M flang/test/Lower/Intrinsics/modulo.f90
M flang/test/Lower/Intrinsics/move_alloc.f90
M flang/test/Lower/Intrinsics/mvbits.f90
M flang/test/Lower/Intrinsics/not.f90
Log Message:
-----------
[flang][NFC] Converted five tests from old lowering to new lowering (part 37) (#188009)
Tests converted from test/Lower/Intrinsics: minval.f90, modulo.f90,
move_alloc.f90, mvbits.f90, not.f90
Commit: ed3d3bfc75b5f2afddf5cd823460a0d39de36562
https://github.com/llvm/llvm-project/commit/ed3d3bfc75b5f2afddf5cd823460a0d39de36562
Author: Davide Grohmann <davide.grohmann at arm.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td
M mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops.mlir
M mlir/test/Target/SPIRV/tosa-ops.mlir
Log Message:
-----------
[mlir][spirv] Add first 3 data layout ops in TOSA Ext Inst Set (#187714)
This patch introduces the following reduction operators:
spirv.Tosa.Concat
spirv.Tosa.Pad
spirv.Tosa.Reshape
Also dialect and serialization round-trip tests have been added.
Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
Commit: c75b8a1649d4f132eefbfc741e68bda0f81e3f24
https://github.com/llvm/llvm-project/commit/c75b8a1649d4f132eefbfc741e68bda0f81e3f24
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Log Message:
-----------
[TargetLowering] Avoid unnecessary nodes in the chunk loop in expandDIVREMByConstant (#187967)
We don't need an AND on the last iteration. If we shifted the dividend
due to trailing zeros in the divisor, we don't need a chunk that only
contains shifted in zeros.
Commit: 0afc30f8d528dc15634b762cd64682707d8f7da5
https://github.com/llvm/llvm-project/commit/0afc30f8d528dc15634b762cd64682707d8f7da5
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Log Message:
-----------
[TargetLowering] Add helper to create FSHR like operation in expandDIVREMByConstant. NFC (#187979)
Commit: 6e5e1c97e024582bcca8eccf9b78f3b5d0991024
https://github.com/llvm/llvm-project/commit/6e5e1c97e024582bcca8eccf9b78f3b5d0991024
Author: laoshd <shandong.lao at hpe.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M flang-rt/include/flang-rt/runtime/format-implementation.h
M flang-rt/include/flang-rt/runtime/format.h
M flang-rt/lib/runtime/edit-output.cpp
M flang-rt/lib/runtime/io-api.cpp
M flang-rt/lib/runtime/io-stmt.cpp
M flang-rt/unittests/Runtime/CMakeLists.txt
A flang-rt/unittests/Runtime/LeadingZeroTest.cpp
M flang/docs/F202X.md
M flang/docs/FortranStandardsSupport.md
M flang/include/flang/Common/format.h
M flang/include/flang/Optimizer/Transforms/RuntimeFunctions.inc
M flang/include/flang/Parser/format-specification.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Runtime/io-api.h
M flang/include/flang/Support/Fortran.h
M flang/lib/Lower/IO.cpp
M flang/lib/Parser/io-parsers.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/check-io.cpp
A flang/test/Semantics/io18.f90
M flang/test/Transforms/set-runtime-call-attributes.fir
M flang/test/Transforms/verify-known-runtime-functions.fir
Log Message:
-----------
[flang][flang-rt] Implement F202X leading-zero control edit descriptors LZ, LZS, and LZP for formatted output (F, E, D, and G editing) (#183500)
LZ: processor-dependent (default, flang prints leading zero); LZS:
suppress the optional leading zero before the decimal point; LZP: print
the optional leading zero before the decimal point. Changes span the
source parser, compile-time format validator, runtime format processing,
and runtime output formatting. Includes semantic test (io18.f90) and
documentation updates.
Commit: a57db57e1b6a57c02eeb0def2dea6e969dc5fec7
https://github.com/llvm/llvm-project/commit/a57db57e1b6a57c02eeb0def2dea6e969dc5fec7
Author: Steven Perron <stevenperron at google.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.h
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/AST/HLSL/Texture2D-scalar-AST.hlsl
M clang/test/AST/HLSL/Texture2D-vector-AST.hlsl
M clang/test/CodeGenHLSL/resources/ByteAddressBuffers-methods.hlsl
M clang/test/CodeGenHLSL/resources/StructuredBuffers-methods-lib.hlsl
M clang/test/CodeGenHLSL/resources/StructuredBuffers-methods-ps.hlsl
M clang/test/CodeGenHLSL/resources/StructuredBuffers-subscripts.hlsl
A clang/test/CodeGenHLSL/resources/Texture2D-Subscript.hlsl
M clang/test/CodeGenHLSL/resources/TypedBuffers-methods.hlsl
M clang/test/CodeGenHLSL/resources/TypedBuffers-subscript.hlsl
M clang/test/SemaHLSL/BuiltIns/resource_getpointer-errors.hlsl
A clang/test/SemaHLSL/Resources/Texture2D-Subscript.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/test/CodeGen/DirectX/MemIntrinsics/memcpy-pointee.ll
M llvm/test/CodeGen/DirectX/forward_handle_on_alloca.ll
M llvm/test/Transforms/GVN/PRE/no-pre-load-for-token-like.ll
M llvm/test/Transforms/GVN/no-sink-dxgetpointer.ll
M llvm/test/Transforms/SimplifyCFG/DirectX/no-sink-dxgetpointer.ll
M llvm/test/Transforms/SimplifyCFG/token_like_type.ll
Log Message:
-----------
[HLSL] Implement Texture2D::operator[] (#186110)
Implments the Texture2D::operator[] method. It uses the same design as
Buffer::operator[]. However, this requires us to chagne the
resource_getpointer intrinsic to accept integer vectors for the index.
Assisted-by: Gemini
Commit: 074851578402961ef2caa82e32461086e0cbe534
https://github.com/llvm/llvm-project/commit/074851578402961ef2caa82e32461086e0cbe534
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for mov_dpp (#187807)
Commit: ce5a1dffa228885b0b7e7811e95dae93277a6c4f
https://github.com/llvm/llvm-project/commit/ce5a1dffa228885b0b7e7811e95dae93277a6c4f
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
Log Message:
-----------
AMDGPU: Improve codegen for VOP2 v_dot2c_f32_f16/bf16 (#179225)
Select VOP2 version when there are no src_modifers, otherwise VOP3.
Commit: 7fa2752a286bb86945b929356c1dc7d429bcbcdb
https://github.com/llvm/llvm-project/commit/7fa2752a286bb86945b929356c1dc7d429bcbcdb
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/Support/APFloat.cpp
Log Message:
-----------
[NFC][Support] Minor code cleanup in APFloat.cpp (#187526)
Minor code cleanup: define variables at their first assignment as
opposed to at the start of functions, and use `[[maybe_unused]]` for
variables used in assert only.
Commit: b2edc0a3f8a5c711ff894dda9541a46874633511
https://github.com/llvm/llvm-project/commit/b2edc0a3f8a5c711ff894dda9541a46874633511
Author: Folkert de Vries <folkert at folkertdev.nl>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/CMakeLists.txt
M llvm/lib/Target/WebAssembly/WebAssembly.h
A llvm/lib/Target/WebAssembly/WebAssemblyReduceToAnyAllTrue.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
A llvm/test/CodeGen/WebAssembly/any-all-true.ll
Log Message:
-----------
wasm: recognize `any_true` and `all_true` (#155885)
fixes https://github.com/llvm/llvm-project/issues/129441
cc @lukel97 @badumbatish
https://github.com/llvm/llvm-project/pull/145108
I've been learning a bit about LLVM, trying to make progress on some of
these issues. The code below is based on
https://github.com/llvm/llvm-project/pull/145108#issuecomment-3004561085,
by implementing `shouldExpandReduction`.
The implementation works for the test cases I added, but (obviously)
fails for any existing cases. `ISD::VECREDUCE_AND` and
`ISD::VECREDUCE_OR` are now marked as legal, which is required for the
`Pat`s to fire, but when they don't that causes a selection failure.
So, I'm wondering, what is the right approach here. Should I mark these
intrinsics as `Custom` instead and manually perform the transformation
in C++? Or is there some trick to still get the default lowering (a
series of loads and scalar bitwise operations) when the patterns don't
fire?
Commit: 44df4116c87c023264c2a0551f808f031489e8f9
https://github.com/llvm/llvm-project/commit/44df4116c87c023264c2a0551f808f031489e8f9
Author: Simon Tatham <simon.tatham at arm.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M compiler-rt/cmake/Modules/CompilerRTUtils.cmake
M compiler-rt/lib/builtins/CMakeLists.txt
M compiler-rt/test/builtins/CMakeLists.txt
Log Message:
-----------
[compiler-rt][ARM] cmake properties for complicated builtin sources (#179919)
In the builtins library, most functions have a portable C implementation
(e.g. `mulsf3.c`), and platforms might provide an optimized assembler
implementation (e.g. `arm/mulsf3.S`). The cmake script automatically
excludes the C source file corresponding to each assembly source file it
includes. Additionally, each source file name is automatically
translated into a flag that lit tests can query, with a name like
`librt_has_mulsf3`, to indicate that a function is available to be
tested.
In future commits I plan to introduce cases where a single .S file
provides more than one function (so that they can share code easily),
and therefore, must supersede more than one existing source file.
I've introduced the `crt_supersedes` cmake property, which you can set
on a .S file to name a list of .c files that it should supersede. Also,
the `crt_provides` property can be set on any source file to indicate a
list of functions it makes available for testing, in addition to the one
implied by its name.
Commit: 0e0dc535d1b3df0faa84df03e7a9b1fb46b4276d
https://github.com/llvm/llvm-project/commit/0e0dc535d1b3df0faa84df03e7a9b1fb46b4276d
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.m0.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ptr.ll
Log Message:
-----------
AMDGPU/GlobalISel: Use B32 for readfirstlane (#187809)
Using B32 would also add missing pointer support to readfirstlane
intrinsic rule.
Commit: b670265b588f51eac9f7cc08edb3787361022af8
https://github.com/llvm/llvm-project/commit/b670265b588f51eac9f7cc08edb3787361022af8
Author: Xinlong Chen <49522466+Xinlong-Chen at users.noreply.github.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/AArch64/insertextract.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
M llvm/test/CodeGen/ARM/combine-vmovdrr.ll
M llvm/test/CodeGen/ARM/pr122670-regression.ll
M llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/aix32-p8-scalar_vector_conversions.ll
M llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
M llvm/test/CodeGen/RISCV/xaluo.ll
M llvm/test/CodeGen/RISCV/xqcisls.ll
M llvm/test/CodeGen/RISCV/xtheadmemidx.ll
M llvm/test/CodeGen/X86/avx512-insert-extract.ll
M llvm/test/CodeGen/X86/clmul-vector.ll
M llvm/test/CodeGen/X86/known-bits.ll
Log Message:
-----------
[DAG] ComputeKnownBits - set low bit to zero for ADD(X,X) (#186461)
ADD(X,X) is equivalent to SHL(X,1), so bit[0] is always zero.
This allows downstream folds like `and(add(x,x), 1) -> 0`.
Fixes #186091
Commit: 27adb8f7ad47380011d879bada73ddb5b28ed6f7
https://github.com/llvm/llvm-project/commit/27adb8f7ad47380011d879bada73ddb5b28ed6f7
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.compr.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for exp_compr (#187822)
This intrinsic only accepts vectorTy. Correct the test to use v2s16.
Commit: ada44b090b7b0f2bf17716b12c2964ba09240878
https://github.com/llvm/llvm-project/commit/ada44b090b7b0f2bf17716b12c2964ba09240878
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
Log Message:
-----------
[clang][bytecode] Avoid a macro redefinition (#188052)
Fixes:
```
/home/b/sanitizer-aarch64-linux/build/llvm-project/clang/lib/AST/ByteCode/Interp.cpp:46:9: error: 'MUSTTAIL' macro redefined [-Werror,-Wmacro-redefined]
46 | #define MUSTTAIL
| ^
/home/b/sanitizer-aarch64-linux/build/llvm-project/clang/lib/AST/ByteCode/Interp.cpp:32:9: note: previous definition is here
32 | #define MUSTTAIL [[clang::musttail]]
| ^
1 error generated.
```
Commit: d69c6709349b9672502f22917a325ccfa44d516b
https://github.com/llvm/llvm-project/commit/d69c6709349b9672502f22917a325ccfa44d516b
Author: Jasmine Tang <jjasmine at igalia.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
A llvm/test/Transforms/SLPVectorizer/WebAssembly/simd-splat-shuffle-cost.ll
Log Message:
-----------
[WebAssembly] Add initial shuffle cost capabilities (#187596)
Fixes #178940
Fixes the case of i16x8, i8x16 manual splat not recognized but the case of i32x4 still remains.
Commit: 3e4efe3ed4a2eedf49f2296e0ab9a7d4a65c2f7c
https://github.com/llvm/llvm-project/commit/3e4efe3ed4a2eedf49f2296e0ab9a7d4a65c2f7c
Author: Austin Kerbow <Austin.Kerbow at amd.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
A llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
A llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
A llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
A llvm/test/CodeGen/AMDGPU/coexec-sched-warning.mir
Log Message:
-----------
[AMDGPU] Add ML-oriented coexec scheduler selection and queue handling (#169616)
This patch adds the initial coexec scheduler scaffold for machine
learning workloads on gfx1250.
It introduces function and module-level controls for selecting the
AMDGPU preRA and postRA schedulers, including an `amdgpu-workload-type`
module flag that maps ML workloads to coexec preRA scheduling and a nop
postRA scheduler by default.
It also updates the coexec scheduler to use a simplified top-down
candidate selection path that considers both available and pending
queues through a single flow, setting up follow-on heuristic work.
Commit: da5d4214bc89021558311055bb5cd905a78020bd
https://github.com/llvm/llvm-project/commit/da5d4214bc89021558311055bb5cd905a78020bd
Author: Robert Konicar <rkonicar at mail.muni.cz>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M mlir/include/mlir/IR/OpImplementation.h
M mlir/lib/AsmParser/AsmParserImpl.h
M mlir/test/IR/enum-attr-roundtrip.mlir
M mlir/test/lib/Dialect/Test/TestEnumDefs.td
M mlir/test/lib/Dialect/Test/TestOpsSyntax.td
M mlir/tools/mlir-tblgen/EnumsGen.cpp
Log Message:
-----------
[MLIR][TableGen] Make optional enum parser not consume the token when it is not matched (#188008)
Previously the optional parser would consume the token even when it
failed to match a value of the enum and prevented parsers later in the
op syntax from having an attempt. This PR changes that so that the token
is consumed only when the parsing succeeds. This change is made to the
emitted `FieldParser<std::optional<T>>` for enums.
This, for example, allows having a simple list of default valued props
in the assembly format without needing decorations around them. This
mimics the behaviour that is emitted for `DefaultValuedAttribute` when
it is used with `EnumAttr`.
This PR also adds `parseOptionalString` variant with an allow-list
argument as `parseOptionalKeyword` has and adds
`parseOptionalKeywordOrString` allow-list variant which combines these
two into a single utility wrapper. These methods do not consume the
token unless it is from the allow-list.
Commit: 079be4e73982e1c7e0cddb8f9bd1b2009c6fb720
https://github.com/llvm/llvm-project/commit/079be4e73982e1c7e0cddb8f9bd1b2009c6fb720
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M libc/utils/libctest/format.py
Log Message:
-----------
[libc] Support Windows test executables in LibcTest lit format (#188057)
Updated LibcTest to handle Windows test executables:
* Added support for .exe extensions when identifying test executables.
* Skipped the executable bit check on Windows as it is not applicable.
* Updated .params file discovery to look for both <test>.exe.params and
<test>.params.
This allows running libc tests on Windows hosts.
Commit: af37ac8aee16f1a32c7f323bdb62c7019aad6322
https://github.com/llvm/llvm-project/commit/af37ac8aee16f1a32c7f323bdb62c7019aad6322
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/reduction-across-different-bb.ll
Log Message:
-----------
[SLP]Use reduction root explicitly from reduction analysis to avoid non-determinism
Initially, the reduction root was detected using the last member of the UserIgnoreList set, which is unordered. Better to use the reduction root explicitly to avoid non-determinism in the reduction parent block, which may cause incorrect scale factor estimation for the reduction cost.
Commit: b32b31e6a7d003a96d8110c3debd891ba6977d25
https://github.com/llvm/llvm-project/commit/b32b31e6a7d003a96d8110c3debd891ba6977d25
Author: NeKon69 <nobodqwe at gmail.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/test/Sema/warn-lifetime-safety.cpp
Log Message:
-----------
[LifetimeSafety] Fix compiler crash with `static operator()` (#187853)
This PR removes the first argument from the `Args` list (which is `S()`)
before doing lifetime safety checks to ensure correct indexing.
It also adds a test to prevent regressions in the future
Fixes #187426
<details>
<summary>Bug details</summary>
When calling a `static operator()` directly (with `S()(...)`), we also
store `S()` in `Args` as the first argument, so all indexing is off by
one.
The most interesting part is that `S::operator()(...)` works correctly
and does not add `S()` at the beginning of the argument list, so it does
not crash during lifetime checks.
This solution is probably not the cleanest, but I would love to hear
feedback on where to put it!
</details>
Commit: 94239b34508d48434f73b1b8ae874e9ec6d83d2b
https://github.com/llvm/llvm-project/commit/94239b34508d48434f73b1b8ae874e9ec6d83d2b
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/permlane16_opsel.ll
Log Message:
-----------
[AMDGPU][GlobalISel] Add RegBankLegalize rules for permlane16/permlanex16 (#187906)
Add RegBankLegalize rules for the amdgcn_permlane16
and amdgcn_permlanex16 intrinsics. Both intrinsics
are sources of divergence, so only the divergent
case is needed: result, old, and src0 map to VGPR,
while src1 and src2 are SGPR with ReadFirstLane if
divergent.
Update the GISEL RUN lines in llvm.amdgcn.permlane.ll
and permlane16_opsel.ll to use -new-reg-bank-select,
and regenerate check lines. The v8i16 test cases now
produce identical SDAG/GISEL output so their checks
are unified.
Commit: 239ca11a55b40ce12b21bc47e45cb4065d1cc3d4
https://github.com/llvm/llvm-project/commit/239ca11a55b40ce12b21bc47e45cb4065d1cc3d4
Author: Théo Degioanni <tdegioanni at nvidia.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/SCF/IR/SCF.h
M mlir/include/mlir/Dialect/SCF/IR/SCFOps.td
M mlir/include/mlir/Interfaces/MemorySlotInterfaces.td
M mlir/lib/Dialect/MemRef/IR/MemRefMemorySlot.cpp
M mlir/lib/Dialect/SCF/IR/CMakeLists.txt
A mlir/lib/Dialect/SCF/IR/MemorySlot.cpp
M mlir/lib/Transforms/Mem2Reg.cpp
M mlir/test/Dialect/LLVMIR/mem2reg.mlir
M mlir/test/Dialect/MemRef/mem2reg.mlir
A mlir/test/Dialect/SCF/mem2reg-reject.mlir
A mlir/test/Dialect/SCF/mem2reg.mlir
M mlir/test/Transforms/mem2reg.mlir
Log Message:
-----------
[MLIR][Mem2Reg] Add support for region control flow and SCF (#185036)
This PR adds support for region control-flow. Region control-flow and
CFG can be mixed together in the same program. See the [accompanying
RFC](https://discourse.llvm.org/t/rfc-support-region-control-flow-in-mem2reg/90082)
for some design considerations.
Beyond the considerations in the RFC, a few minor changes were
introduced:
- Calling the visitor hook for defined values is now deferred to the end
of promotion.
- The lazy creation of default values has been moved to the places where
it happens to prepare for a future change where it is actually lazy.
Documentation about it not working as intended for now was also added.
All SCF operations are supported, including `forall` and `parallel`,
which is pretty cool I think.
I am sorry in advance for git diff displaying a really bad diff for
Mem2Reg.cpp around where the liveness analysis used to be. Do consider
simply reading this part of the code off the file.
As a disclaimer, I designed all the test cases myself, but I used a
large amount of matrix multiplications to produce the corresponding IR
and FileCheck tests. I have reviewed them carefully and they correspond
to my intent.
---------
Co-authored-by: Slava Zakharin <szakharin at nvidia.com>
Commit: 1aa64ff937e71a64710b6290169eeaefa3374fcb
https://github.com/llvm/llvm-project/commit/1aa64ff937e71a64710b6290169eeaefa3374fcb
Author: Sarah Spall <sarahspall at microsoft.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/CodeGenHLSL/BasicFeatures/InitLists.hlsl
Log Message:
-----------
[HLSL] handle hlslAttributedResourceType in init list code (#187813)
Handle HLSL Attributed Resource Type in the init list code. Treat it
like its a scalar value.
Closes #187568
Commit: 54a3518fc3a9efad598d6a83c90fff316bb8f6c1
https://github.com/llvm/llvm-project/commit/54a3518fc3a9efad598d6a83c90fff316bb8f6c1
Author: Joshua Batista <jbatista at microsoft.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/CodeGenHLSL/builtins/WaveActiveBitAnd-errors.hlsl
A clang/test/CodeGenHLSL/builtins/WaveActiveBitAnd.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll
A llvm/test/CodeGen/DirectX/WaveActiveBitAnd.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveBitAnd.ll
Log Message:
-----------
[HLSL] Add WaveActiveBitAnd builtin function (#187149)
This PR adds the WaveActiveBitAnd HLSL function.
Fixes https://github.com/llvm/llvm-project/issues/99166
Commit: c624851037b0d5f4b42880b57d137f94241215c9
https://github.com/llvm/llvm-project/commit/c624851037b0d5f4b42880b57d137f94241215c9
Author: Alan Zhao <ayzhao at google.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
A llvm/test/Transforms/LoopVectorize/X86/cost-divisor-overflow.ll
Log Message:
-----------
[LoopVectorize] Fix an integer narrowing conversion in `getPredBlockCostDivisor(...)` (#187605)
`LoopVectorizationCostModel::getPredBlockCostDivisor(...)` may return
large `uint64_t` values that get coerced to an `unsigned` by
`VPCostContext::getPredBlockCostDivisor(...)`, which can cause division
by zero.
Fixes #187584
Commit: 4cef1c13416d020cc2f8a67a374ff34b444f1b5b
https://github.com/llvm/llvm-project/commit/4cef1c13416d020cc2f8a67a374ff34b444f1b5b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/bitcnt-big-integer.ll
Log Message:
-----------
[X86] canonicalizeShuffleWithOp - add handling for SHUFFLE(PSADBW(X,Y),PSADBW(Z,W)) -> PSADBW(SHUFFLE(X,Z),SHUFFLE(Y,W)) (#188072)
PSADBW takes vXi8 inputs and gives a vXi64 result so we need to tweak
the bitcasts (shuffle types checks will already ensure that the result
type isn't affected).
Minor improvement to #187447
Commit: a9ae2fd79eaef357b77c5c71ae067b1ed6da14b6
https://github.com/llvm/llvm-project/commit/a9ae2fd79eaef357b77c5c71ae067b1ed6da14b6
Author: Andrei Elovikov <andrei.elovikov at sifive.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/pointer-induction-index-width-smaller-than-iv-width.ll
Log Message:
-----------
[NFC][LV] Fix what seems to be a typo in the test (#187769)
The test was added in
https://github.com/llvm/llvm-project/commit/4e9894498e166ef6b207c25e780db0b6f006cc89.
Alternative fixes would be:
* Remove unused GEP, although not clear why we'd want to overwrite
stored `i64` with `ptr` store.
* Keep this patch, but perform both GEPs with `i64` element type to
reduce the diff. It's not clear if the scalarization caused by that type
mismatch is intentional/relevant for the original change.
Commit: 4219fb8a21c6c25d42bb2502c1a46f57a6b8045d
https://github.com/llvm/llvm-project/commit/4219fb8a21c6c25d42bb2502c1a46f57a6b8045d
Author: khaki3 <47756807+khaki3 at users.noreply.github.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/FIRToMemRef.cpp
A flang/test/Transforms/FIRToMemRef/array-coor-slice-shift.mlir
Log Message:
-----------
[flang] Fix FIRToMemRef index computation for array_coor with shape_shift and slice (#186523)
When fir.array_coor carries an explicit shape_shift (non-default lower
bounds) and an explicit slice, the indices are Fortran indices rather
than 1-based section indices. The FIRToMemRef pass was unconditionally
subtracting 1 from sliced indices, which is only correct for 1-based
section indices (the embox-with-embedded-slice case).
For shape_shift + explicit slice, the correct adjustment is to subtract
the slice lower bound instead of 1. This produces proper 0-based memref
indices.
This pattern arises after the FIR inliner canonicalizes
fir.embox(shape_shift, slice) + fir.array_coor(box) into a single
fir.array_coor with explicit shape_shift and slice operands, where the
indices become Fortran indices.
Without this fix, arrays with non-default lower bounds (e.g., A(0:N) or
A(-1:N)) produce negative memref indices, writing before the array
allocation and causing a segfault.
Commit: 291923ba16ad57ce7db599a4d6af0b2936ea17a9
https://github.com/llvm/llvm-project/commit/291923ba16ad57ce7db599a4d6af0b2936ea17a9
Author: Leandro Lupori <leandro.lupori at linaro.org>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M flang/include/flang/Semantics/openmp-utils.h
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.h
M flang/lib/Semantics/openmp-utils.cpp
M flang/lib/Semantics/resolve-directives.cpp
A flang/test/Lower/OpenMP/indirect-reference-privatization.f90
M flang/test/Lower/OpenMP/parallel-lastprivate-clause-scalar.f90
R flang/test/Lower/OpenMP/privatize_predetermined_only_when_defined_by_eval.f90
Log Message:
-----------
[flang][OpenMP] Privatize indirectly referenced symbols (#187097)
Symbols that may be referenced indirectly by lastprivate or linear
DSAs in nested constructs must not have their privatization skipped
in the enclosing context. This avoids updates to the wrong symbols.
This is needed to unblock PRs that fix #170784.
Fixes #179345
Commit: b32d078782c5e05d9a54ada1ba257edd31e28fe6
https://github.com/llvm/llvm-project/commit/b32d078782c5e05d9a54ada1ba257edd31e28fe6
Author: Mark Danial <mark.danial at ibm.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M mlir/test/Dialect/Builtin/Bytecode/builtin_fixed.mlir
Log Message:
-----------
[AIX] XFAIL mlir builtin test on big endian AIX [NFC] (#187365)
Similar to https://github.com/llvm/llvm-project/pull/186305
Commit: 87bab31c27dee5ec69022df3beaa018744c4e8d1
https://github.com/llvm/llvm-project/commit/87bab31c27dee5ec69022df3beaa018744c4e8d1
Author: Pranav Bhandarkar <pranav.bhandarkar at amd.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp
A flang/test/HLFIR/inline-hlfir-assign-allocatable-expr.fir
Log Message:
-----------
[Flang] - Add optional inlining of allocatable assignments with hlfir.expr RHS (#186880)
Add support for inlining hlfir.assign operations where the LHS is an
allocatable and the RHS is an `hlfir.expr` (e.g., from
`hlfir.elemental`). Since `hlfir.expr` values cannot alias with memory
locations, these assignments can be safely inlined without alias
analysis.
The optimization is controlled by the
-inline-hlfir-allocatable-expr-assign flag:
fir-opt -inline-hlfir-allocatable-expr-assign --inline-hlfir-assign
file.fir
flang -mmlir -inline-hlfir-allocatable-expr-assign file.f90
The generated code uses `fir::factory::genReallocIfNeeded` to properly
handle Fortran allocatable assignment semantics (F2018 10.2.1.3):
- If not allocated: allocate with RHS shape
- If allocated with same shape: reuse existing allocation
- If allocated with different shape: reallocate
This is motivated by the increased link time that I am seeing when
`__FortranAAssign` is called from the user code. The details of the
problem are documented in
https://github.com/llvm/llvm-project/issues/187720
Commit: dc4073fbe7ffb8a1886a09029fc1572cdebc1847
https://github.com/llvm/llvm-project/commit/dc4073fbe7ffb8a1886a09029fc1572cdebc1847
Author: google-llvm-bazel-bot <google-bazel-bot at google.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 239ca11 (#188083)
This fixes 239ca11a55b40ce12b21bc47e45cb4065d1cc3d4.
Commit: d2e70414b685a31021b7d5f84661ca5a59c33727
https://github.com/llvm/llvm-project/commit/d2e70414b685a31021b7d5f84661ca5a59c33727
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.live.mask.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for live_mask (#187833)
Commit: e672e88a966c939bfd32d5619cea496ad67bf338
https://github.com/llvm/llvm-project/commit/e672e88a966c939bfd32d5619cea496ad67bf338
Author: idubinov <igor.dubinov at amd.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/test/CodeGen/SPIRV/transcoding/BuildNDRange.ll
R llvm/test/CodeGen/SPIRV/transcoding/BuildNDRange_2.ll
A llvm/test/CodeGen/SPIRV/transcoding/BuildNDRange_no_sret.ll
Log Message:
-----------
[SPIRV] Fix OpBuildNDRange (#186153)
- Fix buildNDRange according to OpenCL and SPIRV specs.
- Fix tablegen SPIRV builtins for ndrange_* functions: despite of OpenCL
spec, the real call has additional first argument - structure return,
changed min and max num arguments accordingly.
- Update test, add checks, combined with BuildNDRange_2
Commit: 412aaeb739eac354110ea4a5dfc66e14f7c90f94
https://github.com/llvm/llvm-project/commit/412aaeb739eac354110ea4a5dfc66e14f7c90f94
Author: Henrich Lauko <xlauko at mail.muni.cz>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/test/CIR/Transforms/bit.cir
Log Message:
-----------
[CIR] Add Involution trait to BitReverseOp and ByteSwapOp (#187862)
bitreverse(bitreverse(x)) == x and byte_swap(byte_swap(x)) == x are
mathematical involutions.
This adds MLIR Involution trait to CIR opetation, it encodes this
property and automatically folds away the outer application when an op's
input is produced by the same op type.
Commit: 89503bda38f77a4567902d43428a6e6a84c551fa
https://github.com/llvm/llvm-project/commit/89503bda38f77a4567902d43428a6e6a84c551fa
Author: Austin Kerbow <Austin.Kerbow at amd.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
Log Message:
-----------
[AMDGPU] Add structural stall heuristic to scheduling strategies (#169617)
Implements a structural stall heuristic that considers both resource
hazards and latency constraints when selecting instructions. In coexec,
this changes the pending queue from a binary “not ready to issue”
distinction into part of a unified candidate comparison. Pending
instructions still identify structural stalls in the current cycle, but
they are now evaluated directly against available instructions by stall
cost, making the heuristics both more intuitive and more expressive.
- Add getStructuralStallCycles() to GCNSchedStrategy that computes the
number of cycles an instruction must wait due to:
- Resource conflicts on unbuffered resources (from the SchedModel)
- Sequence-dependent hazards (from GCNHazardRecognizer)
- Add getHazardWaitStates() to GCNHazardRecognizer that returns the
number
of wait states until all hazards for an instruction are resolved,
providing cycle-accurate hazard information for scheduling heuristics.
Commit: 729480c4aec6ea8a18149fd3c73de57aaa677d2a
https://github.com/llvm/llvm-project/commit/729480c4aec6ea8a18149fd3c73de57aaa677d2a
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
A clang/test/CIR/CodeGen/cleanup-scope-return-in-loop.cpp
A clang/test/CIR/CodeGen/new-array-size-conv.cpp
Log Message:
-----------
[CIR] Generalize cxx alloc new size handling (#187790)
The non-constant size handling in `emitCXXNewAllocSize` was making the
incorrect assumption that the default behavior of the size value being
explicitly cast to size_t would be the only behavior we'd see. This is
actually only true with C++14 and later. To properly handle earlier
standards, we need the more robust checking that classic codegen does in
the equivalent function. This change adds that handling.
Assisted-by: Cursor / claude-4.6-opus-high
Commit: b75222caf3e3247f6cfa5b243619d776dd5b5863
https://github.com/llvm/llvm-project/commit/b75222caf3e3247f6cfa5b243619d776dd5b5863
Author: Amy Kwan <amy.kwan1 at ibm.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M clang/lib/Driver/CMakeLists.txt
Log Message:
-----------
[clang][Driver][CMake] Link pthread when available to fix shared-lib link errors.
Commit: 0ae0ee03619a0db2f8d754d2ea049d2a55e656f7
https://github.com/llvm/llvm-project/commit/0ae0ee03619a0db2f8d754d2ea049d2a55e656f7
Author: kwyatt-ext <kwyatt.external at hpe.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M flang/docs/Extensions.md
Log Message:
-----------
[flang] Adding a new extension that was noticed to be intentionally in the code. (#182891)
The flang compiler intentionally issues a warning on duplicate
prefix-specs for procedures. This is not consistent with the standard
which says "shall contain at most one of each". Other tested compilers
correctly issue an error.
It is safe to leave this as a warning. It can be turned into an error
condition by using the "-Werror" flag.
However, it should be noted in the Extensions document, similar to the
mention of the SAVE attribute.
Commit: 0c1013bfd4144b3d2f91df193f8da4e08c63998c
https://github.com/llvm/llvm-project/commit/0c1013bfd4144b3d2f91df193f8da4e08c63998c
Author: vporpo <vasileios.porpodas at amd.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/include/llvm/IR/Instructions.h
M llvm/lib/IR/Instructions.cpp
Log Message:
-----------
[IR][NFC] Rename UncondBrInst 'IfTrue' argument to 'Target' (#187631)
Follow-up on @slackito's suggestion about the naming of the variable and
discussion with @aengelke in #187196
Commit: e38e87dbb0f3ac4897cf307867b6a3c8c9c7aa35
https://github.com/llvm/llvm-project/commit/e38e87dbb0f3ac4897cf307867b6a3c8c9c7aa35
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
Log Message:
-----------
[LoongArch] Fix -Wunused-variable in c4b01ec20d3e845d348b0b005102b1301a8550ca
This variable was only used in assertions which was causing warnings in
release+noasserts builds.
Commit: 9acfa56d8f23659a568715d502c64f96735bffea
https://github.com/llvm/llvm-project/commit/9acfa56d8f23659a568715d502c64f96735bffea
Author: Owen Anderson <resistor at mac.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
A llvm/test/Transforms/Coroutines/coro-split-addrspace.ll
Log Message:
-----------
[Coro] Preserve program address spaces correctly in CoroSplit. (#188002)
Commit: f7d5e593d38a83bcd9ccaff6fbc1cdbca623fdb2
https://github.com/llvm/llvm-project/commit/f7d5e593d38a83bcd9ccaff6fbc1cdbca623fdb2
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/configuration.py
M lldb/packages/Python/lldbsuite/test/decorators.py
M lldb/packages/Python/lldbsuite/test/dotest.py
M lldb/packages/Python/lldbsuite/test/dotest_args.py
M lldb/test/API/lit.cfg.py
M lldb/test/API/lit.site.cfg.py.in
M lldb/test/CMakeLists.txt
M lldb/utils/lldb-dotest/CMakeLists.txt
M lldb/utils/lldb-dotest/lldb-dotest.in
Log Message:
-----------
[lldb] Check for arm64e debugserver in skipUnlessArm64eSupported (#188082)
Explicitly check whether we are building debugserver for arm64e. To
debug an arm64e binary, debugserver itself needs to be an arm64e
process.
This PR eliminates the possibility of configuring LLDB with Right now,
it's possible to configure CMake with
`LLDB_ENABLE_ARM64E_DEBUGSERVER=Off` and the decorator wouldn't account
for that.
Commit: 205187c5cfe318109deb215583edd5434f69c487
https://github.com/llvm/llvm-project/commit/205187c5cfe318109deb215583edd5434f69c487
Author: Susan Tan (ス-ザン タン) <zujunt at nvidia.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M flang/lib/Optimizer/OpenACC/Transforms/ACCDeclareActionConversion.cpp
M flang/test/Fir/OpenACC/declare-action-conversion.fir
Log Message:
-----------
[openacc][flang] full support to handle allocatable/pointer runtime declare-action calls in ACCDeclareActionConversion (#188055)
Supported before: `fir.store`, `fir.box_addr`, and `fir.call` only for
PointerAllocate/PointerDeallocate.
Added now: fir.call support for PointerAllocateSource,
PointerDeallocatePolymorphic, AllocatableAllocate,
AllocatableAllocateSource, AllocatableDeallocate,
AllocatableDeallocatePolymorphic (found in
flang/include/flang/Runtime/allocatable.h).
Commit: 9096c9cda3df4d09c9c6e4efa1a07a232a9ac8f8
https://github.com/llvm/llvm-project/commit/9096c9cda3df4d09c9c6e4efa1a07a232a9ac8f8
Author: Afonso Rafael (Gafanhoto) <afonsorafael at sapo.pt>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
M llvm/test/Transforms/LoopFusion/da_separate_loops.ll
Log Message:
-----------
[LoopFusion] Remove the InvalidDependencies duplicates (#187744)
If the function dependencesAllowFusion returns false, in fuseCandidates
the reportLoopFusion function is used to increment InvalidDependencies
and to emit a OptimizationRemarkMissed. If both dependencesAllowFusion
and reportLoopFusion increment InvalidDependencies, statistics will
appear duplicated
Commit: 3124cb3fe779ab65aa1f7b1e875d4efd62852757
https://github.com/llvm/llvm-project/commit/3124cb3fe779ab65aa1f7b1e875d4efd62852757
Author: Alireza Torabian <alireza.torabian at huawei.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/test/Analysis/DependenceAnalysis/SameSDLoops.ll
Log Message:
-----------
[DA] Bug fix regarding the SameSD levels (#188098)
SCEV isKnownPredicate may crash if the expressions are involved with
different loops. To verify if two loops have the same iteration space,
we do not need to use the SCEV apis, and it can be done by the equality
check.
Moreover, no pass (not even loop fusion) requires to check SameSD levels
for more than one level. In this patch, we limit the analysis of SameSD
levels to only one level after the common levels.
Commit: 22977fd99ed9f580bbc3bbe3c43c1224f393d348
https://github.com/llvm/llvm-project/commit/22977fd99ed9f580bbc3bbe3c43c1224f393d348
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.permute.ll
Log Message:
-----------
[AMDGPU][NFC] Update permute tests to use auto-generated checks (#188107)
Also add global-isel run line.
Commit: 2f1e0d14f40da09379b489ba4e78fbfd8794f68e
https://github.com/llvm/llvm-project/commit/2f1e0d14f40da09379b489ba4e78fbfd8794f68e
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/X86/transform-narrow-interleave-to-widen-memory-epilogue-vec.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
Log Message:
-----------
[LV] Add additional epilogue vector tests.
Add additional epilogue vectorization tests for
* https://github.com/llvm/llvm-project/issues/187323
* https://github.com/llvm/llvm-project/issues/185345
Commit: c0634cbb07149c8e8fea428c654774cf06be764a
https://github.com/llvm/llvm-project/commit/c0634cbb07149c8e8fea428c654774cf06be764a
Author: Zhen Wang <37195552+wangzpgi at users.noreply.github.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M flang-rt/lib/cuda/registration.cpp
M flang/include/flang/Runtime/CUDA/registration.h
Log Message:
-----------
[flang][cuda] Add CUFRegisterManagedVariable runtime entry for __cudaRegisterManagedVar (#188124)
Add CUFRegisterManagedVariable runtime wrapper in flang-rt that calls
__cudaRegisterManagedVar.
This is preparation for supporting non-allocatable managed variables.
No functional change -- nothing calls this yet.
Commit: a235d96e48e47b33d5772f73661a3d178c11777b
https://github.com/llvm/llvm-project/commit/a235d96e48e47b33d5772f73661a3d178c11777b
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/test/Instrumentation/AddressSanitizer/remove-memory-effects.ll
Log Message:
-----------
[test][ASan] Precommit test for #187794 (#188112)
Commit: fe03749f08f86e8cf94132bd9155a68637657a8c
https://github.com/llvm/llvm-project/commit/fe03749f08f86e8cf94132bd9155a68637657a8c
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/Cuda.cpp
Log Message:
-----------
[Clang] Do not emit multi-gpu warning if they are all the same (#185490)
Summary:
This warning exists because if you do `-mcpu=native` in some contexts it
may not be obvious which GPU you get. But if they are all the same then
it really don't make a difference since we just pass the first one to
`-mcpu` anyway. Relax this so it doesn't annoyingly warn on machines
with more than one of the same GPU.
---------
Co-authored-by: Jacob Lambert <jacob.lambert at amd.com>
Commit: 53e3ed82f690aee90d74f5459fbbf5bb7ba21980
https://github.com/llvm/llvm-project/commit/53e3ed82f690aee90d74f5459fbbf5bb7ba21980
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/utils/gn/secondary/lldb/test/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn
Log Message:
-----------
[gn build] Port commits (#188129)
f7d5e593d38a
b2edc0a3f8a5
3e4efe3ed4a2
Commit: 2bee9585993506a06765b06f8cc83f1e219c45ee
https://github.com/llvm/llvm-project/commit/2bee9585993506a06765b06f8cc83f1e219c45ee
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
Log Message:
-----------
[AMDGPU][NFC] Update test to use update_llc_test_checks (#188102)
Also add globalisel run lines.
Precommit test for https://github.com/llvm/llvm-project/pull/187834.
Commit: 599d74fdc3cee5fa1ed84d6e10830f9aa5fe6b53
https://github.com/llvm/llvm-project/commit/599d74fdc3cee5fa1ed84d6e10830f9aa5fe6b53
Author: lntue <lntue at google.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M libc/src/__support/math/CMakeLists.txt
M libc/src/__support/math/acoshf_utils.h
M libc/test/src/math/acoshf_test.cpp
M libc/test/src/math/asinhf_test.cpp
M libc/test/src/math/atanhf_test.cpp
Log Message:
-----------
[libc][math] Reduce memory usage for single precision inverse hyperbolic functions for LIBC_MATH_HAS_SMALL_TABLES option. (#188110)
Commit: bcfe1e94d3f062139aae009e44ae458f69cf2df2
https://github.com/llvm/llvm-project/commit/bcfe1e94d3f062139aae009e44ae458f69cf2df2
Author: Deric C. <cheung.deric at gmail.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M clang/lib/Sema/SemaCast.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/CodeGenHLSL/BasicFeatures/AggregateSplatCast.hlsl
Log Message:
-----------
[HLSL] Allow 1x1 matrices to be splatted like scalars (#188119)
Fixes #186859 by allowing 1x1 matrices to be splatted like the scalar
and vec1 cases.
Assisted-by: GitHub Copilot (powered by Claude Opus 4.6)
Commit: 20e863de1373fd255f77afcd21ea4b90d47f838e
https://github.com/llvm/llvm-project/commit/20e863de1373fd255f77afcd21ea4b90d47f838e
Author: google-llvm-bazel-bot <google-bazel-bot at google.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 599d74f (#188138)
This fixes 599d74fdc3cee5fa1ed84d6e10830f9aa5fe6b53.
Commit: d194afe062bc2a27f4664590549990e90d27c6a1
https://github.com/llvm/llvm-project/commit/d194afe062bc2a27f4664590549990e90d27c6a1
Author: Théo Degioanni <tdegioanni at nvidia.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M mlir/include/mlir/Transforms/Passes.td
Log Message:
-----------
[MLIR] [Mem2Reg] [NFC] Update pass documentation (#188140)
In #185036, we added region control flow support but forgot to update
the pass declaration documentation. This NFC addresses this.
Commit: 77fb848894cc0d6b3027c6e82e10d32069fc6430
https://github.com/llvm/llvm-project/commit/77fb848894cc0d6b3027c6e82e10d32069fc6430
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-factors.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-widen-inductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/f128-fmuladd-reduction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-runtime-checks.ll
M llvm/test/Transforms/LoopVectorize/AArch64/intrinsiccost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
M llvm/test/Transforms/LoopVectorize/AArch64/neon-inloop-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub-epilogue-vec.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/exit-branch-cost.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/X86/conversion-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/epilog-vectorization-inductions.ll
M llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll
M llvm/test/Transforms/LoopVectorize/X86/gather_scatter.ll
M llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
M llvm/test/Transforms/LoopVectorize/X86/scatter_crash.ll
M llvm/test/Transforms/LoopVectorize/X86/transform-narrow-interleave-to-widen-memory-epilogue-vec.ll
M llvm/test/Transforms/LoopVectorize/X86/transform-narrow-interleave-to-widen-memory.ll
M llvm/test/Transforms/LoopVectorize/epilog-iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-any-of-reductions.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
M llvm/test/Transforms/PhaseOrdering/X86/pr48844-br-to-switch-vectorization.ll
Log Message:
-----------
Reapply "[LV] Simplify and unify resume value handling for epilogue vec." (#187504)
This reverts commit cdaf29f84dd0abbd1f961982799059c92d76625b.
This version skips removeBranchOnConst when vectorizing the epilogue, as
it may trigger folds that remove the resume phi used as resume value
from the epilogue.
This fixes https://github.com/llvm/llvm-project/issues/187323.
Original message:
This patch tries to drastically simplify resume value handling for the
scalar loop when vectorizing the epilogue.
It uses a simpler, uniform approach for updating all resume values in
the scalar loop:
1. Create ResumeForEpilogue recipes for all scalar resume phis in the
main loop (the epilogue plan will have exactly the same scalar resume
phis, in exactly the same order)
2. Update ::execute for ResumeForEpilogue to set the underlying value
when executing. This is not super clean, but allows easy lookup of the
generated IR value when we update the resume phis in the epilogue. Once
we connect the 2 plans together explicitly, this can be removed.
3. Use the list of ResumeForEpilogue VPInstructions from the main loop
to update the resume/bypass values from the epilogue.
This simplifies the code quite a bit, makes it more robust (should fix
https://github.com/llvm/llvm-project/issues/179407) and also fixes a
mis-compile in the existing tests (see change in
llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub-epilogue-vec.ll,
where previously we would incorrectly resume using the start value when
the epilogue iteration check failed)
In some cases, we get simpler code, due to additional CSE, in some cases
the induction end value computations get moved from the epilogue
iteration check to the vector preheader. We could try to sink the
instructions as cleanup, but it is probably not worth the trouble.
Fixes https://github.com/llvm/llvm-project/issues/179407.
PR for recommit https://github.com/llvm/llvm-project/pull/188134
Commit: 4f32ea35f5956c4a2fd93d1c9416421c6f7f71c5
https://github.com/llvm/llvm-project/commit/4f32ea35f5956c4a2fd93d1c9416421c6f7f71c5
Author: Zhen Wang <37195552+wangzpgi at users.noreply.github.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M flang-rt/lib/cuda/registration.cpp
M flang/include/flang/Runtime/CUDA/registration.h
Log Message:
-----------
[flang][cuda] Fix const mismatch in CUFRegisterManagedVariable for __cudaRegisterManagedVar (#188142)
Change varName parameter from `const char *` to `char *` in
CUFRegisterManagedVariable to match the CUDA runtime API signature of
__cudaRegisterManagedVar, which declares deviceAddress as `char *`.
Commit: b4f50cfd4a3a086db3f88271c9595056a877ef90
https://github.com/llvm/llvm-project/commit/b4f50cfd4a3a086db3f88271c9595056a877ef90
Author: Muhammad Bassiouni <60100307+bassiounix at users.noreply.github.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libc/src/__support/CPP/bit.h
M libc/src/__support/FPUtil/NearestIntegerOperations.h
M libc/src/__support/FPUtil/bfloat16.h
M libc/src/__support/FPUtil/comparison_operations.h
M libc/src/__support/FPUtil/generic/add_sub.h
M libc/src/__support/FPUtil/generic/div.h
M libc/src/__support/FPUtil/generic/mul.h
M libc/src/__support/FPUtil/rounding_mode.h
M libc/src/__support/math/ceil.h
M libc/src/__support/math/ceilbf16.h
M libc/src/__support/math/ceilf.h
M libc/src/__support/math/ceilf128.h
M libc/src/__support/math/ceilf16.h
M libc/src/__support/math/ceill.h
M libc/test/shared/CMakeLists.txt
A libc/test/shared/shared_math_constexpr_test.cpp
M libc/test/shared/shared_math_test.cpp
Log Message:
-----------
[libc][math] Qualify ceil functions to constexpr (#184948)
Commit: 08070b75f2a2643ab5eee04e2a6a6e37d006c25e
https://github.com/llvm/llvm-project/commit/08070b75f2a2643ab5eee04e2a6a6e37d006c25e
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M flang/include/flang/Evaluate/tools.h
M flang/lib/Evaluate/tools.cpp
M flang/lib/Semantics/check-cuda.cpp
A flang/test/Lower/CUDA/cuda-data-transfer-implicit.cuf
M flang/test/Lower/CUDA/cuda-data-transfer.cuf
M flang/test/Lower/CUDA/cuda-managed.cuf
Log Message:
-----------
[flang][cuda] Do not check for implicit transfer on managed symbols (#188143)
Avoid to trigger a semantic error when only managed symbols are on the
right hand side.
Commit: 5624cce586c74ec7cfcbd0243f65cb1870677af7
https://github.com/llvm/llvm-project/commit/5624cce586c74ec7cfcbd0243f65cb1870677af7
Author: Ruiling, Song <ruiling.song at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
A llvm/test/CodeGen/AMDGPU/promote-alloca-delay-value-replacement.ll
Log Message:
-----------
AMDGPU: Delay value replacement in PromoteAlloca (#186944)
When we do alloca promotion, there might be cross references to the
values derived from different allocas. RAUW immediately during promotion
may fail to update the values cached in the AllocaAnalysis structure.
Solving the problem by postpone the value replacement, and also the
value deletion as well to make this possible.
Commit: 99a4d78bef28fc0a32e8be24a560ee26f459925d
https://github.com/llvm/llvm-project/commit/99a4d78bef28fc0a32e8be24a560ee26f459925d
Author: Wenju He <wenju.he at intel.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libclc/clc/include/clc/integer/gentype.inc
M libclc/clc/include/clc/math/gentype.inc
Log Message:
-----------
[libclc][NFC] Simplify __CLC_GENTYPE/__CLC_U_GENTYPE/__CLC_S_GENTYPE define in gentype.inc (#188027)
Reduce macro re-definition overhead.
Commit: 0e5e434f999ba0b9011cd30b086512634e355d99
https://github.com/llvm/llvm-project/commit/0e5e434f999ba0b9011cd30b086512634e355d99
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/test/Dialect/Affine/ops.mlir
Log Message:
-----------
[affine] Support xori/maxnumf/minnumf reduction types. (#184450)
This is a follow-up on #163310, which supported the above reduction
kinds, but did not update affine.parallel verification code.
Commit: 6a8a1008b56c8a3532b19551292e71216f0ea03e
https://github.com/llvm/llvm-project/commit/6a8a1008b56c8a3532b19551292e71216f0ea03e
Author: Midhunesh <midhunesh.p at ibm.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M compiler-rt/cmake/base-config-ix.cmake
Log Message:
-----------
[compiler-rt] Error only if sanitizer builds are enabled (#187944)
This fix is to error out only if sanitizer builds are enabled as opposed
to forcing flang to use an option or install the development package.
Commit: 7fc3d6edef2fe3ce799bfc7bc31f46ed68d35e15
https://github.com/llvm/llvm-project/commit/7fc3d6edef2fe3ce799bfc7bc31f46ed68d35e15
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M llvm/include/llvm/ADT/PointerUnion.h
Log Message:
-----------
[llvm][ADT] Refactor PointerUnion to use PunnedPointer. NFC. (#187950)
Replace `PointerIntPair`-based storage with raw `PunnedPointer<void*>`
and explicit tag encoding. The bit layout stay identical. Use constexpr
functions (`minBits`, `tagBits`, `tagShift`) whose bodies are only
instantiated when called, for incomplete-type compatibility
The goal is to prepare `PointerUnion` for future extension to support
variable-length encoding and allow for more variants than with simple
tags, which will require direct bit manipulation not possible with
`PointerIntPair`.
I benchmarked this with https://github.com/llvm/llvm-project/pull/187874
and the performance is identical on my system.
---------
Co-authored-by: Claude Opus 4.6 (1M context) <noreply at anthropic.com>
Commit: 79ae4c741940707c5cb44223e25f248c9bb56552
https://github.com/llvm/llvm-project/commit/79ae4c741940707c5cb44223e25f248c9bb56552
Author: Haohai Wen <haohai.wen at intel.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Object/ELF.cpp
Log Message:
-----------
[Object] Normalize BBAddrMap decode address types in ELF (#187962)
This is part of patches to port BBAddrMap to COFF.
DataExtractor::getAddress reads 4 or 8 bytes according to AddressSize and
returns a uint64_t container value. This code path already sets AddressSize
from ELFT::Is64Bits and stores range/function addresses as uint64_t.
Replace temporary uintX_t/unsigned values in this decoder path with uint64_t
and remove the redundant cast from getAddress(). This preserves behavior for
ELF32/ELF64 inputs.
This is a preparatory step for extracting a format-agnostic BBAddrMap decoder.
Commit: d734ead1328675bf644620cc524c8dab10344815
https://github.com/llvm/llvm-project/commit/d734ead1328675bf644620cc524c8dab10344815
Author: LeeYoungJoon <dog3hk.dev at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/PointerArithmeticOnPolymorphicObjectCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/bugprone/pointer-arithmetic-on-polymorphic-object-all.cpp
Log Message:
-----------
[clang-tidy] Fix false positive in cert-ctr56-cpp (PointerArithmeticOnPolymorphicObjectCheck) (#187452)
## Summary
This change adds `unless(isInstantiationDependent())` to the
`ArraySubscript` matcher.
## Motivation
In template code, some array subscript expressions are not fully
resolved yet.
Because of this, the matcher may treat them incorrectly and produce
false positives.
## Change
This patch skips instantiation-dependent expressions in templates.
It helps the matcher work only on resolved expressions.
Closes https://github.com/llvm/llvm-project/issues/187009.
Commit: 74ca05748f657a39ed53ef50a9a1f8e972f53959
https://github.com/llvm/llvm-project/commit/74ca05748f657a39ed53ef50a9a1f8e972f53959
Author: Jan Voung <jvoung at google.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M clang/lib/Analysis/FlowSensitive/Models/UncheckedOptionalAccessModel.cpp
M clang/unittests/Analysis/FlowSensitive/MockHeaders.cpp
M clang/unittests/Analysis/FlowSensitive/UncheckedOptionalAccessModelTest.cpp
Log Message:
-----------
[clang][dataflow] Fix bugprone-unchecked-optional-access for recent changes to libcxx (#188044)
Fix for https://github.com/llvm/llvm-project/issues/187788
- When checking the receiver with an UncheckedDerivedToBase cast, just
check each component of the chain if we've hit the public optional
class, rather than rely on public vs private/protected inheritance. This
covers the case when the class derives from optional.
- or check if the SubExpr of the cast is already the public optional
type (when not deriving from optional -- since you won't see this first
layer in the cast chain).
See comment about why there is public inheritance to a private base
class at the moment:
https://github.com/llvm/llvm-project/issues/187788#issuecomment-4106543794
The performance doesn't seem much different in several benchmarks.
Perhaps because we first see if the method name matches, which filters a
bunch out.
Also, make the operator* and operator-> calls do this search, since
https://github.com/llvm/llvm-project/pull/185252 moved the methods to
the internal base class.
Update the test mock headers slightly to reflect the operator* and
operator-> change.
Commit: 494b98236fc766b21657bb10b0b9787c5f40cdd6
https://github.com/llvm/llvm-project/commit/494b98236fc766b21657bb10b0b9787c5f40cdd6
Author: Elvis Wang <elvis.wang at sifive.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
Log Message:
-----------
[TargetLowering][RISCV] Using index type for step vector in expandVectorFindLastActive (#187984)
This patch change the type of the step vector lowered from
`expandVectorFindLastActive` from `e8` to the index type of the target
machine.
This can help the index out of bound issue when the VLEN is large.
Note that after this patch, there are still some issue in
expandVectorFindLastActive.
Commit: 6c6b4c154c49eeedc5c0a7e460bf529a73bbfcd6
https://github.com/llvm/llvm-project/commit/6c6b4c154c49eeedc5c0a7e460bf529a73bbfcd6
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M clang/lib/CodeGen/Targets/RISCV.cpp
M clang/test/CodeGen/RISCV/abi-empty-structs.c
M clang/test/CodeGen/RISCV/bfloat-abi.c
M clang/test/CodeGen/RISCV/riscv32-abi.c
M clang/test/CodeGen/RISCV/riscv64-abi.c
Log Message:
-----------
[RISCV] Disable rounding of aggregate return/arguments to iXLen. (#184736)
If the type is rounded to iXLen, an additional zext instruction is
generated. For example, https://godbolt.org/z/bG7vG4dvM
Commit: caf619642a6dbb216969a9450d33dbac5a8d30df
https://github.com/llvm/llvm-project/commit/caf619642a6dbb216969a9450d33dbac5a8d30df
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang/lib/DependencyScanning/DependencyScannerImpl.cpp
A clang/test/ClangScanDeps/p1689-suppress-warnings.cppm
Log Message:
-----------
[ClangScanDeps] Do not emit warning for P1689 format (#186966)
Close https://github.com/llvm/llvm-project/issues/185394
This is only for P1689 format as ClangScanDeps/optimize-vfs-pch.m will
check for warning message. I'll leave this to people who want to change
that.
Commit: a2c6b34193fbcaf76d48d2896c816adb9ee45ffe
https://github.com/llvm/llvm-project/commit/a2c6b34193fbcaf76d48d2896c816adb9ee45ffe
Author: hanbeom <kese111 at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
M llvm/test/CodeGen/WebAssembly/load-ext.ll
Log Message:
-----------
[WebAssembly][FastISel] Fold i64 extension chains into widened loads (#187934)
FastISel can already fold some sign- and zero-extending loads, but a
number of i64 extension patterns still leave redundant instructions
behind.
This patch series extends load folding to recognize several such cases,
including:
- promoted sign-extension chains
- copy + i64.extend_i32_{u,s} chains
- AND-based zero-extension chains
- shift-based sign-extension chains
When these patterns originate from narrow integer loads, fold them
directly into widened i64 loads instead of materializing intermediate
i32 loads followed by redundant i64 extends.
Fixes #179672
Commit: fd11cf430e5a9fd11f93bdcc929a1ce8dfa60f37
https://github.com/llvm/llvm-project/commit/fd11cf430e5a9fd11f93bdcc929a1ce8dfa60f37
Author: John Paul Jepko <john.jepko at ericsson.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/Decl.h
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/test/C/C2y/n3622.c
A clang/test/Sema/Inputs/warn-unused-but-set-static-global-header.h
A clang/test/Sema/warn-unused-but-set-static-global.c
A clang/test/Sema/warn-unused-but-set-static-global.cpp
M clang/test/SemaCXX/warn-variable-not-needed.cpp
Log Message:
-----------
[clang] Extend -Wunused-but-set-variable to static globals (#178342)
This PR extends the capability of -Wunused-but-set-variable to track and
diagnose static global variables that are assigned values within a
function but whose values are never used. This change complements
-Wunused-variable, which detects static globals that are neither set nor
used.
I created this change with the help of claude for some initial guidance.
Fixes #148361
Commit: c1a45ffc84eee23c7c330ea16eb08e9cf8fd623e
https://github.com/llvm/llvm-project/commit/c1a45ffc84eee23c7c330ea16eb08e9cf8fd623e
Author: Owen Pan <owenpiano at gmail.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M clang/docs/ClangFormatStyleOptions.rst
M clang/include/clang/Format/Format.h
Log Message:
-----------
[clang-format][doc] Add a note to OneLineFormatOffRegex option
Closes #184639
Commit: dee01fbf2c401f7ff3bad8341c2ace6e192915cf
https://github.com/llvm/llvm-project/commit/dee01fbf2c401f7ff3bad8341c2ace6e192915cf
Author: owenca <owenpiano at gmail.com>
Date: 2026-03-23 (Mon, 23 Mar 2026)
Changed paths:
M clang/Maintainers.md
Log Message:
-----------
Step down as clang-format maintainer (#187910)
I'm stepping down as clang-format maintainer and nominating
@HazardyKnusperkeks to take my place.
Commit: bd597259a8543a5705cbdb985612de573e5cb962
https://github.com/llvm/llvm-project/commit/bd597259a8543a5705cbdb985612de573e5cb962
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/test/SemaCXX/cxx2b-deducing-this.cpp
M clang/test/SemaTemplate/stack-exhaustion.cpp
M clang/utils/TableGen/ClangOpcodesEmitter.cpp
Log Message:
-----------
[clang][bytecode] Revert tailcalls (#188169)
This _still_ causes problems on aarch64+msan, even when not using
tailcalls at all.
Reverts #173756
Commit: 704c60fe9110256d2698d8e56b8c44ec5d1e733f
https://github.com/llvm/llvm-project/commit/704c60fe9110256d2698d8e56b8c44ec5d1e733f
Author: Dominique Fuchs <df at 0x9d.net>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang/lib/Tooling/InterpolatingCompilationDatabase.cpp
M clang/unittests/Tooling/CompilationDatabaseTest.cpp
Log Message:
-----------
[clang][Tooling] Preserve -std flag when transferring compile commands across same-family language (#184560)
Previously, transfering a compile command from e.g. an ObjC++ source
(`.mm) to a C++ header (`.hh`) would drop `-std=c++20` because they
were different languages.
Fixes https://github.com/clangd/clangd/issues/1014
Fixes https://github.com/clangd/clangd/issues/2613
Signed-off-by: Dominique Fuchs <df at 0x9d.net>
Commit: 4444f517e99690c1221f906a8c4c4dec1333cb75
https://github.com/llvm/llvm-project/commit/4444f517e99690c1221f906a8c4c4dec1333cb75
Author: pkarveti <quic_pkarveti at quicinc.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonLoadStoreWidening.cpp
A llvm/test/CodeGen/Hexagon/load-widen-addasl.mir
A llvm/test/CodeGen/Hexagon/store-widen-addasl.mir
Log Message:
-----------
[Hexagon] Optimize load/store instruction during widening (#186962)
This change enhances the Hexagon Load-Store Widening pass to recognize
and optimize a specific pattern involving the S2_addasl_rrri
instruction. When widening loads/stores, the pass now detects cases
where the base register is defined by an S2_addasl_rrri instruction and
combines the operations into a single load double/store double
instruction with register shift op, eliminating the intermediate address
calculation.
Eg, for load,
If the definition of the base register came from a addasl instruction,
we generate a
memd(Rs + Rt << #imm) instead of memd(Rs + #imm) instruction.
Transform:
%18 = S2_addasl_rrri %8, %17, 3
%19 = L2_loadri_io %18, 0
to
%19 = L4_loadrd_rr %8, %17, 3
Patch By: Pavani Karveti <pkarveti at qti.qulacomm.com>
Author: Santanu Das <santdas at qti.qualcomm.com>
Co-authored-by: quic-santdas <quic_santdas at quicinc.com>
Commit: a8b669ba6ee4ec3eb523d91deaf28ef0f8734100
https://github.com/llvm/llvm-project/commit/a8b669ba6ee4ec3eb523d91deaf28ef0f8734100
Author: Aleksandr Platonov <arcsinx45 at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang-tools-extra/Maintainers.rst
Log Message:
-----------
[clangd] Add ArcsinX as a maintainer (#187886)
To address clangd maintance problem, I'm nominating myself as a clangd
maintainer.
I'm currently actively reviewing PRs. I also participated in
clangd-related discourse discussions, subscribed to clangd issues and
PRs. For a while I plan to spend some time for PRs review in clangd.
Commit: c378b79c145a36c6c45dcedd8dc197e001a75a64
https://github.com/llvm/llvm-project/commit/c378b79c145a36c6c45dcedd8dc197e001a75a64
Author: Ruiling, Song <ruiling.song at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
R llvm/test/CodeGen/AMDGPU/promote-alloca-delay-value-replacement.ll
Log Message:
-----------
Revert "AMDGPU: Delay value replacement in PromoteAlloca (#186944)" (#188180)
This reverts commit 5624cce586c74ec7cfcbd0243f65cb1870677af7.
This is causing libclc failure. revert to fix it properly.
Commit: 85e1c641eba7628070b561089af787ed5d07ed86
https://github.com/llvm/llvm-project/commit/85e1c641eba7628070b561089af787ed5d07ed86
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/2016-07-27-loop-vec.ll
M llvm/test/Transforms/LoopVectorize/AArch64/gather-do-not-vectorize-addressing.ll
M llvm/test/Transforms/LoopVectorize/AArch64/nontemporal-load-store.ll
M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll
M llvm/test/Transforms/LoopVectorize/AArch64/pr36032.ll
M llvm/test/Transforms/LoopVectorize/AArch64/prefer-fixed-if-equal-to-scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-illegal-type.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-invalid-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-known-trip-count.ll
M llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-allowed.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-counting-down.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-loop-hint.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-not-allowed.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-prefer-flag.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-reductions-allowed.ll
M llvm/test/Transforms/LoopVectorize/Hexagon/minimum-vf.ll
M llvm/test/Transforms/LoopVectorize/LoongArch/loongarch-interleaved.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/interleave_IC.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization-profitability.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/predcost.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/vectorize-bswap.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-call.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-vfabi-attr.ll
M llvm/test/Transforms/LoopVectorize/RISCV/illegal-type.ll
M llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-interleaved.ll
M llvm/test/Transforms/LoopVectorize/Sparc/no-vectorize.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/mem-interleaving-costs-03.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/predicated-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/VE/disable_lv.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-half.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/X86/int128_no_gather.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave_short_tc.ll
M llvm/test/Transforms/LoopVectorize/X86/interleaved-accesses-use-after-free.ll
M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
M llvm/test/Transforms/LoopVectorize/X86/pr35432.ll
M llvm/test/Transforms/LoopVectorize/X86/pr54634.ll
M llvm/test/Transforms/LoopVectorize/X86/reg-usage-debug.ll
M llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
M llvm/test/Transforms/LoopVectorize/X86/tail_folding_and_assume_safety.ll
M llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll
M llvm/test/Transforms/LoopVectorize/X86/uniformshift.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-store-accesses-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-pr39099.ll
M llvm/test/Transforms/LoopVectorize/diag-missing-instr-debug-loc.ll
M llvm/test/Transforms/LoopVectorize/diag-with-hotness-info-2.ll
M llvm/test/Transforms/LoopVectorize/diag-with-hotness-info.ll
M llvm/test/Transforms/LoopVectorize/discriminator.ll
M llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-const-TC.ll
M llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-divisible-TC.ll
M llvm/test/Transforms/LoopVectorize/explicit_outer_detection.ll
M llvm/test/Transforms/LoopVectorize/explicit_outer_nonuniform_inner.ll
M llvm/test/Transforms/LoopVectorize/explicit_outer_uniform_diverg_branch.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/fix-reduction-dbg.ll
M llvm/test/Transforms/LoopVectorize/forked-pointers.ll
M llvm/test/Transforms/LoopVectorize/induction-ptrcasts.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-1.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-2.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-masked-group.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-uniform-load.ll
M llvm/test/Transforms/LoopVectorize/libcall-remark.ll
M llvm/test/Transforms/LoopVectorize/memdep-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/memdep.ll
M llvm/test/Transforms/LoopVectorize/memory-dep-remarks.ll
M llvm/test/Transforms/LoopVectorize/middle-block-dbg.ll
M llvm/test/Transforms/LoopVectorize/no_array_bounds_scalable.ll
M llvm/test/Transforms/LoopVectorize/nounroll.ll
M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll
M llvm/test/Transforms/LoopVectorize/pr30654-phiscev-sext-trunc.ll
M llvm/test/Transforms/LoopVectorize/pr31098.ll
M llvm/test/Transforms/LoopVectorize/pr33706.ll
M llvm/test/Transforms/LoopVectorize/pr35773.ll
M llvm/test/Transforms/LoopVectorize/pr38800.ll
M llvm/test/Transforms/LoopVectorize/pr39099.ll
M llvm/test/Transforms/LoopVectorize/pr51614-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/runtime-check.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-counting-down.ll
M llvm/test/Transforms/LoopVectorize/unroll-novec-memcheck-metadata.ll
M llvm/test/Transforms/LoopVectorize/vect-phiscev-sext-trunc.ll
M llvm/test/Transforms/LoopVectorize/vectorizeVFone.ll
Log Message:
-----------
[LV][NFC] Remove some unused attributes from tests (#188091)
The local_unnamed_addr and dso_local attributes add no value to any of
the tests and simply increase file size, so I've removed all instances.
Commit: 428995b49750a97fe4993aa4b2ab3de86c173481
https://github.com/llvm/llvm-project/commit/428995b49750a97fe4993aa4b2ab3de86c173481
Author: Honey Goyal <honeygoyal24 at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
A llvm/test/tools/sancov/XCOFF/lit.local.cfg
A llvm/test/tools/sancov/XCOFF/xcoff-sancov-symbols.test
M llvm/tools/sancov/sancov.cpp
Log Message:
-----------
Add XCOFF object file support in sanitizer coverage tool (#179884)
The sancov tool fails to find coverage symbols in XCOFF object files
because XCOFF uses a "." prefix for function entry point symbols. For
example, `__sanitizer_cov_trace_pc_guard appears` as
`.__sanitizer_cov_trace_pc_guard` in the symbol table.
Before this change, sancov reports:
`ERROR: __sanitizer_cov* functions not found`
This change strips the prefix "." when checking symbol names in XCOFF
files, allowing sancov to correctly identify coverage symbols.
---------
Co-authored-by: Honey Goyal <honey.goyal3 at ibm.com>
Commit: ef5658a289e24fa145663a1c22e0751d6c12991c
https://github.com/llvm/llvm-project/commit/ef5658a289e24fa145663a1c22e0751d6c12991c
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libclc/clc/lib/generic/conversion/clc_convert_float.inc
Log Message:
-----------
libclc: Simplify rtz conversion (#188137)
Commit: 31aa52086fb2208f451be9e22197ae1a63cdc4af
https://github.com/llvm/llvm-project/commit/31aa52086fb2208f451be9e22197ae1a63cdc4af
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libclc/clc/lib/generic/conversion/clc_convert_float.inc
M libclc/clc/lib/generic/conversion/clc_convert_float2float.cl
M libclc/clc/lib/generic/conversion/clc_convert_int2float.cl
Log Message:
-----------
libclc: Use nextup and nextdown in place of nextafter (#188141)
Unfortunately it seems the optimizer isn't able to clean this
up, so this is a code quality improvement.
Commit: f7fb46701a374d2a15d9e79197f21b128e249b95
https://github.com/llvm/llvm-project/commit/f7fb46701a374d2a15d9e79197f21b128e249b95
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
A llvm/test/Analysis/DependenceAnalysis/weak-crossing-siv-coeff-may-zero.ll
Log Message:
-----------
[DA] Add a test where the Weak Crossing SIV test misses dependency (NFC) (#188183)
The root cause is that the Weak Crossing SIV test assumes the
coefficients are non‑zero without verifying it.
Commit: ff68154480eccdfeaa18d87fd6d83906e93a85c1
https://github.com/llvm/llvm-project/commit/ff68154480eccdfeaa18d87fd6d83906e93a85c1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libclc/clc/lib/generic/math/clc_asin.cl
M libclc/clc/lib/generic/math/clc_asin.inc
Log Message:
-----------
libclc: Update asin (#188094)
This was originally ported from rocm device libs in
64a8e1b83e14836f97dab4d28dae498e897804e6. Update for more
recent changes.
Commit: cba948b2b93cc5d51f70f0fa0d66bc5cacef9d76
https://github.com/llvm/llvm-project/commit/cba948b2b93cc5d51f70f0fa0d66bc5cacef9d76
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
A libclc/clc/include/clc/math/clc_atan_helpers.h
A libclc/clc/include/clc/math/clc_atan_helpers_decl.inc
M libclc/clc/lib/generic/CMakeLists.txt
M libclc/clc/lib/generic/math/clc_atan.cl
M libclc/clc/lib/generic/math/clc_atan.inc
A libclc/clc/lib/generic/math/clc_atan_helpers.cl
A libclc/clc/lib/generic/math/clc_atan_helpers.inc
Log Message:
-----------
libclc: Update atan (#188095)
This was originally ported from rocm device libs in
47882923c7b48c00d6c0ea9960b5457e957093c4. Merge in more
recent changes.
Commit: 2e39b1e56025f6fad5b5f84cdf4051b4d1475ec0
https://github.com/llvm/llvm-project/commit/2e39b1e56025f6fad5b5f84cdf4051b4d1475ec0
Author: Lang Hames <lhames at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp
Log Message:
-----------
[ORC] Add a bootstrap symbols JITDylib to ExecutionSession. (#188172)
The ExecutionSession constructor now creates a "<bootstrap>" JITDylib
and populates it with the bootstrap symbols from the
ExecutorProcessControl object. This allows bootstrap symbols to be
looked up via ExecutionSession::lookup, providing greater consistency
with other JIT symbol lookups.
Commit: 32c6a53b767850183208aff8b783e6bc08f21515
https://github.com/llvm/llvm-project/commit/32c6a53b767850183208aff8b783e6bc08f21515
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libclc/clc/lib/generic/conversion/clc_convert_float.inc
M libclc/clc/lib/generic/conversion/clc_convert_float2float.cl
Log Message:
-----------
libclc: Fix -cl-denorms-are-zero for rtp and rtn conversions (#188148)
Commit: 1a5e52168c0bef0c5abecb89e9f18253f8a43dda
https://github.com/llvm/llvm-project/commit/1a5e52168c0bef0c5abecb89e9f18253f8a43dda
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libclc/clc/include/clc/math/clc_ep_decl.inc
M libclc/clc/lib/generic/math/clc_ep.inc
M libclc/clc/lib/generic/math/clc_log1p.cl
M libclc/clc/lib/generic/math/clc_log1p.inc
Log Message:
-----------
libclc: Update log1p (#188186)
Commit: d1b9b4c5488f051a84669b2f8e4b038f49ba4c22
https://github.com/llvm/llvm-project/commit/d1b9b4c5488f051a84669b2f8e4b038f49ba4c22
Author: Fangrui Song <i at maskray.me>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Core/BinaryEmitter.cpp
M bolt/lib/Passes/AsmDump.cpp
M llvm/include/llvm/MC/MCELFStreamer.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/MC/MCWinCOFFStreamer.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/MC/MCELFStreamer.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/MC/MCWinCOFFStreamer.cpp
M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/tools/llvm-ml/Disassembler.cpp
M llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp
M llvm/unittests/MC/DwarfLineTableHeaders.cpp
Log Message:
-----------
[MC] Remove unused NoExecStack parameter from MCStreamer::initSections. NFC (#188184)
Unused after commit 34bc5d580b73c0ca79653bb03e5c50419be2c634
Commit: fbddf80156a831179d5b12c213721d2368704776
https://github.com/llvm/llvm-project/commit/fbddf80156a831179d5b12c213721d2368704776
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang/include/clang/AST/ASTMutationListener.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/Frontend/MultiplexConsumer.cpp
M clang/lib/Sema/SemaModule.cpp
M clang/lib/Serialization/ASTWriter.cpp
A clang/test/Modules/class-instantiate-no-change-02.cppm
A clang/test/Modules/special-member-definitions.cppm
Log Message:
-----------
[C++20] [Modules] Apply DeclUpdate lazily in reduced BMI (#175498)
Previously we will apply all decl update unconditionally, but it might
not be best. See the attached example
'class-instantiate-no-change-02.cppm' for example. Sometimes these BMIs
are reducible.
Would land after 22 cut.
Commit: b929f2f0189ef3698d7b65168ff51976bb6f86e2
https://github.com/llvm/llvm-project/commit/b929f2f0189ef3698d7b65168ff51976bb6f86e2
Author: Wenju He <wenju.he at intel.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libclc/clc/include/clc/math/gentype.inc
M libclc/clc/include/clc/relational/binary_decl.inc
M libclc/clc/include/clc/relational/unary_decl.inc
M libclc/clc/lib/generic/atomic/clc_atomic_exchange.cl
M libclc/clc/lib/generic/atomic/clc_atomic_load.cl
M libclc/clc/lib/generic/atomic/clc_atomic_store.cl
M libclc/clc/lib/generic/common/clc_sign.inc
M libclc/opencl/lib/generic/relational/relational_binary_def.inc
M libclc/opencl/lib/generic/relational/relational_unary_def.inc
Log Message:
-----------
[libclc][NFC] Remove __CLC_BIT_INTN macro (#188023)
This macro was originally introduced in 64735ad63975 for relational
built-ins. It is functionally identical to __CLC_S_GENTYPE. Replacing it
simplifies gentype.inc, which is widely used in the library.
Commit: d607d6f78f803d51a961d991811f0f2f439f695a
https://github.com/llvm/llvm-project/commit/d607d6f78f803d51a961d991811f0f2f439f695a
Author: Alexey Merzlyakov <60094858+AlexeyMerzlyakov at users.noreply.github.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/test/CodeGen/AArch64/cls.ll
M llvm/test/CodeGen/AArch64/pr61549.ll
M llvm/test/CodeGen/VE/Scalar/ctlz.ll
Log Message:
-----------
[LegalizeTypes] Keep non-negative info in SUB(CTLZ) (#186338)
When legalizing CTLZ for a wider type with a SUB bit-width compensation,
the result for a zero-defined case can have an extra bit that exceeds
the maximum value of the original type width. Unlike CTLS, which covers
all bits within its type width, CTLZ leads to producing undefined
KnownBits. So, after subtraction, the KnownBits could represent a
negative value, which prevents subsequent optimizations.
This patch ensures that non-negative information is preserved during the
SUB(CTLZ) expansion, so that KnownBits after SUB will take a stricter
range within the type width, thus allowing further combine optimizations
following by SUB. Particularly, this enables the DAG Combiner to remove
unnecessary AND instructions for CTLZ output type conversion.
Fixes #136516
---------
Co-authored-by: Simon Pilgrim <git at redking.me.uk>
Commit: 96fb2942cb522b05f773f7492c1c125c7aef620c
https://github.com/llvm/llvm-project/commit/96fb2942cb522b05f773f7492c1c125c7aef620c
Author: Dan Blackwell <dan_blackwell at apple.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M compiler-rt/test/asan/TestCases/disable_container_overflow_checks.cpp
M compiler-rt/test/asan/TestCases/stack_container_dynamic_lib.cpp
Log Message:
-----------
[ASan] Enable __SANITIZER_DISABLE_CONTAINER_OVERFLOW__ tests (#181721)
Now that the corresponding libcxx change has landed, these tests should
be passing on some platforms.
This patch re-enables them for all platforms, so that we can see which
bots these do not work on and mark them unsupported accordingly.
rdar://167946476
Commit: 76177971a8f74f533a136577b8f709df96cd6b37
https://github.com/llvm/llvm-project/commit/76177971a8f74f533a136577b8f709df96cd6b37
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
A llvm/test/tools/opt/mattr-mcpu-help.ll
M llvm/tools/opt/optdriver.cpp
Log Message:
-----------
[opt] Enable -mcpu=help without an input file (#187876)
This patch enables `-mcpu=help` or `-mattr=help` invocation without an
input file, like `llc`. For example, the following command `opt
-mtriple=aarch64 -mattr=help` would previously hang but now it succeeds.
The implementation is similar to llc, creating a target machine for help
printing side effects and existing early. Note: llc has a bug in the
default triple handling that we already fix here upfront. Ill submit a
separate fix for llc.
Commit: 5e79d9798584e04fa03e48dd50ba152f74266ff0
https://github.com/llvm/llvm-project/commit/5e79d9798584e04fa03e48dd50ba152f74266ff0
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/test/tools/llc/mattr-mcpu-help.ll
M llvm/test/tools/llc/mtune.ll
M llvm/tools/llc/llc.cpp
Log Message:
-----------
[llc] Fix -mcpu=help for default target triple (#187878)
Previously, a command like `llc -mcpu=help` would fail on invalid target
triple, due to wrongly passing empty target to `Triple::normalize`
resulting in `unknown`.
Commit: 65b576d2b0c49adf2d477e90b43ea9ef35b165c3
https://github.com/llvm/llvm-project/commit/65b576d2b0c49adf2d477e90b43ea9ef35b165c3
Author: Carl Ritson <carl.ritson at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
A llvm/test/CodeGen/AMDGPU/atomic_optimizations_single_lane.ll
Log Message:
-----------
[AMDGPU] Disable atomic optimizer for single lane execution (#187915)
Optimized IR will have worse performance when only a single lane is
active. Disable optimizer when single lane is expected at compile time.
Commit: 34875331d956862d6f5b750c0bcf026d40564671
https://github.com/llvm/llvm-project/commit/34875331d956862d6f5b750c0bcf026d40564671
Author: Daniil Kovalev <dkovalev at accesssoftek.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang/lib/Headers/ptrauth.h
M compiler-rt/lib/builtins/crtbegin.c
Log Message:
-----------
[PAC][compiler-rt] Use `__ptrauth` qualifier instead of builtins (#188109)
Since #100830 has landed, we no longer need to rely on builtins
Commit: ff3632cdf37c94a4eb830c6cd501b3067a79163d
https://github.com/llvm/llvm-project/commit/ff3632cdf37c94a4eb830c6cd501b3067a79163d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libclc/clc/include/clc/math/clc_lgamma_r.h
A libclc/clc/include/clc/math/clc_lgamma_r_decl.inc
M libclc/clc/include/clc/shared/binary_with_out_arg_scalarize.inc
A libclc/clc/include/clc/shared/unary_with_out_arg_scalarize_loop.inc
M libclc/clc/lib/generic/math/clc_lgamma_r.cl
M libclc/clc/lib/generic/math/clc_lgamma_r.inc
A libclc/clc/lib/generic/math/clc_lgamma_r_stret.inc
Log Message:
-----------
libclc: Update lgamma_r (#188065)
This was originally ported from rocm device libs in
0ab07e1bde7d002f1a4c30babb6241c0cc366320. Merge
in more recent changes.
Commit: 641569de4e07f3a38af6720cabd84a91c73d8143
https://github.com/llvm/llvm-project/commit/641569de4e07f3a38af6720cabd84a91c73d8143
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libclc/clc/lib/generic/math/clc_tgamma.cl
A libclc/clc/lib/generic/math/clc_tgamma.inc
Log Message:
-----------
libclc: Improve tgamma handling (#188066)
Commit: 8f85bb16548c67eba62d3458afd21d311ab4d478
https://github.com/llvm/llvm-project/commit/8f85bb16548c67eba62d3458afd21d311ab4d478
Author: Chris Cotter <ccotter14 at bloomberg.net>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M mlir/lib/Pass/PassRegistry.cpp
Log Message:
-----------
[mlir][nfc] Fix gcc compiler error on destructor in PassRegistry.cpp (#187900)
Remove template arguments from out-of-line destructor definition, as
C++20 does not allow template-ids on destructors.
Commit: f243d8656b11e915f6edbffeed2c4afefb67a69f
https://github.com/llvm/llvm-project/commit/f243d8656b11e915f6edbffeed2c4afefb67a69f
Author: David Spickett <david.spickett at arm.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/utils/git/github-automation.py
Log Message:
-----------
[llvm][utils] Handle Issue/PR authors having no display name set (#186094)
user.login is the account name and user.name is an optional display name
(often their full name). I got an email generated from a colleague's PR
that said:
```
Author: None (<their username>)
```
As they hadn't set user.name in their account. Which isn't a problem,
but it would be neater if we didn't print None.
So I've added a helper function to handle that. If the user has set
both, the output is as it was before, if the user has not, we just show
the login name.
The login name can apparently be None too. In that case we'll print
"None" for it. This does not seem to be a common case though, and I'm
not sure printing anything else would be any more useful.
Commit: 040b7e0a1deb08702cf2c929f2f3bb9c62bd3b0c
https://github.com/llvm/llvm-project/commit/040b7e0a1deb08702cf2c929f2f3bb9c62bd3b0c
Author: Markus Böck <markus.boeck02 at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/include/llvm/ADT/PointerUnion.h
Log Message:
-----------
Revert "[llvm][ADT] Refactor PointerUnion to use PunnedPointer. NFC." (#188210)
Reverts llvm/llvm-project#187950
Commit: fe105347e2b6092ef4ce9704bcbdbcf6ad7d3d6b
https://github.com/llvm/llvm-project/commit/fe105347e2b6092ef4ce9704bcbdbcf6ad7d3d6b
Author: Luke Lau <luke at igalia.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll
M llvm/test/CodeGen/AArch64/intrinsic-cttz-elts.ll
M llvm/test/CodeGen/AArch64/sve-mask-partition.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-elts.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-elts.ll
Log Message:
-----------
[SelectionDAG] Expand CTTZ_ELTS[_ZERO_POISON] and handle splitting (#185605)
Currently a cttz.elts of e.g. nxv32i1 will get expanded to a reduction
of nxv32i64 or equivalent, but we can split it into two legal nxv16i1
cttz.elts once we have dedicated SelectionDAG nodes.
This implements the splitting for them the same way we implement type
splitting for vp.cttz.elts, i.e. check if the low result is VF, and if
so add it to the result of the high result. It also implements operand
type promotion for NEON which needs to promote i1 vectors to something
larger first.
We also need to move expansion into LegalizeVectorOps so it doesn't get
expanded before type legalization can do splitting. This uses
LegalizeVectorOps in case the scalar reduction type, which depends on
the minimum bitwidth needed to store the result, still needs type
promotion.
The TTI costs should be updated after this to reflect the more efficient
codegen, but that is deferred to another PR.
Commit: 1a5d1763595dd424d127da6e26dcc4e6ad481e3b
https://github.com/llvm/llvm-project/commit/1a5d1763595dd424d127da6e26dcc4e6ad481e3b
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M flang-rt/unittests/Runtime/Stop.cpp
Log Message:
-----------
[flang-rt] Fix test isolation, fixture usage, and other issues in Stop.cpp tests (#188155)
- Use TEST_F instead of TEST so CrashHandlerFixture::SetUp() is actually
called, registering the custom crash handler for death tests.
- Move putenv/executionEnvironment.Configure calls inside EXPECT_EXIT
blocks so they run in the forked child process, preventing the
NO_STOP_MESSAGE environment variable and configured global state from
leaking into subsequent tests.
- Replace const_cast<char *>("NO_STOP_MESSAGE=1") with a mutable static
char array, to avoid casting away constness of a string literal.
- Update CrashTest's expected pattern to match the output format of the
custom crash handler installed by CrashHandlerFixture, which was
previously never invoked due to the TEST vs TEST_F bug. (Note: there was
a buildbot failure related to this:
https://lab.llvm.org/buildbot/#/builders/130/builds/18413 )
Assisted-by: AI
Commit: 1b255ef5acdc5ebb14320efb135377f3b417c958
https://github.com/llvm/llvm-project/commit/1b255ef5acdc5ebb14320efb135377f3b417c958
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libclc/clc/lib/generic/math/clc_ep.cl
M libclc/clc/lib/generic/math/clc_expm1.cl
M libclc/clc/lib/generic/math/clc_expm1.inc
Log Message:
-----------
libclc: Update expm1 (#188209)
This was originally ported from rocm device libs in
900bd7eb7f5426ad13f624cbf29716afe376c878. Merge in more
recent changes.
Commit: d491f702062d5ca14a7f633baf4b307a900fc02f
https://github.com/llvm/llvm-project/commit/d491f702062d5ca14a7f633baf4b307a900fc02f
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libclc/clc/include/clc/math/clc_ep_decl.inc
M libclc/clc/lib/generic/math/clc_ep.inc
M libclc/clc/lib/generic/math/clc_sinh.cl
M libclc/clc/lib/generic/math/clc_sinh.inc
Log Message:
-----------
libclc: Update sinh (#188213)
This was originally ported from rocm device libs in
9f7172965c650627c020264e9dbdb32d005ce69e. Merge in more
recent changes.
Commit: c15edf8208f01b2bde0b7dfcbe9ac05757cdefb7
https://github.com/llvm/llvm-project/commit/c15edf8208f01b2bde0b7dfcbe9ac05757cdefb7
Author: Zorojuro <sawantsukumar at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libc/shared/math/cbrtf.h
Log Message:
-----------
[libc] cbrtf guard to sync with general format (#188207)
This PR intends to make the cbrtf guard sync with the general format (
as other functions consistently use `LLVM_LIBC_SHARED_MATH_<func>_H`).
This was found during refactoring cbrtbf16.
Commit: aeba5d62e5352aa3ed2f0d5a6a563ac873dde716
https://github.com/llvm/llvm-project/commit/aeba5d62e5352aa3ed2f0d5a6a563ac873dde716
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libclc/clc/lib/generic/math/clc_cosh.cl
M libclc/clc/lib/generic/math/clc_cosh.inc
Log Message:
-----------
libclc: Update cosh (#188214)
This was originally ported from rocm device libs in
9cb070f96a8a9af5f513ffba0a8eed362623f216. Merge in more
recent changes.
Commit: f1931cb6df0f66204f878647b9c341d3d57de241
https://github.com/llvm/llvm-project/commit/f1931cb6df0f66204f878647b9c341d3d57de241
Author: Konrad Kleine <kkleine at redhat.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/DebugInfo/DWARF/DWARFDebugAbbrev.cpp
M llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp
M llvm/lib/DebugInfo/DWARF/DWARFDebugArangeSet.cpp
Log Message:
-----------
[llvm][DebugInfo] Use formatv instead of format in DebugAbbrev/Addr/ArangeSet (#186768)
This relates to #35980.
Commit: 3286de333b691d3d815939ce5618f85be71b1575
https://github.com/llvm/llvm-project/commit/3286de333b691d3d815939ce5618f85be71b1575
Author: Konrad Kleine <kkleine at redhat.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/DebugInfo/DWARF/DWARFCompileUnit.cpp
Log Message:
-----------
[llvm][DebugInfo] DWARFCompileUnit use formatv instead of format (#186761)
This relates to #35980.
Commit: f046f4518dc7c707289b2fc8b748d3034cfa4c15
https://github.com/llvm/llvm-project/commit/f046f4518dc7c707289b2fc8b748d3034cfa4c15
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libclc/clc/lib/generic/math/clc_tanh.cl
M libclc/clc/lib/generic/math/clc_tanh.inc
Log Message:
-----------
libclc: Update tanh (#188215)
This was originally ported from rocm device libs in
f51df5ba8c4512dbeb7828ac0c34f89177b551d6. Merge in more
recent changes.
Commit: fcc9ce94f6ba54484e2438aa5d456cc5dcaa40b6
https://github.com/llvm/llvm-project/commit/fcc9ce94f6ba54484e2438aa5d456cc5dcaa40b6
Author: Konrad Kleine <kkleine at redhat.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/DebugInfo/BTF/BTFParser.cpp
Log Message:
-----------
[llvm][DebugInfo] BTFParser use formatv instead of format (#186109)
This relates to #35980.
Commit: 25da0c8ddbefc7b9c519dc45ae582ec6f5d9121c
https://github.com/llvm/llvm-project/commit/25da0c8ddbefc7b9c519dc45ae582ec6f5d9121c
Author: Konrad Kleine <kkleine at redhat.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/unittests/Support/FormatVariadicTest.cpp
Log Message:
-----------
[llvm][DebugInfo] Make to be formatted test value 64-bit (#188211)
Commit: 80245f3b1471c264cdac87f1d8ceb7169f5f68d6
https://github.com/llvm/llvm-project/commit/80245f3b1471c264cdac87f1d8ceb7169f5f68d6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libclc/clc/lib/generic/math/clc_asinh.cl
M libclc/clc/lib/generic/math/clc_asinh.inc
Log Message:
-----------
libclc: Update asinh (#188219)
This was originally ported from rocm device libs in
2b4ef39b2f46acf29294f1fbb223ea5a243c2567. Merge in more
recent changes.
Commit: 7d39664a6ae8daaf186b65578492244d96a50bf2
https://github.com/llvm/llvm-project/commit/7d39664a6ae8daaf186b65578492244d96a50bf2
Author: Luke Lau <luke at igalia.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll
M llvm/test/CodeGen/AArch64/intrinsic-cttz-elts.ll
M llvm/test/CodeGen/AArch64/sve-mask-partition.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-elts.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-elts.ll
Log Message:
-----------
Revert "[SelectionDAG] Expand CTTZ_ELTS[_ZERO_POISON] and handle splitting" (#188220)
Reverts llvm/llvm-project#185605
Buildbot failures caused by ISel crashes in
https://lab.llvm.org/buildbot/#/builders/157/builds/45416 and
https://lab.llvm.org/buildbot/#/builders/10/builds/25156
Commit: ad39e5a6b84819b75581ab8b1adafd1c8ffc9899
https://github.com/llvm/llvm-project/commit/ad39e5a6b84819b75581ab8b1adafd1c8ffc9899
Author: Twice <twice at apache.org>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M mlir/docs/Bindings/Python.md
Log Message:
-----------
[MLIR][Python][Docs] Fix example of Python-defined dialects (#188174)
Some breaking changes are introduced in #186574 for Python-defined
dialects. So we need to fix the example in the docs.
Commit: 2857f3bb6af5b7befee796c7ad3bb4edf8b6b028
https://github.com/llvm/llvm-project/commit/2857f3bb6af5b7befee796c7ad3bb4edf8b6b028
Author: Mariya Podchishchaeva <mariya.podchishchaeva at intel.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang/lib/Sema/SemaSYCL.cpp
M clang/test/ASTSYCL/ast-dump-sycl-kernel-call-stmt.cpp
M clang/test/CodeGenSYCL/kernel-caller-entry-point.cpp
Log Message:
-----------
[clang][SYCL] Strip references from generated kernel argument types (#186788)
Prior to this patch kernel generation copied kernel argument types
exactly as they're written in function's signature of the function
attributed with [[clang::sycl_kernel_entry_point]] attribute. This
caused generation of kernels that have reference kernel argument instead
of byval kernel argument.
SYCL 2020 doesn't allow reference kernel arguments and it doesn't seem
to work with the backends.
Arguments to [[clang::sycl_kernel_entry_point]]-attributed function can
be big, so we preserve references during host code generation to avoid
performance issues in SYCL Runtime library implementation because the
same function will be used for actual kernel argument setting via
sycl_kernel_launch interface.
Note that we still need to diagnose references in user's kernel
arguments since they are explicitly not allowed by SYCL 2020 spec and
this task is in TODO list. This patch simply removes references from
types written in SYCL Runtime library.
Assisted-by: claude in test writing.
Commit: 8b224162fa6aa6ebb6dd963c89b45571b1b0c8e5
https://github.com/llvm/llvm-project/commit/8b224162fa6aa6ebb6dd963c89b45571b1b0c8e5
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
R libclc/clc/include/clc/math/clc_ep_log.h
R libclc/clc/include/clc/math/clc_ep_log_decl.inc
M libclc/clc/lib/generic/CMakeLists.txt
M libclc/clc/lib/generic/math/clc_acosh.cl
M libclc/clc/lib/generic/math/clc_acosh.inc
R libclc/clc/lib/generic/math/clc_ep_log.cl
R libclc/clc/lib/generic/math/clc_ep_log.inc
Log Message:
-----------
libclc: Update acosh (#188224)
libclc: Update acosh
This was originally ported from rocm device libs
in ca4d382e119e1389c83dbb07d9ca0085e88b2944. Merge in
more recent changes.
Remove unused ep_log.
Commit: 46205ff9b4cbe2bc18cc6600f0acf76bb4810053
https://github.com/llvm/llvm-project/commit/46205ff9b4cbe2bc18cc6600f0acf76bb4810053
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libclc/clc/lib/generic/math/clc_atanh.cl
M libclc/clc/lib/generic/math/clc_atanh.inc
Log Message:
-----------
libclc: Update atanh (#188225)
Commit: b1aa6a45060bb9f89efded9e694503d6b4626a4a
https://github.com/llvm/llvm-project/commit/b1aa6a45060bb9f89efded9e694503d6b4626a4a
Author: Denis.G <34353767+DenisGZM at users.noreply.github.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/include/llvm/CodeGen/LowLevelTypeUtils.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/CodeGenTypes/LowLevelType.h
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/LowLevelTypeUtils.cpp
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGenTypes/LowLevelType.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-subvector.ll
M llvm/test/CodeGen/AArch64/GlobalISel/pr168872.ll
M llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
M llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument-multiple.ll
M llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument.ll
M llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid0.mir
M llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid1.mir
M llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid2.mir
M llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid3.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err0.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err1.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err10.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err11.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err12.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err13.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err14.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err15.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err2.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err3.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err4.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err5.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err6.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err7.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err8.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err9.mir
M llvm/test/CodeGen/MIR/WebAssembly/typed-immediate-operand-invalid0.mir
M llvm/test/CodeGen/MIR/WebAssembly/typed-immediate-operand-invalid1.mir
M llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
M llvm/test/TableGen/GlobalISelEmitter/HwModes.td
M llvm/unittests/CodeGen/GlobalISel/CMakeLists.txt
A llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp
M llvm/utils/TableGen/Common/CMakeLists.txt
M llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
M llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTableExecutorEmitter.cpp
M llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTableExecutorEmitter.h
Log Message:
-----------
[GlobalISel][LLT] Introduce FPInfo for LLT (Enable bfloat, ppc128float and others in GlobalISel) (#155107)
Added extra information in LLT to support ambiguous fp types during
GlobalISel. Original idea by @tgymnich
Main differences from https://github.com/llvm/llvm-project/pull/122503
are:
* Do not deprecate LLT::scalar
* Allow targets to enable/disable IR translation with extenden LLT via
`TargetOption::EnableGlobalISelExtendedLLT` (disabled by default)
* `IRTranslator` use `TargetLoweringInfo` for appropriate `LLT`
generation.
* For this reason added flag in GlobalISelMatchTable` to allow switch
between legacy and new extended LLT names
* Revert using stubs like `LLT::float32` for float types as they are
real now. Added `TODO` for such cases.
Also MIRParser now may parse new type indentifiers.
---------
Co-authored-by: Tim Gymnich <tim at gymni.ch>
Co-authored-by: Ryan Cowan <ryan.cowan at arm.com>
Commit: 8a61e8f816b8f960e3671d458cc3b74f3c9131dc
https://github.com/llvm/llvm-project/commit/8a61e8f816b8f960e3671d458cc3b74f3c9131dc
Author: Utkarsh Saxena <usx at google.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang/include/clang/Analysis/Analyses/LifetimeSafety/Facts.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/Loans.h
M clang/lib/Analysis/LifetimeSafety/Checker.cpp
M clang/lib/Analysis/LifetimeSafety/Facts.cpp
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/lib/Analysis/LifetimeSafety/Loans.cpp
M clang/lib/Analysis/LifetimeSafety/MovedLoans.cpp
M clang/test/Sema/warn-lifetime-safety-dataflow.cpp
M clang/test/Sema/warn-lifetime-safety.cpp
M clang/unittests/Analysis/LifetimeSafetyTest.cpp
Log Message:
-----------
[LifetimeSafety] Introduce AccessPath-based expiry (#187708)
Refactored the loan system to use access paths instead of loan IDs for
expiry tracking, consolidating PathLoan and PlaceholderLoan into a
unified Loan class.
This is a non-functional refactoring to move towards more granular
paths. This also removes a quadratic complexity of `handleLifetimeEnds`
where we iterated over all loans to find which loans expired.
Commit: 17d28a5b53b04c6a89ff3087a3fb57f462e563fa
https://github.com/llvm/llvm-project/commit/17d28a5b53b04c6a89ff3087a3fb57f462e563fa
Author: yronglin <yronglin777 at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Lex/PPDirectives.cpp
M clang/test/CXX/module/dcl.dcl/dcl.module/p1.cpp
Log Message:
-----------
[clang] Don't crash when module directive `export module foo` not following a semicolon and there are no rest pp-tokens in current module file (#187845)
This PR add the missing check of nullable `std::optional<Token>` object
when the module directive `export module foo` not following a semicolon
and there are no rest pp-tokens in current module file.
---------
Signed-off-by: yronglin <yronglin777 at gmail.com>
Co-authored-by: Aaron Ballman <aaron at aaronballman.com>
Commit: 95d54423d9abb3ed577f68e32b1c158cf984193a
https://github.com/llvm/llvm-project/commit/95d54423d9abb3ed577f68e32b1c158cf984193a
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
M flang/test/Fir/declare_value-codegen.fir
M flang/test/Integration/debug-allocatable-1.f90
M flang/test/Integration/debug-common-block-1.f90
M flang/test/Integration/debug-complex-1.f90
M flang/test/Integration/debug-complex-2.f90
M flang/test/Integration/debug-fixed-array-type-2.f90
M flang/test/Integration/debug-local-var-2.f90
M flang/test/Integration/debug-module-2.f90
M flang/test/Integration/debug-proc-ptr-e2e.f90
M flang/test/Integration/debug-ptr-type.f90
M flang/test/Transforms/debug-allocatable-1.fir
M flang/test/Transforms/debug-associate-component.fir
M flang/test/Transforms/debug-complex-1.fir
M flang/test/Transforms/debug-derived-type-1.fir
M flang/test/Transforms/debug-fixed-array-type.fir
M flang/test/Transforms/debug-fn-info.fir
M flang/test/Transforms/debug-index-type.fir
M flang/test/Transforms/debug-local-var.fir
M flang/test/Transforms/debug-module-1.fir
M flang/test/Transforms/debug-module-2.fir
M flang/test/Transforms/debug-proc-ptr.fir
M flang/test/Transforms/debug-ptr-type.fir
M flang/test/Transforms/debug-vector-type.fir
Log Message:
-----------
[flang][debug] Always include (kind=X) suffix in debug type names (#186255)
Previously, 32-bit types (integer, real, logical, complex) were printed
without the (kind=4) suffix in DWARF debug type names, while other sizes
always included the kind suffix. This inconsistency is now removed by
always appending (kind=X) to all basic type names, making the format
uniform across all type sizes.
Fixes https://github.com/llvm/llvm-project/issues/119478.
Commit: 4961700c1004067dab2454df09a0de6b02410025
https://github.com/llvm/llvm-project/commit/4961700c1004067dab2454df09a0de6b02410025
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libc/shared/rpc.h
M libc/shared/rpc_util.h
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/include/RPC.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/common/src/RPC.cpp
Log Message:
-----------
[libc] Support AMDGPU device interrupts for the RPC interface (#188067)
Summary:
One of the main disadvantages to using the RPC interface is that it
requires a server thread to spin on the mailboxes checking for work.
The vast majority of the time, there will be no work and work will come
in large bursts.
The HSA / KFD interface supports device-side interrupts and already has
handling for binding these events to an HSA signal. This means that we
can send interrupts from the GPU to wake a sleeping thread on the CPU.
The sleeping thread will be descheduled with a blocking HSA wait call
and woken up when its event ID is raised through the kernel driver's
interrupt.
This is very target-specific handling, but I believe it is valuable
enough to warrant it being in the protocol. It is completely optional,
as it is ignored if uninitialized. This should bring this support at
parity with the interface HIP expects.
Commit: fb3c8228ed362ed2f778ff44382d61af2395790f
https://github.com/llvm/llvm-project/commit/fb3c8228ed362ed2f778ff44382d61af2395790f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/cttz-elts.ll
Log Message:
-----------
[RISCV] canCreateUndefOrPoisonForTargetNode - RISCVISD::READ_VLENB nodes don't create undef/poison (#188231)
Fixes a number of regressions in an upcoming FREEZE patch
Commit: 7af471a8eda3e1882657115d36eb000df3ffa5fd
https://github.com/llvm/llvm-project/commit/7af471a8eda3e1882657115d36eb000df3ffa5fd
Author: Leandro Lupori <leandro.lupori at linaro.org>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/test/Lower/OpenMP/composite_simd_linear.f90
M flang/test/Lower/OpenMP/distribute-parallel-do-simd.f90
M flang/test/Lower/OpenMP/distribute-simd.f90
M flang/test/Lower/OpenMP/loop-pointer-variable.f90
M flang/test/Lower/OpenMP/ordered-simd.f90
M flang/test/Lower/OpenMP/wsloop-simd.f90
Log Message:
-----------
Reland "[flang][OpenMP] Fix lowering of LINEAR iteration variables (#183794)" (#187766)
Linear iteration variables were being treated as private. This fixes
one of the issues reported in #170784.
The previous regressions are fixed by #187097.
Commit: ef6172f32757aff6e4c4bb237ed3132d7ef24c12
https://github.com/llvm/llvm-project/commit/ef6172f32757aff6e4c4bb237ed3132d7ef24c12
Author: keinflue <keinflue at posteo.de>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaChecking.cpp
M clang/test/SemaCXX/builtin-classify-type.cpp
Log Message:
-----------
[clang] Apply lvalue conversions to __builtin_classify_type argument (#175627)
According to GCC documentation default argument promotion is applied to
the argument, which includes the function-to-pointer and
array-to-pointer lvalue conversions.
This also implies checking of the argument for placeholder types.
Fixes #175589.
Commit: 376874a345d3fd5f7171f78e48e5dea01c703dd8
https://github.com/llvm/llvm-project/commit/376874a345d3fd5f7171f78e48e5dea01c703dd8
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
Log Message:
-----------
[Offload] Fix destroying signal that was never initialized
Summary:
We create the RPC doorbell signal lazily and destroy it at the plugin
level. This means that we can't rely on the normal 'per-device' handling
so this needs to be called unconditionally. We only create the signal if
a device is registered, but deinit is called unconditionally. Just check
the handle.
Commit: da439d54267d478d1771928a714c0c52d7e7fc17
https://github.com/llvm/llvm-project/commit/da439d54267d478d1771928a714c0c52d7e7fc17
Author: Petter Berntsson <petter.berntsson at arm.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libc/docs/CMakeLists.txt
M libc/docs/headers/index.rst
Log Message:
-----------
[libc][docs] Avoid docgen target collisions and restore pthread docs (#188221)
Fixes llvm/llvm-project#123821.
Re-enabling pthread docs created a global CMake utility target named
`pthread`, which collides in combined runtime builds where `pthread` is
expected to be a library name. Namespace the internal libc docgen helper
targets under `libc-docgen-*` and restore the generated pthread docs
page. `docs-libc-html` is unchanged.
Commit: 5bce5f54f081a9ab8b8819634573b03108752764
https://github.com/llvm/llvm-project/commit/5bce5f54f081a9ab8b8819634573b03108752764
Author: Minsoo Choo <minsoochoo0122 at proton.me>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Support/Unix/Process.inc
Log Message:
-----------
[llvm] Update terminal list with ANSI colors (#187920)
ncurses hasn't adopted terminal entries for some terminal emulators like
Alacritty, Ghostty, and kitty in `xterm-*` format. To fix mismatch
between remote terminfo-db and terminal emulator that is accessing (e.g.
SSH), users explicitly set `$TERM` to `ghostty` or similar on the remote
side to make colors work. However, since `$TERM` has changed to non
`xterm-*` format in this case, llvm's `xterm-*` filter fails to catch
the terminal. Thus add entries for most widely used terminal emulators
(Alacritty, Ghostty, kitty) in terminfo-db version so llvm's filter can
catch it.
Signed-off-by: Minsoo Choo <minsoochoo0122 at proton.me>
Commit: 6638cee0d8db18cf19b9d832e8c5f0be12b4f1c8
https://github.com/llvm/llvm-project/commit/6638cee0d8db18cf19b9d832e8c5f0be12b4f1c8
Author: Zorojuro <sawantsukumar at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libc/src/math/generic/logf.cpp
Log Message:
-----------
[libc] Remove redundant and incorrect comments in `logf.cpp` (#188236)
This PR intends to fix the nit (mostly caused during the refactor in
693a018dcf08e )
- During refactor we move the implementation along with the explanation
comments to header.
```CPP
// This is an algorithm for log(x) in single precision which is correctly
// rounded for all rounding modes, based on the implementation of log(x) from
// the RLIBM project at:
// https://people.cs.rutgers.edu/~sn349/rlibm
// Step 1 - Range reduction:
// For x = 2^m * 1.mant, log(x) = m * log(2) + log(1.m)
// If x is denormal, we normalize it by multiplying x by 2^23 and subtracting
.....
// Symposium on Principles of Programming Languages (POPL-2022), Philadelphia,
// USA, January 16-22, 2022.
// https://people.cs.rutgers.edu/~sn349/papers/rlibmall-popl-2022.pdf
```
Though the explanation comments were copied and moved to header in
d2492c1 . It wasn't deleted from the `cpp` file.
Along with this in the same,
`#include "src/__support/math/logf.h" // Lookup table for (1/f) and
log(f)`
is wrong as it is actually for
`#include "src/__support/math/common_constants.h" // Lookup table for
(1/f) and log(f)`
Commit: 227bab0a623c42a631d3b30446e668335732c488
https://github.com/llvm/llvm-project/commit/227bab0a623c42a631d3b30446e668335732c488
Author: Alex Duran <alejandro.duran at intel.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M offload/plugins-nextgen/level_zero/src/L0Context.cpp
M offload/plugins-nextgen/level_zero/src/L0Plugin.cpp
M offload/plugins-nextgen/level_zero/src/L0Program.cpp
Log Message:
-----------
[OFFLOAD][L0] Improve cleanup on errors (#188251)
Additional cleanup improvements on error conditions (in addition to
those in #187597):
* Fixed incomplete cleanup in L0Context::init()
* Fixed build log leak in addModule()
* Fixed context inconsistent state in findDevices()
Disclaimer: The base of this PR was generated by Claude and adjusted by
me afterwards.
Commit: 0328820004d89ca9876ac75c8c55f1eb239a6be7
https://github.com/llvm/llvm-project/commit/0328820004d89ca9876ac75c8c55f1eb239a6be7
Author: Sirui Mu <msrlancern at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/test/CIR/IR/invalid-func.cir
Log Message:
-----------
[CIR][NFC] Fix regression in clang/test/CIR/IR/func.cir (#188069)
This patch fixes a regression in `clang/test/CIR/IR/func.cir` where the
parsing of `special_member` attributes fails.
Commit: 4fcc3d7f4ced4f911883f4427907d2a7d66d951f
https://github.com/llvm/llvm-project/commit/4fcc3d7f4ced4f911883f4427907d2a7d66d951f
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Target/Sparc/SparcInstrInfo.cpp
Log Message:
-----------
[Sparc] Report correct size for GETPCX pseudo (#188075)
This currently reports size 4, but the actual size is larger.
Commit: d422ffe19f1cacc7c6a6908d9f73d81ba8e65b6e
https://github.com/llvm/llvm-project/commit/d422ffe19f1cacc7c6a6908d9f73d81ba8e65b6e
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/AArch64/unprofitable-alternate-subtree.ll
Log Message:
-----------
[SLP][NFC]Add a test with the non-profitable alternate vectorization, not throttled
Commit: c312bf3fa94430185410c06c502abd9953f838fa
https://github.com/llvm/llvm-project/commit/c312bf3fa94430185410c06c502abd9953f838fa
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Support/DivisionByConstantInfo.cpp
Log Message:
-----------
[DivisionByConstant] Don't compare bool to 0. Use APInt::getOneBitSet. NFC (#188178)
Commit: ff07361fdf18bb9094331814db9dae000a35e254
https://github.com/llvm/llvm-project/commit/ff07361fdf18bb9094331814db9dae000a35e254
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/AArch64/rem-by-const.ll
M llvm/test/CodeGen/RISCV/urem-lkk.ll
M llvm/test/CodeGen/X86/divmod128.ll
M llvm/test/CodeGen/X86/i128-udiv.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
Log Message:
-----------
[TargetLowering] In expandDIVREMByConstant, combine shift by trailing zeros with chunk shifts. (#188086)
This reduces the number of generated instructions in some cases.
While I was there, I changed an Add to a Disjoint OR since DAGCombine
was going to do it anyway.
Commit: 2c2706dd04dea8803437b7cb96152179a848862e
https://github.com/llvm/llvm-project/commit/2c2706dd04dea8803437b7cb96152179a848862e
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
Log Message:
-----------
[X86] getFauxShuffleMask - decode insert_subvector(undef, x, c) as shuffle if c != 0 (#188258)
Move existing combineX86ShufflesRecursively handling into
getFauxShuffleMask to allow other shuffle folds to make use of it
Commit: 20e59c8e2dbbd3b574e2358e0b690f0ddec129fc
https://github.com/llvm/llvm-project/commit/20e59c8e2dbbd3b574e2358e0b690f0ddec129fc
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/cube.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubeid.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubema.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubesc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubetc.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for cube intrinsics (#187762)
Add RegBankLegalize rules for cube* intrinsics. Also update manual tests
to use autogenerated checks.
Commit: 1034c7077296542fe0f88d38dbcfa6814f85be6c
https://github.com/llvm/llvm-project/commit/1034c7077296542fe0f88d38dbcfa6814f85be6c
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for cvt_pknorm (#187834)
Commit: 9708da6f2dc95edcfc98a82c67c8f44079110f55
https://github.com/llvm/llvm-project/commit/9708da6f2dc95edcfc98a82c67c8f44079110f55
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for fmad_ftz (#188132)
Commit: 4a2b384f1518b0e2bd35ac2d04bc3aac72db25d3
https://github.com/llvm/llvm-project/commit/4a2b384f1518b0e2bd35ac2d04bc3aac72db25d3
Author: Jasmine Tang <jjasmine at igalia.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/test/CodeGen/NVPTX/i1-int-to-fp.ll
Log Message:
-----------
[NVPTX] Fix sign issue in sint -> bf16 (#188118)
Fixes #187000
Commit: c1ea10a854dcbbb50c954ebb87246d822cd01e21
https://github.com/llvm/llvm-project/commit/c1ea10a854dcbbb50c954ebb87246d822cd01e21
Author: Justin Cady <desk at justincady.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang-tools-extra/clangd/CMakeLists.txt
A clang-tools-extra/clangd/remap/CMakeLists.txt
A clang-tools-extra/clangd/remap/RemapMain.cpp
M clang-tools-extra/clangd/test/CMakeLists.txt
A clang-tools-extra/clangd/test/remap.test
Log Message:
-----------
[clangd] Add background index path remapping tool (#185482)
Introduce a standalone tool to remap paths inside clangd background
index files. This allows users to pay the cost of generating a full
background index once, then reuse the background index across multiple
clients. Each client rewrites the background index in place after
copying the original, specifying the path(s) to be remapped.
This is an alternative approach to the dynamic path remapping proposed
in #180285.
Fixes clangd/clangd#847
Assisted-by: claude
Commit: 9391ce93a1b82b85890e5d15b36849b542e11db8
https://github.com/llvm/llvm-project/commit/9391ce93a1b82b85890e5d15b36849b542e11db8
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M flang/test/Lower/Intrinsics/pack.f90
M flang/test/Lower/Intrinsics/parity.f90
M flang/test/Lower/Intrinsics/popcnt.f90
M flang/test/Lower/Intrinsics/poppar.f90
M flang/test/Lower/Intrinsics/present.f90
Log Message:
-----------
[flang][NFC] Converted five tests from old lowering to new lowering (part 38) (#188151)
Tests converted from test/Lower/Intrinsics: pack.f90, parity.f90,
popcnt.f90, poppar.f90, present.f90
Commit: 8443dfaacf520b22700555718ecfb71508c15a64
https://github.com/llvm/llvm-project/commit/8443dfaacf520b22700555718ecfb71508c15a64
Author: Kevin Sala Penades <salapenades1 at llnl.gov>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang/docs/OpenMPSupport.rst
Log Message:
-----------
[OpenMP] Mark dyn_groupprivate support as partial for C/C++ (#186706)
Commit: 26fcbd5aaed125ab99b19299f4ec686912a7af92
https://github.com/llvm/llvm-project/commit/26fcbd5aaed125ab99b19299f4ec686912a7af92
Author: vporpo <vasileios.porpodas at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Log Message:
-----------
[AMDGPU][SIInsertWaitcnts] Fix counterOutOfOrder() check for LOAD_CNT (#187758)
This is a follow-up to @piotrAMD's comment in #178511 .
`hasPendingEvent()` used to return an unsigned mask but this changed in
#178511 when this function started to return bool. This changed the
functionality of `counterOutOfOrder()` which was still using an unsigned
mask that was erroneously being assigned a boolean instead of the
expected mask.
Commit: d0f5df111865ea4bb9d7d6ff35b517ee1aa7402f
https://github.com/llvm/llvm-project/commit/d0f5df111865ea4bb9d7d6ff35b517ee1aa7402f
Author: Minsoo Choo <minsoochoo0122 at proton.me>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M lldb/source/Plugins/Process/FreeBSD-Kernel-Core/ProcessFreeBSDKernelCore.cpp
Log Message:
-----------
[lldb][Process/FreeBSDKernelCore] Remove interactive mode check (#187981)
`debugger.GetCommandInterpreter().IsInteractive()` doesn't necessarily
mean that the debugger is running without `-b` or `--batch` flag. This
caused an issue where the message isn't printed in any case. Remove the
check so the message is always printed for now.
Fixes: 9d9c7fc00bdddd72e78b19e9fbb6af9d07c2218b (#178027)
Signed-off-by: Minsoo Choo <minsoochoo0122 at proton.me>
Commit: 1d883c675e786920d9e1c6af4fb5fcfb40b4f09a
https://github.com/llvm/llvm-project/commit/1d883c675e786920d9e1c6af4fb5fcfb40b4f09a
Author: Kunwar Grover <groverkss at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/TilingInterfaceImpl.cpp
M mlir/test/Dialect/Linalg/transform-tile-reduction.mlir
M mlir/test/Interfaces/TilingInterface/tile-and-fuse-with-reduction-tiling.mlir
Log Message:
-----------
[mlir][linalg] Fix linalg.index handeling in partial reduction tiling (#188261)
PartialReduction tiling wasn't handeling linalg.index offsets properly.
This patch fixes it to do the same thing as TilingInterface.
Commit: 5f0b3d6af425d2cd849a5914d5bb65d45f091cca
https://github.com/llvm/llvm-project/commit/5f0b3d6af425d2cd849a5914d5bb65d45f091cca
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Fix formatting and debug printing, NFC
Commit: ab903b4f783fbed6f005d40b17b8050d79a662b2
https://github.com/llvm/llvm-project/commit/ab903b4f783fbed6f005d40b17b8050d79a662b2
Author: Oliver Hunt <oliver at apple.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/include/llvm/ADT/StringSwitch.h
M llvm/unittests/ADT/StringSwitchTest.cpp
Log Message:
-----------
[ADT] Add predicate based match support to StringSwitch (#188046)
This introduces `Predicate` and `IfNotPredicate` case selection to
StringSwitch to allow use cases like
```
StringSwitch<...>(..)
.Case("foo", FooTok)
.Predicate([](StringRef Str){ ... }, IdentifierTok)
...
```
This is mostly useful for improving conciseness and clarity when
processing generated strings, diagnostics, and similar.
Commit: ce44d63e0d14039f1e8f68e6b7c4672457cabd4e
https://github.com/llvm/llvm-project/commit/ce44d63e0d14039f1e8f68e6b7c4672457cabd4e
Author: Alan Li <me at alanli.org>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp
Log Message:
-----------
[GlobalISel][Test] Fix `IRTranslatorBF16Test` crash (#188273)
Skip the test when the AArch64 target is unavailable.
Commit: de6ed3c81dabee9772d77f95510480c8e1cee1ff
https://github.com/llvm/llvm-project/commit/de6ed3c81dabee9772d77f95510480c8e1cee1ff
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
Log Message:
-----------
[PowerPC] Fix some instruction sizes (#188227)
This fixes:
* PADDIdtprel: Lowers to PADDI8, which is prefixed.
* PATCHABLE_FUNTION_ENTER/PATCHABLE_RET: Handle xray sleds.
These came up when generalizing the instruction size verification
infrastructure.
Commit: 4eedd518be53814395dcba5c78bb14d09a77821c
https://github.com/llvm/llvm-project/commit/4eedd518be53814395dcba5c78bb14d09a77821c
Author: earnol <earnol at users.noreply.github.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/StdNamespaceModificationCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/test/clang-tidy/checkers/bugprone/std-namespace-modification-implicit.cpp
A clang/test/AST/ast-dump-implicit-align-val.cpp
Log Message:
-----------
[clang-tidy] Do not provide diagnostics for cert-dcl58-cpp on implicit declarations (#188152)
Do not provide diagnostics for cert-dcl58-cpp for compiler generated
intrinsic as it will be a false positive.
In provided tests compiler generates align_val_t which ends up inside
std namespace, resulting in std::align_val_t symbol. This symbol is
compiler generated, having no location, causing compiler crash. Also
there is no point to notify user about violations which user has no
control of.
Resolution: Diagnostics suppressed.
Co-authored-by: Vladislav Aranov <vladislav.aranov at ericsson.com>
Commit: e73d8f8fc59ae2108baf863a6c8c8cfddbbca537
https://github.com/llvm/llvm-project/commit/e73d8f8fc59ae2108baf863a6c8c8cfddbbca537
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M compiler-rt/cmake/Modules/CompilerRTUtils.cmake
M compiler-rt/cmake/caches/GPU.cmake
M compiler-rt/test/CMakeLists.txt
M compiler-rt/test/builtins/CMakeLists.txt
M compiler-rt/test/builtins/Unit/lit.cfg.py
M compiler-rt/test/lit.common.cfg.py
Log Message:
-----------
[compiler-rt] Support unit tests for the GPU build (#187895)
Summary:
This PR enables the basic unit tests for builtins to be run on the GPU
architectures. Other targets like profiling are supported, but the
host-device natures will make it more difficult to adequately unit
test. It may be be possible to do basic tests there, to simply verify
that
counters are present and in the proper format for when they are copied
to the host.
Commit: c7b5f7c635e2534a9b2b2b204998b0bc39921b7e
https://github.com/llvm/llvm-project/commit/c7b5f7c635e2534a9b2b2b204998b0bc39921b7e
Author: Fangrui Song <i at maskray.me>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Support/Parallel.cpp
Log Message:
-----------
[Support] Use atomic counter in parallelFor instead of per-task spawning (#187989)
This function is primarily used by lld and debug info tools.
Instead of pre-splitting work into up to MaxTasksPerGroup (1024) tasks
and spawning each through the Executor's mutex+condvar, use an atomic
counter for work distribution. Only ThreadCount workers are spawned;
each grabs the next chunk via atomic fetch_add.
This reduces futex calls from ~31K (glibc, release+assertions build) to
~1.4K when linking clang-14 (191MB PIE with --export-dynamic) with
`ld.lld --threads=8` (each parallelFor spawned up to 1024 tasks, each
requiring mutex lock + condvar signal).
```
Wall System futex
glibc (assertions) before: 927ms 897ms 31K
glibc (assertions) after: 879ms 765ms 1.4K
mimalloc before: 872ms 694ms 25K
mimalloc after: 830ms 661ms 1K
```
Commit: 6e2a720dd1890d49afef6ab5165cb6e7fd346048
https://github.com/llvm/llvm-project/commit/6e2a720dd1890d49afef6ab5165cb6e7fd346048
Author: Pankaj Dwivedi <pankajkumar.divedi at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/include/llvm/ADT/GenericUniformityImpl.h
M llvm/include/llvm/ADT/Uniformity.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/UniformityAnalysis.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
A llvm/test/Analysis/UniformityAnalysis/AMDGPU/uniform_intrinsic.ll
Log Message:
-----------
[AMDGPU][Uniformity][TTI] Make Uniformity Analysis Operand-Aware via Custom Uniformity Checks (#137639)
See: https://github.com/llvm/llvm-project/issues/131779
Extends uniformity analysis to support instructions whose uniformity
depends on which specific operands are uniform. Introduces
`InstructionUniformity::Custom` and a target hook `TTI::isUniform(I,
UniformArgs)` that allows targets to define custom uniformity rules.
During propagation, custom candidates are checked via the target hook.
If we can prove they are uniform, we skip marking them divergent and let
iterative propagation re-evaluate as operands change.
Implements AMDGPU's `llvm.amdgcn.wave.shuffle` rules (uniform when
either operand is uniform, divergent only when both are divergent) as
the motivating example.
This inverted-logic approach is critical for correctness: proving
uniformity early during propagation would be unsafe, as operands can
transition from uniform to divergent during divergence propagation.
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Commit: ca2bc5505c18e9a72c6f4c8f7c60d2fc5172d86b
https://github.com/llvm/llvm-project/commit/ca2bc5505c18e9a72c6f4c8f7c60d2fc5172d86b
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for ps_live (#188101)
Commit: 6159b253ef4ebf7ee8e996e94d4ba2378cf2eec3
https://github.com/llvm/llvm-project/commit/6159b253ef4ebf7ee8e996e94d4ba2378cf2eec3
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang/test/CIR/IR/invalid-linkage.cir
Log Message:
-----------
[CIR][NFC] Mark invalid-linkage.cir as XFAIL (#188279)
The invalid-linkage.cir test is currently failing as a result of a
recent change to the MLIR attribute parser. I am temporarily marking
this test as XFAIL while that problem is being worked on to unblock CIR
development. I added a check that will force the test to fail even after
the problem is fixed so that we don't start getting unexpected passes
when the fix is merged. (CIR testing isn't run during CI for MLIR
changes.) I will reenable the test after the problem has been fixed.
Commit: 3deca2dc322e0c4328da35247157b28bb4b552fc
https://github.com/llvm/llvm-project/commit/3deca2dc322e0c4328da35247157b28bb4b552fc
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/include/llvm/Support/KnownBits.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/unittests/Support/KnownBitsTest.cpp
Log Message:
-----------
[KnownBits] KnownBits::add - add optional arg indicating a X+X self add pattern (#188078)
Compute knownbits for ADD(X,X) as SHL(X,1)
Followup to #186461
Commit: 549b529225050ecf597b2e0824857f041065d465
https://github.com/llvm/llvm-project/commit/549b529225050ecf597b2e0824857f041065d465
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Target/X86/X86AsmPrinter.h
M llvm/test/CodeGen/X86/npm-asmprint.ll
Log Message:
-----------
[X86][NewPM] Mark X86AsmPrinter isRequired (#188278)
Otherwise the pass does not run when a function has the optnone
attribute, which means we get no assembly out for functions marked
optnone.
Commit: 8d8f635e4b2c669d8f84d615ddcb74e883f1d10f
https://github.com/llvm/llvm-project/commit/8d8f635e4b2c669d8f84d615ddcb74e883f1d10f
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Target/SPIRV/Analysis/SPIRVConvergenceRegionAnalysis.h
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVBaseInfo.h
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.h
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVTargetStreamer.h
M llvm/lib/Target/SPIRV/SPIRVCBufferAccess.h
M llvm/lib/Target/SPIRV/SPIRVCommandLine.h
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
M llvm/lib/Target/SPIRV/SPIRVLegalizeZeroSizeArrays.h
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.h
M llvm/lib/Target/SPIRV/SPIRVMetadata.h
M llvm/lib/Target/SPIRV/SPIRVPushConstantAccess.h
M llvm/lib/Target/SPIRV/SPIRVStructurizerWrapper.h
M llvm/lib/Target/SPIRV/SPIRVTypeInst.h
Log Message:
-----------
[NFC][SPIR-V] Fix include guard names to match file paths (#187689)
Commit: 047cd90b5efdd41655fc32f00410d69b899abd95
https://github.com/llvm/llvm-project/commit/047cd90b5efdd41655fc32f00410d69b899abd95
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang/lib/DependencyScanning/DependencyScannerImpl.cpp
R clang/test/ClangScanDeps/p1689-suppress-warnings.cppm
Log Message:
-----------
Revert "[ClangScanDeps] Do not emit warning for P1689 format" (#188179)
Reverts llvm/llvm-project#186966
Commit: 01af1528f8497c58b5390ba514eaf3244818df73
https://github.com/llvm/llvm-project/commit/01af1528f8497c58b5390ba514eaf3244818df73
Author: Jasmine Tang <jjasmine at igalia.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/test/CodeGen/NVPTX/i1-int-to-fp.ll
Log Message:
-----------
[NVPTX] Fix assumption of sm versioning (#188282)
The test case in #188118 assumes sm-90 is always available, leading to a
crash
```
# | ptxas fatal : SM version specified by .target is higher than default SM version assumed
```
This PR updates the test case to follow the check specified in
`llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-reduce.ll`,
namely `%if ptxas-sm_90 && ptxas-isa-7.8`
Commit: 95546c849ea6a2be66767879617b24f0750d7c6b
https://github.com/llvm/llvm-project/commit/95546c849ea6a2be66767879617b24f0750d7c6b
Author: Dave Lee <davelee.com at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M lldb/examples/python/formatter_bytecode.py
M lldb/test/Shell/ScriptInterpreter/Python/Inputs/FormatterBytecode/RigidArrayLLDBFormatterC.txt
M lldb/test/Shell/ScriptInterpreter/Python/Inputs/FormatterBytecode/RigidArrayLLDBFormatterSwift.txt
Log Message:
-----------
[lldb] Fix value of sig_update in formatter_bytecode.py (#188292)
Commit: 0158cd04e3a29c265d4695e25d022ba07b86be97
https://github.com/llvm/llvm-project/commit/0158cd04e3a29c265d4695e25d022ba07b86be97
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
A llvm/test/CodeGen/RISCV/fold-addi-loadstore-cpi.mir
A llvm/test/CodeGen/RISCV/sfb-merge-base-offset.ll
Log Message:
-----------
[RISCV] Merge Base Offset for SFB Pseudos (#187620)
This implements the Merge Base Offset pass for the SFB Load Pseudos.
These Pseudos are expanded after Merge Base Offset, so the pass needs to
handle them.
I also had to extend support in MergeBaseOffset to ensuring that ImmOp
could be a Constant Pool Index, which seemed to be supported in some
checks but not others.
Commit: efaf00194404f227b037ad5822e885e21a11f79b
https://github.com/llvm/llvm-project/commit/efaf00194404f227b037ad5822e885e21a11f79b
Author: Dave Lee <davelee.com at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M lldb/docs/resources/formatterbytecode.rst
Log Message:
-----------
[lldb][docs] Restore correct @update bytecode signature (#188295)
Mistakenly changed in https://github.com/llvm/llvm-project/pull/182155
Commit: 82287496072bef952bd400c335459f4fa4c750c7
https://github.com/llvm/llvm-project/commit/82287496072bef952bd400c335459f4fa4c750c7
Author: Hans Wennborg <hans at hanshq.net>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/WinCFGuard.cpp
A llvm/test/CodeGen/WinCFGuard/cfguard-alias.ll
Log Message:
-----------
[CFGuard] Consider function aliases as indirect call targets (#188223)
With vector deleting destructors, it's common to include function
aliases in vftables.
After #185653 it's become more likely that the alias gets overridden in
a different TU. It's therefore important that it's the alias itself that
goes in the control-flow guard table.
Commit: 68edb9f3c0dcb79a6222afc92d31bded7fba8449
https://github.com/llvm/llvm-project/commit/68edb9f3c0dcb79a6222afc92d31bded7fba8449
Author: Tom Hewitt <tom at tom-hewitt.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M lldb/source/Target/ProcessTrace.cpp
M lldb/unittests/Process/ProcessTraceTest.cpp
Log Message:
-----------
[lldb] Fix trace load hang (#187768)
#179799 removed the `SetPrivateState(eStateStopped)` call in
`ProcessTrace::DidAttach()`. This makes the call to
`WaitForProcessToStop` hang forever, causing the `trace load` command to
hang.
This fix reintroduces the `SetPrivateState` call so a postmortem trace
process will "stop" after being loaded, matching the logic used in
`Process::LoadCore()`.
Commit: 9fd8bc0f0eedd3d6ca2c71f90de768a7759ab44c
https://github.com/llvm/llvm-project/commit/9fd8bc0f0eedd3d6ca2c71f90de768a7759ab44c
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M compiler-rt/lib/fuzzer/FuzzerInterceptors.cpp
Log Message:
-----------
[libFuzzer] Fix -Wunused-variable when building with NDEBUG (#188301)
The variable `FuzzerInitIsRunning` is only used within `assert()`.
Follow up to #178342.
Commit: 1bad1d9c28a5619d61ec9f7ebbf34ef076e074f0
https://github.com/llvm/llvm-project/commit/1bad1d9c28a5619d61ec9f7ebbf34ef076e074f0
Author: Brian Cain <brian.cain at oss.qualcomm.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
A llvm/test/MC/Hexagon/checker-solo-cof-slots.s
A llvm/test/MC/Hexagon/elf-reloc-variants.s
A llvm/test/MC/Hexagon/packet-constraint-checks.s
A llvm/test/MC/Hexagon/reloc-data-sizes.s
A llvm/test/MC/Hexagon/reloc-tls-gd.s
Log Message:
-----------
[Hexagon] Add MC checker and relocation coverage tests (#183955)
Add tests targeting HexagonMCChecker, MC relocation encoding, and ELF
object writing:
- packet-constraint-checks.s: MCChecker packet constraint violation
detection including solo instructions, slot restrictions, and read-write
hazards. Improves HexagonMCChecker.cpp line coverage from 46.53% to
84.23%.
- checker-solo-cof-slots.s: MCChecker hardware loop restrictions and
slot overflow handling.
- reloc-tls-gd.s: MC relocation encoding for TLS GD/LD/IE/LE variants.
Improves HexagonMCCodeEmitter.cpp line coverage from 74.18% to 91.14%.
- reloc-data-sizes.s: MC relocation encoding for data-size relocations
(8/16/32-bit).
- elf-reloc-variants.s: HexagonELFObjectWriter exercising getRelocType()
paths for GOT, IE-GOT, TPREL, and PCREL relocation variants. Improves
line coverage from 10.29% to 62.87%.
Commit: 738cbb2fb472373fde9e9b7117ecd7eb54ebab5d
https://github.com/llvm/llvm-project/commit/738cbb2fb472373fde9e9b7117ecd7eb54ebab5d
Author: Brian Cain <brian.cain at oss.qualcomm.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M .mailmap
Log Message:
-----------
[mailmap] Map quicinc.com addresses to qti.qualcomm.com/oss.qualcomm.com; fix sort order (#181426)
Co-authored-by: Sam Elliott <sam at lenary.co.uk>
Commit: b6151c4f32829e036e7756167b5bceb1857df867
https://github.com/llvm/llvm-project/commit/b6151c4f32829e036e7756167b5bceb1857df867
Author: Perdixky <105138864+Perdixky at users.noreply.github.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
A clang/test/CIR/CodeGen/rtti-member-pointer.cpp
A clang/test/CIR/CodeGen/rtti-qualfn.cpp
M clang/test/CIR/CodeGen/throws.cpp
Log Message:
-----------
[CIR] Implement pointer type RTTI (#184011)
#163601
#163850
---------
Signed-off-by: Nikita B <n2h9z4 at gmail.com>
Co-authored-by: Nikita B <n2h9z4 at gmail.com>
Co-authored-by: Copilot <175728472+Copilot at users.noreply.github.com>
Commit: 993b110502d07db08114864c31f651a3f0ba9c82
https://github.com/llvm/llvm-project/commit/993b110502d07db08114864c31f651a3f0ba9c82
Author: Lei Huang <lei at ca.ibm.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang/lib/Headers/altivec.h
M clang/lib/Sema/SemaPPC.cpp
M clang/test/CodeGen/PowerPC/altivec-ct.c
M clang/test/CodeGen/PowerPC/builtins-ppc-32bit-vec-ll.c
M clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c
M clang/test/CodeGen/PowerPC/builtins-ppc-error.c
M clang/test/CodeGen/PowerPC/builtins-ppc-p8vector.c
M clang/test/CodeGen/PowerPC/builtins-ppc-p9vector.c
M clang/test/CodeGen/PowerPC/builtins-ppc-quadword-char.c
M clang/test/CodeGen/PowerPC/builtins-ppc-quadword-noi128.c
M clang/test/CodeGen/PowerPC/builtins-ppc-quadword.c
M clang/test/CodeGen/PowerPC/builtins-ppc-xl-xst.c
M clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
M clang/test/CodeGen/PowerPC/ppc-vector-compare.cpp
M clang/test/Parser/cxx-altivec-bool-128.cpp
M clang/test/Parser/cxx-altivec.cpp
A clang/test/Sema/PowerPC/ppc-dmf-mma-builtin-err.c
M clang/test/Sema/builtins-bcd-format-conversion.c
M clang/test/Sema/builtins-bcd-transform.c
M clang/test/Sema/builtins-ppc.c
Log Message:
-----------
[PowerPC] Add target feature validation for builtins in Sema (#187371)
Adds early target feature checking for PowerPC builtins during semantic
analysis, catching missing target features before code generation and
providing better error messages to users.
Assisted by AI.
Commit: 410558aa4d9d45c6131d5f826592710491bbd5e8
https://github.com/llvm/llvm-project/commit/410558aa4d9d45c6131d5f826592710491bbd5e8
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
M clang/test/CIR/CodeGen/new.cpp
Log Message:
-----------
[CIR] Use per-element zero-initialization with array new (#187760)
There was a discrepancy between the CIR and classic codegen handling of
zero-initialization of constructed objects with array new. Classic
codegen performs zero-initialization on a per-element basis, while CIR
had been inserting a single zero-initialization of the entire array
before individually constructing the elements.
This change aligns the CIR behavior with the classic codegen behavior.
Commit: dbb271961e0fea893c8595119a780d9cf33a351f
https://github.com/llvm/llvm-project/commit/dbb271961e0fea893c8595119a780d9cf33a351f
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M mlir/lib/Dialect/Tosa/Transforms/TosaReduceTransposes.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for readability-simplify-boolean-expr in TosaReduceTransposes.cpp (NFC)
Commit: 9f6d9d6a12b1b4d08bdb5642a41fe936485bd6c5
https://github.com/llvm/llvm-project/commit/9f6d9d6a12b1b4d08bdb5642a41fe936485bd6c5
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
Log Message:
-----------
[MLIR] Apply clang-tidy fixes for llvm-else-after-return in TosaOps.cpp (NFC)
Commit: 46620f84b32601e20552cf28cb626eb8d739b11e
https://github.com/llvm/llvm-project/commit/46620f84b32601e20552cf28cb626eb8d739b11e
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang/include/clang/AST/ExternalASTSource.h
M llvm/include/llvm/ADT/PointerUnion.h
M llvm/unittests/ADT/PointerUnionTest.cpp
Log Message:
-----------
Reland "[llvm][ADT] Refactor PointerUnion to use PunnedPointer. NFC." (#188242)
This reverts commit 040b7e0a1deb and re-lands the PointerUnion
refactoring from #187950, with a fix for the 32-bit crash.
The bug was in doCast: it masked with
PointerLikeTypeTraits<To>::NumLowBitsAvailable to strip tag bits, but
the old PointerIntPair-based code masked with minLowBitsAvailable() (the
minimum across all union members). When a member type's PLTT over-claims
spare low bits, the new mask was too aggressive and cleared bits
belonging to a nested PointerUnion's tag.
Concretely, on 32-bit systems, Redeclarable::DeclLink nests
LazyGenerationalUpdatePtr (LGUP) whose PLTT claims 2 spare bits (Decl*
has alignas(8) = 3 bits, minus 1). But LGUP's inner PointerUnion<Decl*,
LazyData*> only has 1 spare bit on 32-bit (alignof(LazyData) = 4 gives
LazyData* only 2 low bits, tagShift = 1). Extracting LGUP from the outer
PointerUnion cleared bit 1 (the inner PU's type tag), corrupting the
discriminator and breaking redeclaration chains.
Added new unit tests that cover this scenario, but we will want to fix
the clang side too.
Issue: #188269
---------
Co-authored-by: Claude Opus 4.6 (1M context) <noreply at anthropic.com>
Commit: 5928fc42d8e8d4992266602eaf44210a2c530253
https://github.com/llvm/llvm-project/commit/5928fc42d8e8d4992266602eaf44210a2c530253
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/test/MC/RISCV/rv32p-invalid.s
M llvm/test/MC/RISCV/rv32p-valid.s
M llvm/test/MC/RISCV/rv64p-invalid.s
M llvm/test/MC/RISCV/rv64p-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Use uimm3/4/5/6_plus1 for (P)SATI instructions. (#186541)
The encoded immediate is the number of trailing 1s in the maximum value.
Mailing list discussion has a preference to print and parse this value
plus one. https://lists.riscv.org/g/tech-p-ext/message/910
With this patch, saturating to a signed 8-bit integer would be "sati a0,
a0, 8". Previously it was "sati a0, a0, 7".
This is reflected in version 0.20 of the adoc spec here
https://github.com/riscv/riscv-p-spec/pull/226. I have updated our
RISCVUsage.rst to point to the adoc version of the spec.
Commit: 03e8fd6aa76da2b0071de57d730edf98ff50a1b8
https://github.com/llvm/llvm-project/commit/03e8fd6aa76da2b0071de57d730edf98ff50a1b8
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
M llvm/test/CodeGen/WebAssembly/load-ext.ll
Log Message:
-----------
Revert "[WebAssembly][FastISel] Fold i64 extension chains into widened loads" (#188306)
Reverts llvm/llvm-project#187934
Breaks bots.
Commit: 7712249363574068c3c5413b1ccd839f75c0e5df
https://github.com/llvm/llvm-project/commit/7712249363574068c3c5413b1ccd839f75c0e5df
Author: Matthias Springer <me at m-sp.org>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
Log Message:
-----------
[mlir][arith] Mark `arith.remsi` and `arith.remui` as conditionally speculatable (#188263)
Division by zero is undefined behavior, so these two ops cannot be pure.
This commit marks them as conditionally speculatable, similar to
`arith.divsi` and `arith.divui`.
Commit: e71da01f0f908417723a54cf8829a734a37fa173
https://github.com/llvm/llvm-project/commit/e71da01f0f908417723a54cf8829a734a37fa173
Author: Guo Chen <guochen2 at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
Log Message:
-----------
[AMDGPU][True16] add true16 pattern for cvt_pk_fp32_f8 (#180096)
Commit: 5c06541fb811eaa5aa87fa317c359506d0d8c17f
https://github.com/llvm/llvm-project/commit/5c06541fb811eaa5aa87fa317c359506d0d8c17f
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M mlir/include/mlir/Conversion/ControlFlowToSCF/ControlFlowToSCF.h
M mlir/include/mlir/Transforms/CFGToSCF.h
M mlir/lib/Conversion/ControlFlowToSCF/ControlFlowToSCF.cpp
M mlir/lib/Transforms/Utils/CFGToSCF.cpp
A mlir/test/Conversion/ControlFlowToSCF/invalid.mlir
M mlir/test/Conversion/ControlFlowToSCF/unknown-cf-op.mlir
Log Message:
-----------
[mlir][CFGToSCF] Fix crash when region contains unconvertible multi-successor op (#183935)
`transformCFGToSCF` would crash with a use-list assertion when it
encountered an op like `spirv.BranchConditional` that implements
`BranchOpInterface` (passing the existing precondition checks) but is
not handled by `createStructuredBranchRegionOp`. The algorithm mutated
the IR significantly before discovering the op was unsupported, leaving
it in a corrupt half-transformed state that triggered the assertion on
teardown.
Fix by adding `canConvertBranchOp` to `CFGToSCFInterface` (default:
accept all ops) and calling it inside `checkTransformationPreconditions`
for every block with more than one successor, before any IR
modifications are made. `ControlFlowToSCFTransformation` overrides the
method to accept only `cf.cond_br` and `cf.switch`.
Fixes #173566
Assisted-by: Claude Code
Commit: 52296eab79f628a6565e2d6746dc1aea078fc336
https://github.com/llvm/llvm-project/commit/52296eab79f628a6565e2d6746dc1aea078fc336
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/AArch64/rem-by-const.ll
M llvm/test/CodeGen/LoongArch/lasx/issue170976.ll
Log Message:
-----------
[TargetLowering] In BuildSDIV, avoid creating build_vector with illegal scalar types after type legalization. (#188280)
Code is based on a similar code in BuildUDIV.
Commit: 35e958d7f0b7e381d83b055607c31f3f1e3124a9
https://github.com/llvm/llvm-project/commit/35e958d7f0b7e381d83b055607c31f3f1e3124a9
Author: Susan Tan (ス-ザン タン) <zujunt at nvidia.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
M flang/test/Lower/OpenACC/acc-declare.f90
Log Message:
-----------
[openacc][flang] Avoid attaching declare post-actions to acc.terminator (#188157)
Fix lowering so post declare-actions are not attached to acc.terminator
(step back from trailing fir.result/acc.terminator before attaching).
---------
Co-authored-by: Slava Zakharin <szakharin at nvidia.com>
Commit: 0692bd52cb3f7a3c4b27cd788746e8085484792f
https://github.com/llvm/llvm-project/commit/0692bd52cb3f7a3c4b27cd788746e8085484792f
Author: Oleksandr Tarasiuk <oleksandr.tarasiuk at outlook.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaStmtAttr.cpp
M clang/test/Sema/code_align.c
Log Message:
-----------
[Clang] fix crash in duplicate attribute checking (#188274)
Fixes #188259
---
This PR fixes a crash in duplicate attribute checking when arguments
have different integer signedness. It changes the check to use
`isSameValue` (which uses `compareValues`) instead of `llvm::APSInt`
equality.
Commit: cd1a598d8677cd33a8c41c83f45c4381ebeb143e
https://github.com/llvm/llvm-project/commit/cd1a598d8677cd33a8c41c83f45c4381ebeb143e
Author: Richard Howell <rmaz at users.noreply.github.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
A llvm/test/tools/llvm-lipo/remove.test
M llvm/tools/llvm-lipo/LipoOpts.td
M llvm/tools/llvm-lipo/llvm-lipo.cpp
Log Message:
-----------
[lipo] add -remove flag (#188275)
Add the -remove flag to llvm-lipo. This matches the existing Darwin lipo
tool:
```
% xcrun lipo 2>&1 | grep remove
error: /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/bin/lipo: one of -create, -thin <arch_type>, -extract <arch_type>, -remove <arch_type>, -replace <arch_type> <file_name>, -verify_arch <arch_type> ... , -archs, -info, or -detailed_info must be specified
-remove <arch_type> [-remove <arch_type> ...]
```
Assisted-by: claude-code
Commit: 55bbf7b16b9467e86081cd0eb54935f717f60081
https://github.com/llvm/llvm-project/commit/55bbf7b16b9467e86081cd0eb54935f717f60081
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
M llvm/test/CodeGen/WebAssembly/load-ext.ll
Log Message:
-----------
Reland "[WebAssembly][FastISel] Fold i64 extension chains into widened loads" (#188324)
Reverts llvm/llvm-project#188306
Relands llvm/llvm-project#187934
It was reverted by mistake.
Commit: 7bfd54ac2548a3161e6237621e57a8406bf94964
https://github.com/llvm/llvm-project/commit/7bfd54ac2548a3161e6237621e57a8406bf94964
Author: vporpo <vasileios.porpodas at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/InstrMaps.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
M llvm/test/Transforms/SandboxVectorizer/external_uses.ll
M llvm/test/Transforms/SandboxVectorizer/scheduler.ll
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/InstrMapsTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
Log Message:
-----------
[SandboxVec][BottomUpVec] Improve handling of external uses (#185468)
Up until now the bottom-up vectorizer pass would not delete the scalar
instructions that have external uses after being vectorized, because it
lacked the ability to generate extracts from the vectors.
With the term "external uses", we refer to uses outside the currently
vectorized graph.
This patch fixes this. We can now properly handle external uses by
extracting from the vectors.
This change relies on the recent changes to the DAG's callbacks because
the external user may not be within the current DAG's interval.
Commit: 2ae3d8ae57004e6cfb2673083289660d8cfc2dac
https://github.com/llvm/llvm-project/commit/2ae3d8ae57004e6cfb2673083289660d8cfc2dac
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/include/llvm/CodeGen/ExpandPostRAPseudos.h
A llvm/test/CodeGen/X86/post-ra-pseudos.mir
Log Message:
-----------
[CodeGen][NewPM] Mark ExpandPostRAPseudos as required (#188304)
We need to lower these pseudoinstructions regardless of optimization
level or we end up with instructions that we cannot print.
Commit: daec3b9fb6e2192febfbd29046e02e476a5b159f
https://github.com/llvm/llvm-project/commit/daec3b9fb6e2192febfbd29046e02e476a5b159f
Author: Deric C. <cheung.deric at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
A clang/include/clang/Basic/HLSLIntrinsics.td
M clang/lib/Headers/CMakeLists.txt
M clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
A clang/test/TableGen/hlsl-intrinsics.td
M clang/utils/TableGen/CMakeLists.txt
A clang/utils/TableGen/HLSLEmitter.cpp
M clang/utils/TableGen/TableGen.cpp
M clang/utils/TableGen/TableGenBackends.h
Log Message:
-----------
[HLSL] Implement TableGen for builtin HLSL intrinsics (#187610)
This PR introduces a TableGen-based code generation system for HLSL
intrinsic overloads as described in proposal
[[0043]](https://github.com/llvm/wg-hlsl/blob/main/proposals/0043-hlsl-intrinsic-tablegen.md)
for replacing hand-written boilerplate with declarative .td definitions.
Actual changes to `hlsl_intrinsics.h` and `hlsl_alias_intrinsics.h` to
replace handwritten HLSL intrinsic overloads with TableGen is left to
follow-up PRs.
Assisted-by: GitHub Copilot (powered by Claude Opus 4.6)
Commit: 6ef30612ee6d69d0a5658ec0d2f78b6a09a4aa0d
https://github.com/llvm/llvm-project/commit/6ef30612ee6d69d0a5658ec0d2f78b6a09a4aa0d
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M lldb/source/Target/ProcessTrace.cpp
Log Message:
-----------
[lldb][trace] Ensure ProcessTrace plugin can be re-registered (#188336)
Initialize makes sure that it calls RegisterPlugin only once, but
Terminate always calls UnregisterPlugin. This is a problem for tests
that call Initialize/Terminate before and after each test case: the
second case will fail because the trace plugin won't be loaded.
This fixes a test failure introduced by #187768, which adds a test case
that passes on its own but fails when run after the previous test case.
Commit: 4e290b34294cd6de562385bc8c5f8af457aeb46a
https://github.com/llvm/llvm-project/commit/4e290b34294cd6de562385bc8c5f8af457aeb46a
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libc/src/string/memory_utils/utils.h
Log Message:
-----------
[libc][strings] Refactor load_aligned for cleaner endianness handling (#186360)
Replace the explicit `if constexpr` branching for big and little
endianness with compile-time calculated shift constants `VAL_SHIFT` and
`NEXT_SHIFT`. This simplifies the logic and reduces code duplication,
relying on the compiler to constant-fold the zero shifts into no-ops.
Commit: 11bc6e8776d233a98b573d5c8b08cfb4e5c3ab61
https://github.com/llvm/llvm-project/commit/11bc6e8776d233a98b573d5c8b08cfb4e5c3ab61
Author: zGoldthorpe <Zach.Goldthorpe at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
Log Message:
-----------
[SelectionDAG] Add known bit for `ISD::FABS` (#188335)
Absolute value always clears the sign bit, so make that knowh to
selectionDAG's `computeKnownBits`.
Commit: 13b2ee25aebc937c0f459ca38c2092b882bec9dc
https://github.com/llvm/llvm-project/commit/13b2ee25aebc937c0f459ca38c2092b882bec9dc
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang/include/clang/AST/ExternalASTSource.h
Log Message:
-----------
[clang][AST] Fix LazyGenerationalUpdatePtr NumLowBitsAvailable on 32-bit (#188318)
The `PointerLikeTypeTraits` for `LazyGenerationalUpdatePtr` claimed
`PointerLikeTypeTraits<T>::NumLowBitsAvailable - 1` spare low bits. This
assumed that the inner `PointerUnion<T, LazyData*>` has `T_bits - 1`
spare bits, which is only true when `alignof(LazyData) >= alignof(*T)`.
On 32-bit systems, `LazyData` (containing pointers and `uint32_t`) has
`alignof = 4`, giving `LazyData*` only 2 low bits. With `T = Decl*` (3
bits due to `alignas(8)`), the inner `PointerUnion` has `min(3,2) - 1 =
1` spare bit, but the PLTT claimed `3 - 1 = 2`.
Historically, the formula was correct when introduced in 053f6c6c9e4d --
at that time `Decl` had no alignment annotation, so `T_bits ==
LazyData*_bits` on all platforms. It became outdated when 771721cb35f3
added `LLVM_ALIGNAS(8)` to `Decl`, raising `Decl*` to 3 bits on 32-bit
while `LazyData*` stayed at 2. The old `PointerIntPair`-based
`PointerUnion::doCast` happened to mask with `minLowBitsAvailable()`
(tolerant of overclaims), so this was never exposed until the
`PunnedPointer` refactoring changed `doCast` to mask with
`To::NumLowBitsAvailable`.
Fixes: https://github.com/llvm/llvm-project/issues/188269
Co-authored-by: Claude Opus 4.6 (1M context) <noreply at anthropic.com>
Commit: e3c6244f6e7ce9c76274f9ebca7b6a1f1fcec781
https://github.com/llvm/llvm-project/commit/e3c6244f6e7ce9c76274f9ebca7b6a1f1fcec781
Author: Lang Hames <lhames at gmail.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/EPCGenericJITLinkMemoryManager.h
M llvm/lib/ExecutionEngine/Orc/EPCGenericJITLinkMemoryManager.cpp
M llvm/unittests/ExecutionEngine/Orc/EPCGenericJITLinkMemoryManagerTest.cpp
Log Message:
-----------
[ORC] Add EPCGenericJITLinkMemoryManager::Create named constructor. (#188191)
Create takes a JITDylib and a SymbolNames struct, looks up the
implementation symbol addresses in the given JITDylib, and uses them to
construct an EPCGenericJITLinkMemoryManager instance. This makes it
easier for ORC clients to construct the memory manager from named
symbols (e.g. in a bootstrap JITDylib) rather than raw addresses.
Commit: fe286356ca34a530f8a6ccf0b630fc32fc69fc44
https://github.com/llvm/llvm-project/commit/fe286356ca34a530f8a6ccf0b630fc32fc69fc44
Author: Mircea Trofin <mtrofin at google.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
A llvm/test/Transforms/JumpThreading/update-bpi-bfi-unfold-select.ll
Log Message:
-----------
[JT] `tryToUnfoldSelectInCurrBB` should update BFI & BPI if present (#188097)
Issue #187545
Commit: 642bde76c32e38457a0b30644763f1447523cff5
https://github.com/llvm/llvm-project/commit/642bde76c32e38457a0b30644763f1447523cff5
Author: Jinsong Ji <jinsong.ji at intel.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/order-reduction-infinite-loop.ll
Log Message:
-----------
[SLP] Fix infinite loop in ordered reduction worklist processing (#188342)
The ordered reduction support introduced in 94e366ef2060 can cause an
infinite loop when processing complex reduction chains. The worklist
algorithm re-adds instructions from PossibleOrderedReductionOps when
switching to ordered mode, but doesn't track which instructions have
already been processed. This allows instructions to be re-added and
processed multiple times, creating cycles.
Add a Visited set to track processed instructions and skip any that
have already been handled, preventing the infinite loop.
Commit: 674cb9e3f18a6e428d611f39e7f5a99537afb5b6
https://github.com/llvm/llvm-project/commit/674cb9e3f18a6e428d611f39e7f5a99537afb5b6
Author: satyanarayana reddy janga <satyajanga at fb.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
Log Message:
-----------
[lldb] Fix immediately-destroyed ScopedTimeout in KillProcess (#188333)
The ScopedTimeout was created as a temporary, causing it to be destroyed
immediately and the timeout to have no effect. Give it a name so it
lives until the end of the function scope.
Commit: 6b128091ba87ec711e11ed34b2810ff5deb8cef4
https://github.com/llvm/llvm-project/commit/6b128091ba87ec711e11ed34b2810ff5deb8cef4
Author: Sirraide <aeternalmail at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang/test/InstallAPI/extra-exclude-headers.test
M clang/test/InstallAPI/hiddens.test
Log Message:
-----------
[InstallAPI] [Tests] Avoid checking compiler output for 'error' (#188307)
We have two tests that use FileCheck for diagnostics and which try to
check that the output contains no compiler errors by checking for the
string 'error'. The issue with this approach is that this also causes
those tests to fail if the *path* contains the word 'error', which can
happen e.g. if the branch name contains the word 'error'.
Instead, we now check for `error:` since that string is much less likely
to appear in a path.
Commit: 6a045c29a98ce371d05ed2cf66fb04c33dc0691f
https://github.com/llvm/llvm-project/commit/6a045c29a98ce371d05ed2cf66fb04c33dc0691f
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/include/llvm/CodeGen/LowLevelTypeUtils.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/CodeGenTypes/LowLevelType.h
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/LowLevelTypeUtils.cpp
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGenTypes/LowLevelType.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-subvector.ll
M llvm/test/CodeGen/AArch64/GlobalISel/pr168872.ll
M llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
M llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument-multiple.ll
M llvm/test/CodeGen/AArch64/GlobalISel/translate-sve-formal-argument.ll
M llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid0.mir
M llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid1.mir
M llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid2.mir
M llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid3.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err0.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err1.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err10.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err11.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err12.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err13.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err14.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err15.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err2.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err3.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err4.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err5.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err6.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err7.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err8.mir
M llvm/test/CodeGen/MIR/Generic/scalable-vector-type-err9.mir
M llvm/test/CodeGen/MIR/WebAssembly/typed-immediate-operand-invalid0.mir
M llvm/test/CodeGen/MIR/WebAssembly/typed-immediate-operand-invalid1.mir
M llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
M llvm/test/TableGen/GlobalISelEmitter/HwModes.td
M llvm/unittests/CodeGen/GlobalISel/CMakeLists.txt
R llvm/unittests/CodeGen/GlobalISel/IRTranslatorBF16Test.cpp
M llvm/utils/TableGen/Common/CMakeLists.txt
M llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
M llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTableExecutorEmitter.cpp
M llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTableExecutorEmitter.h
Log Message:
-----------
Revert "[GlobalISel][LLT] Introduce FPInfo for LLT (Enable bfloat, ppc128float and others in GlobalISel) (#155107)" (#188344)
This reverts commit b1aa6a45060bb9f89efded9e694503d6b4626a4a and commit
ce44d63e0d14039f1e8f68e6b7c4672457cabd4e.
This fails the build with some older gcc:
llvm/include/llvm/CodeGenTypes/LowLevelType.h:501:35: error: call to
non-constexpr function ‘static llvm::LLT llvm::LLT::integer(unsigned
int)’
return integer(getSizeInBits());
^
Commit: de0c366e4b7224f33d2945194035d21501e3d636
https://github.com/llvm/llvm-project/commit/de0c366e4b7224f33d2945194035d21501e3d636
Author: Alex Duran <alejandro.duran at intel.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/SPIRV.h
A llvm/lib/Target/SPIRV/SPIRVCtorDtorLowering.cpp
A llvm/lib/Target/SPIRV/SPIRVCtorDtorLowering.h
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
A llvm/test/CodeGen/SPIRV/ctor-dtor-lowering-ir.ll
A llvm/test/CodeGen/SPIRV/ctor-dtor-lowering.ll
A llvm/test/CodeGen/SPIRV/ctor-dtor-no-openmp-ir.ll
M llvm/test/CodeGen/SPIRV/llc-pipeline.ll
Log Message:
-----------
[llvm][SPIRV] Add pass to lower Ctors/Dtors for SPIRV (#187509)
This PR adds a new SPIRV pass that generates a kernel named
"spirv$device$init" that iterates the pointers in the table pointed by
__init_array_start and __init_array_end and executes them. It also
generates symbols for each constructor with the form
__init_array_object_NAME_PRIORITY.
These symbols will be used by the Level Zero plugin in the liboffload
runtime (with the support introduced by #187510) to generate the
aforementioned table as spirv-link cannot create the table itself.
It also does the same thing for destructors, with the kernel name being
"spirv$device$fini", the table pointers __fini_array_start and
__fini_array_end, and the generated symbols prefix __fini_array_object.
The code was mostly generated by Claude 4.5 and has been reviewed by me
to the best of my ability.
Commit: 31b17c4789abc2504cfe3b3f05feebafc0e88dc8
https://github.com/llvm/llvm-project/commit/31b17c4789abc2504cfe3b3f05feebafc0e88dc8
Author: Amir Ayupov <aaupov at fb.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M bolt/docs/index.rst
A bolt/docs/profiles.md
Log Message:
-----------
[BOLT] Add profile format documentation (#186685)
Create bolt/docs/profiles.md documenting all accepted profile formats:
perf.data, fdata, YAML, and pre-aggregated. Covers collection methods,
format syntax, examples, and known limitations.
Add reference from bolt/docs/index.rst.
Commit: fce6895804e596f18765c4db0f76931dac8df9f8
https://github.com/llvm/llvm-project/commit/fce6895804e596f18765c4db0f76931dac8df9f8
Author: Amir Ayupov <aaupov at fb.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Profile/DataAggregator.cpp
Log Message:
-----------
[BOLT] Support buildid in pre-aggregated profile
Sample addresses belonging to external DSOs (buildid doesn't match the
current file) are treated as external (0).
Buildid for the main binary is expected to be omitted.
Test Plan: added pre-aggregated-perf-buildid.test
Reviewers:
paschalis-mpeis, maksfb, yavtuk, ayermolo, yozhu, rafaelauler, yota9
Reviewed By: paschalis-mpeis
Pull Request: https://github.com/llvm/llvm-project/pull/186931
Commit: 2975451a70fbd4b35cc790294ee7ed46970a253b
https://github.com/llvm/llvm-project/commit/2975451a70fbd4b35cc790294ee7ed46970a253b
Author: Dave Lee <davelee.com at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbtest.py
Log Message:
-----------
[lldb] Mark lldbtest.build() parameters as keyword-only (#188327)
This reinforces what is already true in the codebase: all uses of
`build()` use keyword arguments.
With this change, it will be an error to call `build` using positional
arguments:
```
TypeError: build() takes 1 positional argument but 2 were given
```
Commit: 2e247a1d54ff9a3ae73d16fd1d70fca6f7169c7e
https://github.com/llvm/llvm-project/commit/2e247a1d54ff9a3ae73d16fd1d70fca6f7169c7e
Author: Amir Ayupov <aaupov at fb.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/lib/Profile/DataAggregator.cpp
Log Message:
-----------
Revert "[BOLT] Support buildid in pre-aggregated profile"
Accidentally pushed unreviewed version.
This reverts commit fce6895804e596f18765c4db0f76931dac8df9f8.
Commit: 2fafeb0509f972c70c5e1dc6d4ac466c52d25591
https://github.com/llvm/llvm-project/commit/2fafeb0509f972c70c5e1dc6d4ac466c52d25591
Author: Amir Ayupov <aaupov at fb.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/include/bolt/Profile/DataReader.h
M bolt/lib/Profile/DataAggregator.cpp
A bolt/test/X86/Inputs/pre-aggregated-buildid.txt
A bolt/test/X86/pre-aggregated-perf-buildid.test
Log Message:
-----------
[BOLT] Support buildid in pre-aggregated profile (#186931)
Sample addresses belonging to external DSOs (buildid doesn't match the
current file) are treated as external (0).
Buildid for the main binary is expected to be omitted.
Test Plan:
added pre-aggregated-perf-buildid.test
Commit: 303afa0899357b21a6a325115068108aa5e71a4f
https://github.com/llvm/llvm-project/commit/303afa0899357b21a6a325115068108aa5e71a4f
Author: Zyn <103019185+zyn-li at users.noreply.github.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.h
A lldb/test/API/lang/cpp/non-type-template-param-member-ptr/Makefile
A lldb/test/API/lang/cpp/non-type-template-param-member-ptr/TestCppNonTypeTemplateParamPtrToMember.py
A lldb/test/API/lang/cpp/non-type-template-param-member-ptr/main.cpp
Log Message:
-----------
[lldb][DWARFASTParserClang] Handle pointer-to-member-data non-type template (#187598)
## Description
### Problem
MakeAPValue in DWARFASTParserClang.cpp did not handle
pointer-to-member-data non-type template parameters (e.g., template <int
S::*P>), causing LLDB to produce incorrect results or crash.
DWARF encodes pointer-to-member-data NTTPs as
`DW_TAG_template_value_parameter` with a `DW_AT_const_value`
representing the byte offset of the member within the containing struct.
MakeAPValue is responsible for converting this value into a clang
APValue, but it only handled integer/enum and floating-point types. For
pointer-to-member types, it returned `std::nullopt`.
This caused the caller (ParseTemplateDIE) to fall back to creating a
type-only TemplateArgument (kind=Type) instead of a value-carrying one.
When two specializations differ only by which member they point to
(e.g., MemberData<&S::x> / MemberData<&S::y>), both produce identical
TemplateArguments. Clang's
[findSpecialization](https://github.com/llvm/llvm-project/blob/3bc216c29cb42c7d94b617943b1d44afce605588/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp#L1674-L1677)
then treats the second as a duplicate, so only one specialization exists
in the AST. The second variable becomes unresolvable.
(See Debugger Evidence section below)
In more complex cases, this triggers an assertion failure in
[clang::CXXRecordDecl::setBases():
cast()](https://github.com/llvm/llvm-project/blob/3bc216c29cb42c7d94b617943b1d44afce605588/clang/lib/AST/DeclCXX.cpp#L219)
argument of incompatible type.
## Fix
MakeAPValue: Added `IsMemberDataPointerType()` to the integral type
check so that pointer-to-member byte offsets produce distinct APValues.
Also replaced the silent return `std::nullopt` for unsupported types
with `lldbassert` so unknown type classes are caught during development.
`ResolveMemberDataPointerToFieldDecl`: New method that follows the DWARF
chain to resolve the byte offset to the actual FieldDecl, creating
TemplateArgument(Declaration) matching clang's own AST:
DW_TAG_template_value_parameter (DW_AT_type)
→ DW_TAG_ptr_to_member_type (DW_AT_containing_type)
→ DW_TAG_structure_type → match DW_TAG_member by byte offset
If resolution fails at any step, falls through to the integer APValue
path as a safe fallback.
Verified by comparing clang's AST (clang -Xclang -ast-dump) with LLDB's
reconstructed AST (image dump ast) — both now produce TemplateArgument
decl '&S::x' referencing the correct FieldDecl.
## Test Plan
Added `lldb/test/API/lang/cpp/non-type-template-param-member-ptr/` with
a test that creates two specializations (MemberData<&S::x> and
MemberData<&S::y>) and verifies both are resolvable with correct type
names.
```
| |-ClassTemplateSpecializationDecl 0x234e2314800 <line:18:1, line:21:1> line:19:8 struct MemberData definition instantiated_from 0x234e2314110 implicit_instantiation
| | |-DefinitionData pass_in_registers empty aggregate standard_layout trivially_copyable pod trivial literal has_constexpr_non_copy_move_ctor can_const_default_init
| | | |-DefaultConstructor exists trivial constexpr defaulted_is_constexpr
--
| | |-TemplateArgument decl '&S::x'
| | | `-Field 0x234e2313ed0 'x' 'int'
| | |-CXXRecordDecl 0x234e2314ac0 <col:1, col:8> col:8 implicit struct MemberData
--
| `-ClassTemplateSpecializationDecl 0x234e25b5968 <line:18:1, line:21:1> line:19:8 struct MemberData definition instantiated_from 0x234e2314110 implicit_instantiation
| |-DefinitionData pass_in_registers empty aggregate standard_layout trivially_copyable pod trivial literal has_constexpr_non_copy_move_ctor can_const_default_init
| | |-DefaultConstructor exists trivial constexpr defaulted_is_constexpr
--
| |-TemplateArgument decl '&S::y'
| | `-Field 0x234e2313f38 'y' 'int'
| |-CXXRecordDecl 0x234e25b5bd8 <col:1, col:8> col:8 implicit struct MemberData
--
| |-ClassTemplateSpecializationDecl 0x234e25b7080 <line:27:1, line:30:1> line:28:8 struct MaybeNull definition instantiated_from 0x234e25b6b50 implicit_instantiation
| | |-DefinitionData pass_in_registers empty aggregate standard_layout trivially_copyable pod trivial literal has_constexpr_non_copy_move_ctor can_const_default_init
| | | |-DefaultConstructor exists trivial constexpr defaulted_is_constexpr
--
| `-ClassTemplateSpecializationDecl 0x234e25b80c0 <line:27:1, line:30:1> line:28:8 struct MaybeNull definition instantiated_from 0x234e25b6b50 implicit_instantiation
| |-DefinitionData pass_in_registers empty aggregate standard_layout trivially_copyable pod trivial literal has_constexpr_non_copy_move_ctor can_const_default_init
| | |-DefaultConstructor exists trivial constexpr defaulted_is_constexpr
--
| |-TemplateArgument decl '&g1'
| | `-Var 0x234e25b69b8 'g1' 'int'
| |-CXXRecordDecl 0x234e25b8338 <col:1, col:8> col:8 implicit struct MaybeNull
```
```
lldb a.out -o "type lookup MemberData<&S::x>" -o "type lookup MemberData<&S::y>" -o quit
(lldb) target create "a.out"
Current executable set to 'a.out' (x86_64).
(lldb) type lookup MemberData<&S::x>
template<> struct MemberData<&S::x> {
int get(S &);
}
(lldb) type lookup MemberData<&S::y>
template<> struct MemberData<&S::y> {
int get(S &);
}
```
## **Debugger Evidence**
Collected at two `DW_TAG_template_value_parameter` DIEs during
ParseTemplateDIE, both with name="PtrToMember" and `type_class=256`
(eTypeClassMemberPointer): DIE `0xcb: uval64=8`; DIE `0x1e9 : uval64=24`
These correspond to two members of Fiber:
```
DW_TAG_member "listHook_" DW_AT_data_member_location(0x08) ← uval64=8
DW_TAG_member "globalListHook_" DW_AT_data_member_location(0x18) ← uval64=24
```
Clang's ground truth AST correctly produces TemplateArgument decl
(kind=Declaration) with distinct FieldDecl references for each
specialization.
```
22:| | |-ClassTemplateSpecializationDecl 0x36d785b7cc0 <line:43:1, line:56:1> line:44:8 struct mhtraits definition instantiated_from 0x36d785b4238 implicit_instantiation
23-| | | |-DefinitionData pass_in_registers empty aggregate standard_layout trivially_copyable pod trivial literal has_constexpr_non_copy_move_ctor can_const_default_init
24-| | | | |-DefaultConstructor exists trivial constexpr defaulted_is_constexpr
25-| | | | |-CopyConstructor simple trivial has_const_param implicit_has_const_param
26-| | | | |-MoveConstructor exists simple trivial
27-| | | | |-CopyAssignment simple trivial has_const_param needs_implicit implicit_has_const_param
28-| | | | |-MoveAssignment exists simple trivial needs_implicit
29-| | | | `-Destructor simple irrelevant trivial
30-| | | |-TemplateArgument type 'intrusive::Fiber'
31-| | | | `-RecordType 0x36d785b3fb0 'intrusive::Fiber' canonical
32-| | | | `-CXXRecord 0x36d78344850 'Fiber'
33-| | | |-TemplateArgument type 'intrusive::list_member_hook<>'
34-| | | | `-RecordType 0x36d785b3c20 'intrusive::list_member_hook<>' canonical
35-| | | | `-ClassTemplateSpecialization 0x36d78344b48 'list_member_hook'
36-| | | |-TemplateArgument decl '&intrusive::Fiber::listHook_'
37-| | | | `-Field 0x36d785b3e70 'listHook_' 'list_member_hook<>':'intrusive::list_member_hook<>'
38-| | | |-CXXRecordDecl 0x36d785b93a0 <col:1, col:8> col:8 implicit struct mhtraits
39-| | | |-TypeAliasDecl 0x36d785b9470 <line:45:3, col:22> col:9 referenced value_type 'intrusive::Fiber'
40-| | | | `-SubstTemplateTypeParmType 0x36d785b9430 'intrusive::Fiber' sugar typename depth 0 index 0 T
41-| | | | |-ClassTemplateSpecialization 0x36d785b7cc0 'mhtraits'
42-| | | | `-RecordType 0x36d785b3fb0 'intrusive::Fiber' canonical
--
78:| | `-ClassTemplateSpecializationDecl 0x36d785b8210 <line:43:1, line:56:1> line:44:8 struct mhtraits definition instantiated_from 0x36d785b4238 implicit_instantiation
79-| | |-DefinitionData pass_in_registers empty aggregate standard_layout trivially_copyable pod trivial literal has_constexpr_non_copy_move_ctor can_const_default_init
80-| | | |-DefaultConstructor exists trivial constexpr defaulted_is_constexpr
81-| | | |-CopyConstructor simple trivial has_const_param implicit_has_const_param
82-| | | |-MoveConstructor exists simple trivial
83-| | | |-CopyAssignment simple trivial has_const_param needs_implicit implicit_has_const_param
84-| | | |-MoveAssignment exists simple trivial needs_implicit
85-| | | `-Destructor simple irrelevant trivial
86-| | |-TemplateArgument type 'intrusive::Fiber'
87-| | | `-RecordType 0x36d785b3fb0 'intrusive::Fiber' canonical
88-| | | `-CXXRecord 0x36d78344850 'Fiber'
89-| | |-TemplateArgument type 'intrusive::list_member_hook<>'
90-| | | `-RecordType 0x36d785b3c20 'intrusive::list_member_hook<>' canonical
91-| | | `-ClassTemplateSpecialization 0x36d78344b48 'list_member_hook'
92-| | |-TemplateArgument decl '&intrusive::Fiber::globalListHook_'
93-| | | `-Field 0x36d785b3f60 'globalListHook_' 'list_member_hook<>':'intrusive::list_member_hook<>'
94-| | |-CXXRecordDecl 0x36d785be080 <col:1, col:8> col:8 implicit struct mhtraits
95-| | |-TypeAliasDecl 0x36d785be150 <line:45:3, col:22> col:9 referenced value_type 'intrusive::Fiber'
96-| | | `-SubstTemplateTypeParmType 0x36d785be110 'intrusive::Fiber' sugar typename depth 0 index 0 T
97-| | | |-ClassTemplateSpecialization 0x36d785b8210 'mhtraits'
98-| | | `-RecordType 0x36d785b3fb0 'intrusive::Fiber' canonical
```
### **Full Paste**
```
$ llvm-dwarfdump --debug-info=0x000000cb repro.dwp -c -p
repro.dwp: file format elf64-x86-64
.debug_info.dwo contents:
0x00000014: DW_TAG_compile_unit
DW_AT_producer ("clang version 22.1.20 ...)
DW_AT_language (DW_LANG_C_plus_plus_14)
DW_AT_name ("repro.cpp")
DW_AT_dwo_name ("repro-repro.dwo")
0x0000001a: DW_TAG_namespace
DW_AT_name ("intrusive")
0x000000b9: DW_TAG_structure_type
DW_AT_calling_convention (DW_CC_pass_by_value)
DW_AT_name ("mhtraits<intrusive::Fiber, intrusive::list_member_hook<(intrusive::link_mode_type)2>, &intrusive::Fiber::listHook_>")
DW_AT_byte_size (0x01)
DW_AT_decl_file (0x00)
DW_AT_decl_line (44)
0x000000cb: DW_TAG_template_value_parameter
DW_AT_type (0x0000022d "intrusive::list_member_hook<(intrusive::link_mode_type)2> intrusive::Fiber::*")
DW_AT_name ("PtrToMember")
DW_AT_const_value (8)
```
lldb prints:
```
p name
(const char *) 0x000055f44554c4ca "PtrToMember"
p uval64
(uint64_t) 8
p (unsigned)clang_type.GetTypeClass()
(unsigned int) 256
```
```
$ llvm-dwarfdump --debug-info=0x000001e9 repro.dwp -c -p
repro.dwp: file format elf64-x86-64
.debug_info.dwo contents:
0x00000014: DW_TAG_compile_unit
DW_AT_producer ("clang version 22.1.20")
DW_AT_language (DW_LANG_C_plus_plus_14)
DW_AT_name ("repro.cpp")
DW_AT_dwo_name ("repro-repro.dwo")
0x0000001a: DW_TAG_namespace
DW_AT_name ("intrusive")
0x000001d7: DW_TAG_structure_type
DW_AT_calling_convention (DW_CC_pass_by_value)
DW_AT_name ("mhtraits<intrusive::Fiber, intrusive::list_member_hook<(intrusive::link_mode_type)2>, &intrusive::Fiber::globalListHook_>")
DW_AT_byte_size (0x01)
DW_AT_decl_file (0x00)
DW_AT_decl_line (44)
0x000001e9: DW_TAG_template_value_parameter
DW_AT_type (0x0000022d "intrusive::list_member_hook<(intrusive::link_mode_type)2> intrusive::Fiber::*")
DW_AT_name ("PtrToMember")
DW_AT_const_value (24)
```
lldb prints:
```
p name
(const char *) 0x000055f44554c4ca "PtrToMember"
p uval64
(uint64_t) 24
p (unsigned)clang_type.GetTypeClass()
(unsigned int) 256
```
Commit: c3d69eda36f10488512bf2ca4295fc07d096b489
https://github.com/llvm/llvm-project/commit/c3d69eda36f10488512bf2ca4295fc07d096b489
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M mlir/lib/Transforms/Mem2Reg.cpp
M mlir/test/Dialect/LLVMIR/mem2reg.mlir
Log Message:
-----------
[mlir][mem2reg] Process direct uses inside other regions. (#188359)
We need to add the regions with the direct uses into the list
for processing, otherwise the direct uses will not be removed
and will use the slot after the promotion.
The added LIT test was triggering "after promotion, the slot pointer
should not be used anymore" assertion.
Commit: 30084d74765c70e9cab4f11e9f2c29f141df299e
https://github.com/llvm/llvm-project/commit/30084d74765c70e9cab4f11e9f2c29f141df299e
Author: Peter Collingbourne <pcc at google.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libcxx/include/ext/hash_map
A libcxx/test/extensions/gnu/hash_map/non_standard_layout.pass.cpp
A libcxx/test/extensions/gnu/hash_multimap/non_standard_layout.pass.cpp
Log Message:
-----------
[libc++] Fix type confusion in hash_{,multi}map
The type `__gnu_cxx::hash_{,multi}map` creates objects of type
`std::pair<Key, Value>` and returns pointers to them of type
`std::pair<const Key, Value>`. If either `Key` or `Value` are
non-standard-layout, this is UB, and is furthermore considered by
pointer field protection to be a type confusion, which leads to a
program crash. Fix it by using the correct type for the pair's storage
and using const_cast to form a pointer to the key in the one place where
that is needed.
Reviewers: ldionne
Reviewed By: ldionne
Pull Request: https://github.com/llvm/llvm-project/pull/183223
Commit: 2a7b0f06d2060dbab8fa38fae7689f2d9048fa9d
https://github.com/llvm/llvm-project/commit/2a7b0f06d2060dbab8fa38fae7689f2d9048fa9d
Author: Charlie Li <git at vishwin.info>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M lldb/bindings/python/python-wrapper.swig
Log Message:
-----------
[lldb] use the Py_REFCNT() macro instead of directly accessing member (#188161)
[PyObject members are not to be accessed
directly](https://docs.python.org/3/c-api/structures.html#c.PyObject),
but rather through macros, in this case `Py_REFCNT()`.
In most, ie Global Interpreter Lock-enabled, CPython cases,
`Py_REFCNT()` expands to accessing `ob_refcnt` anyway. However, in a
free-threaded CPython, combined with disabling the limited API (since it
requires the GIL for now), the direct member does not exist, causing the
build to fail. The macro expands to the correct access method in the
free-threaded configuration.
Commit: 710c2f0ca5a4e0b93eda0e014af24ed09946f5c5
https://github.com/llvm/llvm-project/commit/710c2f0ca5a4e0b93eda0e014af24ed09946f5c5
Author: vporpo <vasileios.porpodas at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/unittests/SandboxIR/TrackerTest.cpp
Log Message:
-----------
[SandboxIR][Tracker] Test UncondBrInst CondBrInst setters (#187549)
This checks the `setCondition()` and `setSuccessor()` setters introduced
in #187196.
Commit: d2dab9788a57186a2b3ce927ee8a0fcdb09907a2
https://github.com/llvm/llvm-project/commit/d2dab9788a57186a2b3ce927ee8a0fcdb09907a2
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
A llvm/test/CodeGen/SPIRV/bool-vector-bitcast.ll
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/masked-load-store.ll
Log Message:
-----------
[SPIR-V] Decompose bitcasts involving bool vectors (#187960)
OpTypeBool has no defined bitwidth in SPIR-V, so OpBitcast is invalid
for boolean vector types. Decompose `<N x i1> <-> iN` bitcasts into
element-wise extract/shift/OR and AND/icmp/insert sequences during IR
preprocessing.
Fixes:
https://github.com/kuhar/iree/blob/amdgcn-spirv/spirv-repros/bitcast_crash.ll
and https://github.com/llvm/llvm-project/issues/185815
Commit: dd9885c0f34fdf64e0de2b07b94ab141274a82e2
https://github.com/llvm/llvm-project/commit/dd9885c0f34fdf64e0de2b07b94ab141274a82e2
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M clang-tools-extra/clang-tidy/modernize/UseStdFormatCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/test/clang-tidy/checkers/modernize/use-std-format-macro.cpp
Log Message:
-----------
[clang-tidy] Add missing #include insertion in macros for modernize-use-std-format (#188247)
Added missing ``#include`` insertion when the format function call
appears as an argument to a macro.
Part of #175183
---------
Co-authored-by: Victor Chernyakin <chernyakin.victor.j at outlook.com>
Commit: b60a39e3c223624577d475f278bbc26540adca9c
https://github.com/llvm/llvm-project/commit/b60a39e3c223624577d475f278bbc26540adca9c
Author: Derek Schuff <dschuff at chromium.org>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
A lld/test/wasm/lto/thinlto-shared-memory-atomics.ll
M lld/wasm/LTO.cpp
Log Message:
-----------
[lld][WebAssembly] Propagate +atomics for ThinLTO when using --shared-memory (#188381)
When compiling WebAssembly with ThinLTO, functions are partitioned into
isolated `.bc` modules and dispatched to individual LTO backend threads.
During code generation, the `CoalesceFeaturesAndStripAtomics` pass
iterates over the module to gather the union of target features (like
`+atomics`) attached to defined functions. In particular when not using
threads, it lowers away atomics and TLS variables to their
single-threaded equivalents.
However, if a partitioned module only contains globally defined TLS
variables (e.g. there are no functions, or all functions were fully
inlined or stripped by dropDeadSymbols before ThinLTO optimization), the
module becomes completely devoid of function definitions. The coalescing
pass then falls back to fetching features from the `TargetMachine`.
Because in LTO the `TargetMachine` defaults to a generic target without
atomics enabled, the TLS is lowered away and the `wasm-feature-atomics`
flag is omitted from the resulting ThinLTO object partition, causing
`wasm-ld` to immediately reject it.
To fix this we take advantage of the fact that the linker always knows
whether threads are being used (via the --shared-memory flag). When
using shared memory, we enable +atomics and +bulk-memory in the
TargetMachine that is used for the backend, and the feature coalescing
pass will correctly detect the use of therads.
This only makes sense for atomics because of the global linker
configuration; for other features we wouldn't be able to do this, but we
don't rewrite away any other features anyway.
Commit: 9999f7fe085333215d95a022e15a12610289c4e3
https://github.com/llvm/llvm-project/commit/9999f7fe085333215d95a022e15a12610289c4e3
Author: Zorojuro <sawantsukumar at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libc/src/math/atanpif16.h
Log Message:
-----------
[libc] Wrong header guard comment for atanpif16 (#188310)
This PR intends to fix a small nit caused in
[1c1135b](https://github.com/llvm/llvm-project/pull/150400/commits/1c1135b3fccf59537243fc365e83a568f77273ae)
```
#endif // LLVM_LIBC_SRC_MATH_ASINIF16_H
```
to
```
#endif // LLVM_LIBC_SRC_MATH_ATANPIF16_H
```
Commit: 408bb4d4b22bbd255eb0b4ea65b9c9d18bf55979
https://github.com/llvm/llvm-project/commit/408bb4d4b22bbd255eb0b4ea65b9c9d18bf55979
Author: Zorojuro <sawantsukumar at gmail.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M libc/src/math/totalorderbf16.h
M libc/src/math/totalordermagbf16.h
Log Message:
-----------
[libc] Wrong guards for `totalorderbf16` and `totalordermagbf16` (#188241)
Currently the guards for `totalorderbf16` and `totalordermagbf16` are as
follows:
```
#ifndef LLVM_LIBC_SRC_MATH_TOTALORDERMAGF16_H
#define LLVM_LIBC_SRC_MATH_TOTALORDERMAGF16_H
-
#endif // LLVM_LIBC_SRC_MATH_TOTALORDERMAGF16_H
```
and
```
#ifndef LLVM_LIBC_SRC_MATH_TOTALORDERF16_H
#define LLVM_LIBC_SRC_MATH_TOTALORDERF16_H
-
#endif // LLVM_LIBC_SRC_MATH_TOTALORDERF16_H
```
As we can see these are for F16 and not BF16 .
This Pr intends to fix that with correct guards as `TOTALORDERBF16` and
`TOTALORDERMAGBF16`
Commit: aecfaf11953fe6117a15a26b81d86bb75813e09b
https://github.com/llvm/llvm-project/commit/aecfaf11953fe6117a15a26b81d86bb75813e09b
Author: khaki3 <47756807+khaki3 at users.noreply.github.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M flang/lib/Optimizer/OpenACC/Support/RegisterOpenACCExtensions.cpp
M flang/test/Fir/OpenACC/offload-livein-value-canonicalization.fir
Log Message:
-----------
[flang][acc] Handle fir.undefined with OutlineRematerializationOpInterface in OffloadLiveInValueCanonicalization (#188325)
Example:
```fortran
!$ACC KERNELS PRESENT(CG, W1)
CG(1:W1%WDES1%NPL, NN) = W1%CPTWFP(1:W1%WDES1%NPL)
CPROJ(:, NN) = W1%CPROJ(1:SIZE(CPROJ,1))
!$ACC END KERNELS
```
When compiling OpenACC kernels containing array section assignments of
rank-2 arrays with a scalar index in one dimension (e.g. `CG(1:NPL,
NN)`), the Fortran lowering creates a `fir.slice` where collapsed
(scalar) dimensions use `fir.undefined index` as the stop/step values.
`SliceOp::getOutputRank()` relies on `getDefiningOp()` returning
`fir::UndefOp` to identify these collapsed dimensions and compute the
correct output rank.
When `fir.undefined` values defined outside an offload region are used
inside it, `gpu-kernel-outlining` turns them into function arguments.
Since function arguments have no defining op (`getDefiningOp()` returns
`nullptr`), `getOutputRank()` no longer recognizes the collapsed
dimensions, computing rank 2 instead of rank 1. This causes the
`fir.rebox` verifier to fail with:
```
'fir.rebox' op result type rank and rank after applying slice operand must match
```
Fix: Register `OutlineRematerializationOpInterface` for `fir::UndefOp`
(and `fir::SliceOp`) in `RegisterOpenACCExtensions.cpp`. This causes
`OffloadLiveInValueCanonicalization` to clone these operations inside
the offload region before outlining, preserving the `fir::UndefOp`
identity so that `getOutputRank()` correctly identifies collapsed
dimensions.
Commit: cb125346509a10b48d32788a8242b3722e5113d9
https://github.com/llvm/llvm-project/commit/cb125346509a10b48d32788a8242b3722e5113d9
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M compiler-rt/lib/builtins/emutls.c
Log Message:
-----------
[compiler-rt] Suppress unused variable report in emutls
Pull Request: https://github.com/llvm/llvm-project/pull/188329
Commit: 218f240472086d243ec6a30651e7ea9c2b9b4c8b
https://github.com/llvm/llvm-project/commit/218f240472086d243ec6a30651e7ea9c2b9b4c8b
Author: Jim Lin <jim at andestech.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Log Message:
-----------
[RISCV] Fix ssub_sat cost model to use signed VSSUB instead of VSSUBU (#188195)
Intrinsic::ssub_sat was incorrectly mapped to RISCV::VSSUBU_VV (unsigned
saturating subtract) instead of RISCV::VSSUB_VV (signed saturating
subtract), causing wrong cost estimates.
Co-authored-by: Claude Opus 4.6 (1M context) <noreply at anthropic.com>
Commit: d49d24ca978d8130c2e440fb42fea8f237c5203e
https://github.com/llvm/llvm-project/commit/d49d24ca978d8130c2e440fb42fea8f237c5203e
Author: Philip Reames <preames at rivosinc.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
M llvm/lib/Target/RISCV/RISCVInstrPredicates.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.cpp
M llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-insertelement.ll
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/CodeGen/RISCV/pr148084.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
M llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
R llvm/test/MC/RISCV/xrivosvisni-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Remove the experimental XRivosVisni extension (#188370)
Commit: 6ae5803ffdebf1486d9a1987b818a231444cfd8d
https://github.com/llvm/llvm-project/commit/6ae5803ffdebf1486d9a1987b818a231444cfd8d
Author: wanglei <wanglei at loongson.cn>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/test/CodeGen/LoongArch/fsqrt-reciprocal-estimate.ll
M llvm/test/CodeGen/LoongArch/lasx/fsqrt-reciprocal-estimate.ll
M llvm/test/CodeGen/LoongArch/lsx/fsqrt-reciprocal-estimate.ll
Log Message:
-----------
[LoongArch] Fix incorrect reciprocal sqrt estimate semantics (#187621)
The current implementation of getSqrtEstimate() has incorrect semantics
when using `FRSQRTE`.
`FRSQRTE` computes an approximation to 1/sqrt(x), but the existing code
multiplies the estimate by the operand when Reciprocal is true. This
results in returning sqrt(x) instead of 1/sqrt(x), effectively reversing
the intended semantics of the 'Reciprocal' flag.
Additionally, the implementation does not properly account for LLVM's
Newton-Raphson refinement pipeline. When refinement steps are requested,
the initial estimate must be in reciprocal form so that the generic
DAGCombiner can apply NR iterations correctly.
This patch fixes the behavior by:
- Returning the raw FRSQRTE result when Reciprocal is true, or when
refinement steps are required.
- Only reconstructing sqrt(x) via x * rsqrt(x) when no refinement is
requested.
- Refactoring type checks into a helper function
(isSupportedReciprocalEstimateType)
for improved readability and maintainability.
The updated implementation aligns with the expectations of LLVM's
reciprocal estimate framework and matches the behavior of other targets
such as X86 and AArch64.
No functional change when reciprocal estimates are disabled, but fixes
incorrect results when fast-math enables reciprocal sqrt estimates.
Fixes #186328
Commit: cd9a0dc4545773e0c8b80f56881423751efa5994
https://github.com/llvm/llvm-project/commit/cd9a0dc4545773e0c8b80f56881423751efa5994
Author: Lang Hames <lhames at gmail.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/EPCGenericJITLinkMemoryManager.h
M llvm/lib/ExecutionEngine/Orc/EPCGenericJITLinkMemoryManager.cpp
M llvm/unittests/ExecutionEngine/Orc/EPCGenericJITLinkMemoryManagerTest.cpp
Log Message:
-----------
[ORC] EPCGenericJITLinkMemoryManager from SimpleNativeMemoryMap syms. (#188391)
Adds a new EPCGenericJITLinkMemoryManager convenience constructor that
constructs an instance by looking up the given symbol names in the
bootstrap JITDylib of the given ExecutionSession.
The symbol names default to the SimpleNativeMemoryMap SPS-interface
symbol names provided by the new ORC runtime.
Commit: 80603c6672226cb48798bd60120c8f859dbeca19
https://github.com/llvm/llvm-project/commit/80603c6672226cb48798bd60120c8f859dbeca19
Author: Weibo He <NewSigma at 163.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/docs/Coroutines.rst
M llvm/docs/LangRef.rst
M llvm/lib/FuzzMutate/RandomIRBuilder.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Transforms/Coroutines/SpillUtils.cpp
A llvm/test/Transforms/Coroutines/coro-alloca-10.ll
M llvm/unittests/FuzzMutate/StrategiesTest.cpp
Log Message:
-----------
[CoroSplit] Never collect allocas used by catchpad into frame (#186728)
Windows EH requires exception objects allocated on stack. But there is
no reliable way to identify them. CoroSplit employs a best-effort
algorithm to determine whether allocas persist on the stack or the
frame, which may result in miscompilation when Windows exceptions are
used.
This patch proposes that we treat allocas used by catchpad as exception
objects and never place them on the frame. A verifier check is added to
enforce that operands of catchpad are either constants or allocas.
Close #143235 Close #153949 Close #182584
Commit: eca7d833a6158194078635c1054ada81324e9b97
https://github.com/llvm/llvm-project/commit/eca7d833a6158194078635c1054ada81324e9b97
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/test/Conversion/MemRefToLLVM/expand-then-convert-to-llvm.mlir
M mlir/test/Dialect/MemRef/expand-strided-metadata.mlir
Log Message:
-----------
[mlir][memref] Simplify expand_shape size/stride computation using output_shape (#187844)
This PR refactors `getExpandedSizes` and `getExpandedStrides` to compute
their results directly from the `output_shape` of `memref.expand_shape`.
Instead of reconstructing expanded sizes/strides through manual
inference, we now rely on the operation’s explicit shape information.
The previous implementation imposed the restriction that there must be
at most one dynamic size per reassociation group. This limitation is
removed by the new approach: any number of dynamic dimensions within a
group is now supported, as long as they are represented in the
`output_shape`.
As a result, the code becomes both simpler and more expressive, while
better matching the semantics of `memref.expand_shape`.
Commit: feae3bc202cedbc1e83201eb8ea147f1a7729cd3
https://github.com/llvm/llvm-project/commit/feae3bc202cedbc1e83201eb8ea147f1a7729cd3
Author: Nikhil Kotikalapudi <nak00001 at outlook.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M libcxx/docs/ReleaseNotes/23.rst
M libcxx/include/__iterator/wrap_iter.h
Log Message:
-----------
[libc++] Remove non-standard member type iterator_type from __wrap_iter (#186871)
Resolves #186801
Removed the non-standard member type `iterator_type` from `__wrap_iter`.
This member exposed the underlying iterator type, and its removal
prevents users from relying on the implementation detail.
Commit: b16e012603de706c6fa172af92767a22094fb8b1
https://github.com/llvm/llvm-project/commit/b16e012603de706c6fa172af92767a22094fb8b1
Author: Sairudra More <sairudra60 at gmail.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M flang-rt/lib/runtime/trampoline.cpp
Log Message:
-----------
[flang-rt] Fix macOS build: define _DARWIN_C_SOURCE for mmap flags (#186142)
On Darwin, `sys/mman.h` hides `MAP_JIT` and `MAP_ANON(YMOUS)` when
`_POSIX_C_SOURCE` is defined unless `_DARWIN_C_SOURCE` is also defined.
`trampoline.cpp` uses those flags, so this change defines
`_DARWIN_C_SOURCE` before including `<sys/mman.h>` in this file.
Fixes build failure reported in #183108.
Co-authored-by: Sairudra More <moresair at pe31.hpc.amslabs.hpecorp.net>
Commit: 665c2e91e29ddfc2a60746d7d2e6bc60fe5d3e08
https://github.com/llvm/llvm-project/commit/665c2e91e29ddfc2a60746d7d2e6bc60fe5d3e08
Author: Sairudra More <sairudra60 at gmail.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
A flang/test/Integration/OpenMP/taskloop-bounds-cast.f90
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
A mlir/test/Target/LLVMIR/openmp-taskloop-bounds-cast.mlir
Log Message:
-----------
[Flang][OpenMP] Remove dead restoreIP in OpenMP taskloop lowering (#187222)
This fixes an intermittent crash in `OpenMP` taskloop lowering.
In `OMPIRBuilder::createTaskloop`, the `restoreIP` in `PostOutlineCB`
was immediately overwritten by the following
`Builder.SetInsertPoint(StaleCI)` with no instructions created in
between, so it was effectively dead. This patch removes that dead
restore, which is the smallest change and preserves the intended IR
placement.
Adds a regression test that compiles a taskloop to LLVM IR and verifies
the bounds casts and __kmpc_taskloop call are present.
Commit: f599bfcd273a502aebb392b901e39240a0074710
https://github.com/llvm/llvm-project/commit/f599bfcd273a502aebb392b901e39240a0074710
Author: Fangrui Song <i at maskray.me>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M lld/ELF/LinkerScript.cpp
Log Message:
-----------
[ELF] Guard relocation section handling behind copyRelocs in addOrphanSections. NFC (#188409)
In addOrphanSections, getRelocatedSection() only returns non-null for -r
or --emit-relocs links. Guard code blocks with `copyRelocs` to skip
unnecessary dyn_cast + getRelocatedSection calls per section in the
common case. Hoist copyRelocs and relocatable to local variables so the
compiler does not reload them through ctx on every loop iteration.
"Assign sections" decreases by 1ms.
Commit: 3b04d26abd50bb50f8ffa889439a30f2b778d9a1
https://github.com/llvm/llvm-project/commit/3b04d26abd50bb50f8ffa889439a30f2b778d9a1
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
A compiler-rt/test/asan/TestCases/disable_container_overflow_checks.c
R compiler-rt/test/asan/TestCases/disable_container_overflow_checks.cpp
A compiler-rt/test/asan/TestCases/stack_container_dynamic_lib.c
R compiler-rt/test/asan/TestCases/stack_container_dynamic_lib.cpp
Log Message:
-----------
[asan] Convert __SANITIZER_DISABLE_CONTAINER_OVERFLOW__ tests to C (#188406)
As-is tests do not pass on android with older C++ headers.
There is nothing C++ specific in tests.
Followup to #181721.
Commit: 2eae3f3fcfe503370d7487d3bf1cfa7e488016d4
https://github.com/llvm/llvm-project/commit/2eae3f3fcfe503370d7487d3bf1cfa7e488016d4
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M clang/lib/DependencyScanning/DependencyScannerImpl.cpp
A clang/test/ClangScanDeps/p1689-suppress-warnings.cppm
Log Message:
-----------
[Reland] [ClangScanDeps] Do not emit warning for P1689 format (#186966) (#188401)
Close https://github.com/llvm/llvm-project/issues/185394
This is only for P1689 format as ClangScanDeps/optimize-vfs-pch.m will
check for warning message. I'll leave this to people who want to change
that.
Commit: acbbe5c145a9702d14e163659a60573aaf66036c
https://github.com/llvm/llvm-project/commit/acbbe5c145a9702d14e163659a60573aaf66036c
Author: Zeyi Xu <mitchell.xu2 at gmail.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/std/cstddef
M clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/std/stddef.h
M clang-tools-extra/test/clang-tidy/checkers/readability/implicit-bool-conversion-cxx98.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/implicit-bool-conversion.cpp
Log Message:
-----------
[clang-tidy][NFC] Remove hack in readability-implicit-bool-conversion testcases (#188399)
Another attempt after #184850
Commit: a5a7f6266ef05aa0093a779d6f2fc8e513a352e6
https://github.com/llvm/llvm-project/commit/a5a7f6266ef05aa0093a779d6f2fc8e513a352e6
Author: Andrew Haberlandt <ahaberlandt at apple.com>
Date: 2026-03-24 (Tue, 24 Mar 2026)
Changed paths:
M compiler-rt/test/builtins/CMakeLists.txt
M compiler-rt/test/builtins/Unit/lit.cfg.py
M compiler-rt/test/builtins/Unit/lit.site.cfg.py.in
Log Message:
-----------
[compiler-rt] CRT builtins tests should not run on mac/windows under LLVM_ENABLE_RUNTIMES (#187835)
#171941 got the builtins tests running under LLVM_ENABLE_RUNTIMES by
testing the builtins as part of the runtimes build.
As a consequence, CMake in `lib/builtins/` is no longer visible when
configuring the tests (but `test/builtins/` is). This means that the
`cmake_dependent_option` from `lib/builtins/` is not accounted for by
the tests, allowing COMPILER_RT_BUILD_CRT to be YES when
COMPILER_RT_HAS_CRT is NO. As a consequence, the CRT tests are running
on platforms where COMPILER_RT_HAS_CRT is false (#176892).
https://github.com/llvm/llvm-project/blob/367da15a11c52886c50e7f020cb4de59fe6d07ca/compiler-rt/lib/builtins/CMakeLists.txt#L1106-L1108
Although the long-term solution could be to split both the builtins (and
their tests) out of compiler-rt into a top-level directory with shared
options, this works around the issue for the moment by checking both
COMPILER_RT_HAS_CRT and COMPILER_RT_BUILD_CRT before enabling the "crt"
feature.
Fixes #176892
Commit: f0b58c16e10c401bb772db55f3ef8a9803afef65
https://github.com/llvm/llvm-project/commit/f0b58c16e10c401bb772db55f3ef8a9803afef65
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M libc/docs/dev/cmake_build_rules.rst
M libc/docs/dev/entrypoints.rst
M libc/docs/dev/fuzzing.rst
M libc/docs/dev/implementation_standard.rst
M libc/docs/dev/source_tree_layout.rst
M libc/docs/dev/undefined_behavior.rst
M libc/docs/porting.rst
Log Message:
-----------
[libc][docs][NFC] Expand entrypoints technical reference (#4) (#188255)
Expanded entrypoints.rst with details about definitions, registration
rules, and the lifecycle of an entrypoint.
Updated multiple documents to remove redundant technical details and
link to the centralized entrypoints reference:
- libc/docs/dev/cmake_build_rules.rst
- libc/docs/dev/implementation_standard.rst
- libc/docs/porting.rst
- libc/docs/dev/source_tree_layout.rst
Commit: d69fc653c1cad4f1eb8acc7a31e4f5efe1fcdb49
https://github.com/llvm/llvm-project/commit/d69fc653c1cad4f1eb8acc7a31e4f5efe1fcdb49
Author: Ruiling, Song <ruiling.song at amd.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
A llvm/test/CodeGen/AMDGPU/promote-alloca-placeholder-replacement.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-use-after-erase.ll
Log Message:
-----------
AMDGPU: Simplify placeholder replacement in AMDGPUPromoteAlloca (#188202)
If `promoteAllocaUserToVector` returns the placeholder, it means the
instruction does not actually modify the alloca. we don't need to add
the placeholder as block available value for correctness. Instructions
appear afterwards in the the same block could still get the placeholder
as source value through GetCurVal() call. Instructions in other block
which access the alloca will be set up later when we really do
placeholder replacement.
This help simplify the placeholder replacement logic.
Commit: abd26bf251a6303a249523aa3dd683f7f5372280
https://github.com/llvm/llvm-project/commit/abd26bf251a6303a249523aa3dd683f7f5372280
Author: Lang Hames <lhames at gmail.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/SelfExecutorProcessControl.h
M llvm/lib/ExecutionEngine/Orc/SelfExecutorProcessControl.cpp
Log Message:
-----------
[ORC] Move DylibManager impl out of SelfExecutorProcessControl. (#188417)
SelfExecutorProcessControl no longer implements DylibManager. Instead a
private inner class, InProcessDylibManager, is used to implement this
interface. This change should not affect the behavior of
SelfExecutorProcessControl from the perspective of API clients.
This is a step towards decoupling ExecutorProcessControl implementations
from other interfaces.
Commit: e40062c0bdefc0272b918031d1f4d41443efe8bd
https://github.com/llvm/llvm-project/commit/e40062c0bdefc0272b918031d1f4d41443efe8bd
Author: Alex Duran <alejandro.duran at intel.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M offload/plugins-nextgen/level_zero/include/L0Device.h
M offload/plugins-nextgen/level_zero/src/L0Device.cpp
Log Message:
-----------
[OFFLOAD][L0] Add support to run ctor/dtor code (#187510)
This PR adds support in the Level Zero plugin to execute
constructors/destructors on the device code. As spirv-link has some
limitations, it mimics the CUDA plugin behavior where the RTL constructs
the device side tables before invoking the kernel that will execute
them.
The kernel and other necessary symbols to create the device tables are
created by the SPIRVCtorDtorLowering pass to be added in #187509
Commit: 4c4c1db7c69a6fda6cfa6bc6066bb09a433edc89
https://github.com/llvm/llvm-project/commit/4c4c1db7c69a6fda6cfa6bc6066bb09a433edc89
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/llvm-libc-macros/linux/sys-stat-macros.h
M libc/include/sys/stat.yaml
M libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
A libc/src/__support/OSUtil/linux/syscall_wrappers/utimensat.h
M libc/src/sys/stat/CMakeLists.txt
M libc/src/sys/stat/linux/CMakeLists.txt
A libc/src/sys/stat/linux/utimensat.cpp
A libc/src/sys/stat/utimensat.h
M libc/src/sys/time/linux/CMakeLists.txt
M libc/src/sys/time/linux/utimes.cpp
M libc/test/src/sys/stat/CMakeLists.txt
A libc/test/src/sys/stat/utimensat_test.cpp
Log Message:
-----------
[libc] Add utimensat syscall wrapper and entrypoint (#188347)
Implemented the utimensat syscall for Linux and added the entrypoint to
sys/stat.h.
* Added utimensat syscall wrapper to OSUtil
* Updated utimes to use the utimensat wrapper
* Added utimensat unit tests to sys/stat
* Configured entrypoints for x86_64, riscv, and aarch64
Commit: 19048672ab1bc9acbcb517655116729426443112
https://github.com/llvm/llvm-project/commit/19048672ab1bc9acbcb517655116729426443112
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
A llvm/test/Transforms/InstCombine/nanless-canonicalize-combine.ll
Log Message:
-----------
InstCombine: Add baseline test for nanless canonicalize combine (#172997)
Commit: 34ee487775ae3b93f241e1bf8c8e97046d998654
https://github.com/llvm/llvm-project/commit/34ee487775ae3b93f241e1bf8c8e97046d998654
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
Log Message:
-----------
AMDGPU: Implememt memsize forms of isLoadFromStackSlot/isStoreToStackSlot (#188264)
Requested in #182673, though I'm not sure why this needs to be pushed
into targets. The size can be taken from the machine mem operand
generically.
Commit: 7cb57c680828ff1a8cb020296c9995cc01bf1c3d
https://github.com/llvm/llvm-project/commit/7cb57c680828ff1a8cb020296c9995cc01bf1c3d
Author: Tuomas Kärnä <tuomas.karna at intel.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/TransformOps/XeGPUTransformOps.td
M mlir/lib/Dialect/XeGPU/TransformOps/XeGPUTransformOps.cpp
M mlir/python/mlir/dialects/transform/xegpu.py
M mlir/test/Dialect/XeGPU/transform-ops-invalid.mlir
M mlir/test/Dialect/XeGPU/transform-ops.mlir
M mlir/test/python/dialects/transform_xegpu_ext.py
Log Message:
-----------
[MLIR][XeGPU][TransformOps] Remove obsolete transform ops (#187561)
Cleaning up XeGPU transform ops. Now that XeGPU layout propagation
works, it is sufficient to set the layouts for anchor ops (e.g.
load/store/dpas ops) only.
Changes:
* Remove `xegpu.get_desc_op` and `xegpu.set_desc_layout`. Users should
not change the layout of descriptor op's return value anymore.
* Add `xegpu.get_load_op(value)` that finds either `xegpu.load_nd` or
`xegpu.load` op in the value's producer chain. This is a useful utility
as load ops often need to be annotated with a layout.
* The generic `xegpu.set_op_layout_attr(op, ...)` is now replaced by
`xegpu.set_anchor_layout(op, ...)` that only sets layout attribute of
anchor ops. Raises an error if the given op does not support anchor
layouts.
* `xegpu.insert_prefetch` takes a load op handle instead of a value.
Commit: c1cd0d57c319c28cb0ded983eb7f1fb07163faea
https://github.com/llvm/llvm-project/commit/c1cd0d57c319c28cb0ded983eb7f1fb07163faea
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M libclc/clc/include/clc/math/gentype.inc
M libclc/clc/include/clc/math/math.h
M libclc/clc/lib/generic/math/clc_ep.cl
M libclc/clc/lib/generic/math/clc_ep.inc
M libclc/clc/lib/generic/math/clc_sincos_helpers.inc
Log Message:
-----------
libclc: Unify fast FMA controls (#188244)
This was defined in multiple places with different names. Consolidate
on one, with a gentype wrapper for it. Also set the value based on the
standard FP_FAST_FMA* macros.
Commit: 73df0d6b2cbcd485f99afc6714b6f0148a3993ef
https://github.com/llvm/llvm-project/commit/73df0d6b2cbcd485f99afc6714b6f0148a3993ef
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/test/MC/AMDGPU/gfx1250_asm_wmma_w32.s
M llvm/test/MC/AMDGPU/gfx1250_asm_wmma_w32_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_wmma_w32.txt
Log Message:
-----------
[AMDGPU] Disable neg_lo[0:1] and neg_hi[0:1] on gfx1250 WMMA, MC part (#188349)
Commit: 5012b76ae273790340283084a3d0de96aeb54866
https://github.com/llvm/llvm-project/commit/5012b76ae273790340283084a3d0de96aeb54866
Author: David Green <david.green at arm.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/test/CodeGen/ARM/vld2.ll
Log Message:
-----------
[ARM] Fix incorrect post increment from Or (#188036)
If a Or is detected by findPointerConstIncrement but not by
getPointerConstIncrement it could use an invalid increment for the
offset. Protect against cases where getPointerConstIncrement cannot
return a valid offset.
Fixes #185677
Commit: 4e7274dd4ae6ded0bdb8e79b58e33359d4cbfa79
https://github.com/llvm/llvm-project/commit/4e7274dd4ae6ded0bdb8e79b58e33359d4cbfa79
Author: Raphael Isemann <rise at apple.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M lldb/source/Target/Thread.cpp
Log Message:
-----------
[lldb] Print correct thread plan in logging code of Thread::ShouldReportRun (#188198)
This code accesses the completed thread plan (even if it's private one).
However, the logging code does not pass `skip_private=false` and instead
accesses only the public completed thread plan. In case there is no
public thread plan, the logging code could also crash.
This is just some minor refactoring that ensures we use the same thread
plan in the logging code.
Commit: 8b1f7f00b43757ab941c8b835be5fee6495084c1
https://github.com/llvm/llvm-project/commit/8b1f7f00b43757ab941c8b835be5fee6495084c1
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll
M llvm/test/Analysis/DependenceAnalysis/weak-crossing-siv-coeff-may-zero.ll
Log Message:
-----------
[DA] Fix the Weak Crossing SIV test when Coeff and Delta are zero (#188203)
The Weak Zero SIV test concluded that there is a dependency only in the
`=`-direction when `Delta` is zero. This is incorrect, because the
coefficients of the addrecs might be zero, in which case the dependency
should have all directions. This patch adds non-zero check for the
coefficient to address the issue.
Commit: c43f6a060ae40788f4b2ab17b4fef91215b26cac
https://github.com/llvm/llvm-project/commit/c43f6a060ae40788f4b2ab17b4fef91215b26cac
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vec-strict-cmp-128.ll
Log Message:
-----------
[X86] Fix widening for strict_fmin/fmax (#188286)
I believe that widening these with undef is not correct, because the
undef values might be picked as sNaN and then trap.
Commit: 0e49be0d985e30592b400961e77e2582082ed196
https://github.com/llvm/llvm-project/commit/0e49be0d985e30592b400961e77e2582082ed196
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M libclc/clc/include/clc/math/math.h
Log Message:
-----------
libclc: Force assuming fast float fma for AMDGPU (#188245)
Currently the build uses the default dummy target, which assumes
FMA is slow. Force this to assume fast fma, which is the case on
any remotely new hardware. In the future if we want better support
for older targets, there should be a separate build of the math
functions for the slow fma case.
Commit: 7c933f0979e03eb3acd132706e378185acae24b8
https://github.com/llvm/llvm-project/commit/7c933f0979e03eb3acd132706e378185acae24b8
Author: Matthias Springer <me at m-sp.org>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
M mlir/test/Conversion/ArithToLLVM/convert-nd-vector-to-llvmir.mlir
M mlir/test/Dialect/Arith/canonicalize.mlir
M mlir/test/Dialect/Arith/invalid.mlir
M mlir/test/Dialect/Arith/ops.mlir
Log Message:
-----------
[mlir][arith] Add `arith.convertf` op (#188041)
There are multiple FP types with the same bitwidth. Neither `extf` nor
`truncf` can be used in that case. Add a new `arith.convertf` op that
can be used in such cases. The op is modeled after `arith.truncf`. Also
add a lowering to LLVM.
Discussion:
https://discourse.llvm.org/t/arith-fptofp-vs-arith-extf-arith-truncf/90276
Assisted-by: claude-4.6-opus-high
Commit: ebe2454dc518d8edcd352fcb2038797eccc13d42
https://github.com/llvm/llvm-project/commit/ebe2454dc518d8edcd352fcb2038797eccc13d42
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M libclc/clc/include/clc/math/clc_atan_helpers_decl.inc
M libclc/clc/lib/generic/math/clc_atan_helpers.inc
M libclc/clc/lib/generic/math/clc_atanpi.cl
M libclc/clc/lib/generic/math/clc_atanpi.inc
Log Message:
-----------
libclc: Update atanpi (#188424)
This was originally ported from rocm device libs in
03dc366e79cd01afe0bbfad2a7ede3087d6c9356. Merge in more
recent changes.
Commit: 1dbf7c7e1b9ef996f1db0fc2454d39cf5433dd92
https://github.com/llvm/llvm-project/commit/1dbf7c7e1b9ef996f1db0fc2454d39cf5433dd92
Author: fineg74 <61437305+fineg74 at users.noreply.github.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M offload/plugins-nextgen/level_zero/include/L0Kernel.h
M offload/plugins-nextgen/level_zero/include/L0Trace.h
M offload/plugins-nextgen/level_zero/src/L0Device.cpp
M offload/plugins-nextgen/level_zero/src/L0Kernel.cpp
Log Message:
-----------
[OFFLOAD] Improve resource management of the plugin (#187597)
This PR improves event management of the plugin by fixing potential
resource leaks and preventing a potential deadlock
Commit: 952dc121244765e6d2b5614b51d7293ab7a2f232
https://github.com/llvm/llvm-project/commit/952dc121244765e6d2b5614b51d7293ab7a2f232
Author: Jakob Koschel <jakobkoschel at google.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M libc/src/__support/OSUtil/darwin/aarch64/syscall.h
M libc/src/__support/OSUtil/linux/aarch64/syscall.h
M libc/src/__support/OSUtil/linux/arm/syscall.h
M libc/src/__support/OSUtil/linux/i386/syscall.h
M libc/src/__support/OSUtil/linux/riscv/syscall.h
M libc/src/__support/OSUtil/linux/x86_64/syscall.h
Log Message:
-----------
Force to inline syscall_impl on all platforms (#186849)
With currently only LIBC_INLINE, we just hint the compiler to inline the
function which however in practice is not always the case.
Since we added `[[gnu::always_inline]]` on linux/x86_64 it makes sense
to do it on all platforms consistently and add a comment explaining why
we need it.
Commit: ea3eb0144748cd03f4e57570b41820688a88c8c0
https://github.com/llvm/llvm-project/commit/ea3eb0144748cd03f4e57570b41820688a88c8c0
Author: Midhunesh <midhunesh.p at ibm.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/tools/llvm-symbolizer/llvm-symbolizer.cpp
Log Message:
-----------
[NFC][llvm-symbolizer]Replace makeStringError helper with createStringError (#188428)
The local `makeStringError` helper in `llvm-symbolizer.cpp` is
equivalent to `createStringError` from `llvm/Support/Error.h`. Remove it
and use `createStringError` directly at all call sites.
Commit: b549b3378f5613f9e136e8d3003603b826906e39
https://github.com/llvm/llvm-project/commit/b549b3378f5613f9e136e8d3003603b826906e39
Author: Jianjian Guan <jacquesguan at me.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
A clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CMakeLists.txt
Log Message:
-----------
[CIR][RISCV][NFC] Add CIRGenBuiltinRISCV file to support RISCV builtins codegen (#186050)
This PR adds CIRGenBuiltinRISCV.cpp file for RISCV specific builtins
codegen support.
List all builtins except vector builtins which need tablegen, and mark
them as "NYI".
Commit: 3ac9b77df2fd1d988129fc920c949234736bcb9e
https://github.com/llvm/llvm-project/commit/3ac9b77df2fd1d988129fc920c949234736bcb9e
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/include/llvm/Analysis/LazyValueInfo.h
M llvm/lib/Analysis/LazyValueInfo.cpp
Log Message:
-----------
[LVI] Remove unused DL member (NFC)
This is never used (the data layout is taken later from the
module instead) and not even initialized in the legacy PM code path.
Commit: 2ecd8e2d5243e7d09e040270ce3fa03011f893bc
https://github.com/llvm/llvm-project/commit/2ecd8e2d5243e7d09e040270ce3fa03011f893bc
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/include/llvm/Analysis/LazyValueInfo.h
M llvm/lib/Analysis/LazyValueInfo.cpp
Log Message:
-----------
[LVI] Store function in LVI wrapper class
We know the function we're working on at construction, there is
no need to have code to fetch the module in every place that
fetches the Impl object.
I'm storing the function instead of the module to be able to get
the block number epoch in a future change.
Commit: 458d3a8f0541a9fe2e7af22a47f7aa4f71151113
https://github.com/llvm/llvm-project/commit/458d3a8f0541a9fe2e7af22a47f7aa4f71151113
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M libc/src/sys/time/linux/utimes.cpp
Log Message:
-----------
[libc] Fix unused variable warning in utimes.cpp (#188347) (#188448)
Moved the declaration of 'ret' inside the SYS_utimes block to prevent an
unused variable warning on the libc-riscv32-qemu-yocto-fullbuild-dbg
builder, which doesn't define SYS_utimes.
Commit: 2e7dd442a562c12756d9a6a19479f628bc87d540
https://github.com/llvm/llvm-project/commit/2e7dd442a562c12756d9a6a19479f628bc87d540
Author: Endre Fülöp <endre.fulop at sigmatechnology.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/CStringChecker.cpp
M clang/test/Analysis/bstring.cpp
M clang/test/Analysis/malloc.c
Log Message:
-----------
[analyzer] Untangle subcheckers of CStringChecker (#186802)
It turns out, that some checks for cstring functions happened as a side
effect of other checks. For example, whether the arguments to memcpy
were uninitialized happened during buffer overflow checking.
The way this was implemented is that if alpha.unix.cstring.OutOfBounds
was disabled, alpha.unix.cstring.UninitializedRead couldn't emit any
warnings. It turns out that major modeling steps are early-exited if a
certain checker is disabled!
This patch moved the early returns to the report emission parts --
modeling still happens, only the bug report construction is omitted.
This would mean that if we find a fatal error (like buffer overflow) we
_should_ stop analysis even if we don't emit a warning (thats a part of
doing modeling), but I decided against implementing that.
One hurdle is that CStringChecker is a dependency of MallocChecker, and
the current tests rely on the CStringChecker _not_ terminating execution
paths prematurely. Considering that the checkers that would do that are
in alpha anyways, this doesn't seem to be an urgent step immediately.
I added FIXMEs to all tests would have failed if the patch sank the
analysis at the fatal cstring function call, but didn't. I also added a
new test case for buffers overlapping, but not being quite equal.
Original Author: Kristóf Umann <dkszelethus at gmail.com>
Co-Author: Endre Fülöp <endre.fulop at sigmatechnology.com> (rebasing, cleaning up comments)
Reviewers added valuable suggestions to comments/test code organisation.
Commit: 86c1510418a0020af2f5650e77945b6386b6b24a
https://github.com/llvm/llvm-project/commit/86c1510418a0020af2f5650e77945b6386b6b24a
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
A llvm/test/Transforms/LoopVectorize/AArch64/binop-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/predicated-costs.ll
Log Message:
-----------
[VPlan] Remove isVector guard in getCostForRecipeWithOpcode. (#188126)
The legacy cost model computes and passes RHSInfo both when widening and
replicating. Match behavior in VPlan-based cost model.
The added test shows that we now compute the same cost as the legacy
cost model.
Without this change, the test added in
llvm/test/Transforms/LoopVectorize/AArch64/predicated-costs.ll would
crash with https://github.com/llvm/llvm-project/pull/187056.
PR: https://github.com/llvm/llvm-project/pull/188126
Commit: d21e1a379878ae23d695ac033274fc8006415202
https://github.com/llvm/llvm-project/commit/d21e1a379878ae23d695ac033274fc8006415202
Author: Rohit Aggarwal <44664450+rohitaggarwal007 at users.noreply.github.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls.ll
Log Message:
-----------
[LIBM][AMDLIBM] - New vector calls for cdfnorm and round scalar calls (#187232)
In amdlibm, new vector calls
cdfnorm
amd_vrd2_cdfnorm
amd_vrd4_cdfnorm
amd_vrd8_cdfnorm
round
amd_vrs16_roundf
amd_vrs8_roundf
amd_vrs4_roundf
amd_vrd8_round
amd_vrd4_round
amd_vrd2_round
Link to aocl repo -
[aocl-libm-ose](https://github.com/amd/aocl-libm-ose)
Commit: 065a39b9f7f06fca0926394096ee1c1fac41d446
https://github.com/llvm/llvm-project/commit/065a39b9f7f06fca0926394096ee1c1fac41d446
Author: Luke Lau <luke at igalia.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Tighten SafeAVL matching in convertEVLExitCond. NFC (#179164)
Follow-up from
https://github.com/llvm/llvm-project/pull/178181#discussion_r2743630145
Commit: 89431a368e022d50c42d7eb38327cafe0ae880a0
https://github.com/llvm/llvm-project/commit/89431a368e022d50c42d7eb38327cafe0ae880a0
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/lib/Analysis/LazyValueInfo.cpp
Log Message:
-----------
[LVI] Use block numbers (#188270)
Store the cache as a vector indexed by block numbers instead of a map,
which results in a small compile-time improvement.
Commit: 0effa7caf1263b4ca7fccb2b6b1953b363923375
https://github.com/llvm/llvm-project/commit/0effa7caf1263b4ca7fccb2b6b1953b363923375
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M libclc/clc/lib/generic/math/clc_asinpi.cl
M libclc/clc/lib/generic/math/clc_asinpi.inc
Log Message:
-----------
libclc: Update asinpi (#188454)
This was originally ported from rocm device libs in
eea0997566cad3be13df897a06dfda74cbd684b9. Update for more recent
changes.
Commit: 5f49ce5eafd892b723b46a733efc3b44e859f53a
https://github.com/llvm/llvm-project/commit/5f49ce5eafd892b723b46a733efc3b44e859f53a
Author: John Brawn <john.brawn at arm.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/test/Transforms/LoopVectorize/ARM/mve-reg-pressure-spills.ll
Log Message:
-----------
[ARM] Consider register pressure when vectorizing with MVE (#188053)
MVE only has 8 vector registers, so it's not too hard for the vectorizer
to end up using more than that resulting in enough spilling that it's
worse than not vectorizing. Enable
shouldConsiderVectorizationRegPressure for targets with MVE so the
vectorizer doesn't vectorize in those cases.
Commit: 1d2f14f625cf3fd2025e45ea584440a8e7e0cc26
https://github.com/llvm/llvm-project/commit/1d2f14f625cf3fd2025e45ea584440a8e7e0cc26
Author: Fabio D'Urso <fdurso at google.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
M compiler-rt/lib/scudo/standalone/tests/common_test.cpp
Log Message:
-----------
[scudo] Use portable TEST_SKIP macro (#188045)
Which expands to ZXTEST_SKIP on Fuchsia.
Commit: 2f38a8fc57b7b64ea26ff667524d4850f8853cae
https://github.com/llvm/llvm-project/commit/2f38a8fc57b7b64ea26ff667524d4850f8853cae
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
Log Message:
-----------
AMDGPU: Codegen for v_dual_dot2acc_f32_f16/bf16 from VOP3 (#179226)
For V_DOT2_F32_F16 and V_DOT2_F32_BF16 add their VOPDName and mark
them with usesCustomInserter which will be used to add pre-RA register
allocation hints to preferably assign dst and src2 to the same physical
register. When the hint is satisfied, canMapVOP3PToVOPD recognises the
instruction as eligible for VOPD pairing by checking if it is VOP2 like:
dst==src2, no source modifiers, no clamp, and src1 is a register.
Mark both instructions as commutable to allow a literal in src1 to be
moved to src0, since VOPD only permits a literal in src0.
Commit: 5999c53e32e85a2991385f8e2a77199416147e8a
https://github.com/llvm/llvm-project/commit/5999c53e32e85a2991385f8e2a77199416147e8a
Author: Fabio D'Urso <fdurso at google.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M libc/include/stdlib-malloc.yaml
Log Message:
-----------
[libc] Declare free_sized and free_aligned_sized in stdlib.h / malloc.h (#188364)
Commit: 64e75b1026e635b7d0d42d1551a8ad983b8a1997
https://github.com/llvm/llvm-project/commit/64e75b1026e635b7d0d42d1551a8ad983b8a1997
Author: David Spickett <david.spickett at arm.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M lldb/docs/use/troubleshooting.rst
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionSourceCode.cpp
Log Message:
-----------
[lldb] Correct spelling of "language" (#188456)
Commit: 0cefe6358f38d99e9e70cb242af5b5f8e9fe4e32
https://github.com/llvm/llvm-project/commit/0cefe6358f38d99e9e70cb242af5b5f8e9fe4e32
Author: Minsoo Choo <minsoochoo0122 at proton.me>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M lldb/source/Plugins/Process/FreeBSD-Kernel-Core/ProcessFreeBSDKernelCore.cpp
Log Message:
-----------
[lldb][Process/FreeBSDKernelCore] Rework plugin destruction (#188426)
Destroy the plugin classes similar to `ProcessElfCore`, another process
plugin derived from `PostMortemProcess` class. After clearing thread
list, invoke `Finalize()` to cleanup resources properly. `Finalize()`
will call `DoDestroy()` which releases `m_kvm` via `kvm_close()`.
---------
Signed-off-by: Minsoo Choo <minsoochoo0122 at proton.me>
Commit: 4b4fbf176dee88820dec55b6e39e2feabb49ac52
https://github.com/llvm/llvm-project/commit/4b4fbf176dee88820dec55b6e39e2feabb49ac52
Author: Hussam Alhassan <hsm.link at proton.me>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
Log Message:
-----------
[NFC][AArch64] ConditionOptimizer: add CmpCondPair and tryOptimizePair (#187160)
Add CmpCondPair to bundle a compare/conditional instruction pair with
its condition code.
Update applyCmpAdjustment() to take CmpCondPair, and extract core
optimization logic into tryOptimizePair() to be used in both intra- and
cross-block paths.
Commit: 6ac9ab87dac313f561432c1271c4083b5f09df94
https://github.com/llvm/llvm-project/commit/6ac9ab87dac313f561432c1271c4083b5f09df94
Author: Yi Zhang <cathyzhyi at google.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
Log Message:
-----------
[mlir][arith] Fix variable only used by assert (#188461)
Commit: ef8c94ea8f869628a4e1115379490f9144346bfc
https://github.com/llvm/llvm-project/commit/ef8c94ea8f869628a4e1115379490f9144346bfc
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/MachineSink.cpp
A llvm/test/CodeGen/AArch64/sink-and-fold-unique-operand.mir
Log Message:
-----------
[MachineSink] Prevent attempts to sink-and-fold into the same instruction more than once (#188048)
When sinking an instruction, we check if the destination instruction can
fold the source instruction into its address mode. If the destination
instruction contains more than one use of the register being sunk, we
won't be able to remove the original instruction, so we should not
attempt to sink.
This also prevents a compiler crash when the destination instruction is
deleted after the first sink-and-fold, and we attempt to sink-and-fold
into it again.
Fixes https://github.com/llvm/llvm-project/issues/187785
Commit: 5e89d60586159138622a6112bedc5801274a7ec3
https://github.com/llvm/llvm-project/commit/5e89d60586159138622a6112bedc5801274a7ec3
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
Log Message:
-----------
[AArch64] Remove add_and_or_is_add pattern matcher and use generic add_like equivalent (#188284)
Commit: 27ba9e2a44c11f8123528c350227db2c9a707c8f
https://github.com/llvm/llvm-project/commit/27ba9e2a44c11f8123528c350227db2c9a707c8f
Author: Victor Campos <victor.campos at arm.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M libc/include/CMakeLists.txt
M libc/include/errno.h.def
M libc/include/stdio.yaml
M libc/include/stdlib.yaml
M libc/include/string.yaml
M libc/include/time.yaml
Log Message:
-----------
[libc] Define Annex K's errno_t in specified headers (#187700)
- Change `errno.h.def` to include a placeholder where hdrgen emits the
public API, which contains the `errno_t` definition.
- Make headers `stdio.h`, `stdlib.h`, `string.h` and `time.h` also
define `errno_t` as specified in the standard.
Commit: 201c5c14c87ca756d5160fc688eb9ffdc3c6e617
https://github.com/llvm/llvm-project/commit/201c5c14c87ca756d5160fc688eb9ffdc3c6e617
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M clang/lib/Basic/Targets/AMDGPU.h
M clang/test/Misc/amdgcn.languageOptsOpenCL.cl
Log Message:
-----------
clang: Report subgroup ext types for AMDGPU with llvm env (#188472)
Report cl_khr_subgroup_extended_types for AMDGPU when targeting
the llvm environment.
Commit: bec0aee0ba1591d46c8cd2d59feeb8240b63a80c
https://github.com/llvm/llvm-project/commit/bec0aee0ba1591d46c8cd2d59feeb8240b63a80c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/aix32-p8-scalar_vector_conversions.ll
M llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
M llvm/test/CodeGen/PowerPC/signbit-shift.ll
M llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/wide-scalar-shift-by-byte-multiple-legalization.ll
Log Message:
-----------
[PowerPC] Use add_like pattern for ADDI/ADDIS add-immediate matching (#187326)
Allow or_disjoint nodes with sext-immediates to make use of the ADD instructions instead of OR (which use zext-immediates) to potentially allow further folding
Commit: d642f598ba421d3d3de791f4854a1131154c3e16
https://github.com/llvm/llvm-project/commit/d642f598ba421d3d3de791f4854a1131154c3e16
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M libclc/clc/lib/generic/math/clc_acospi.cl
M libclc/clc/lib/generic/math/clc_acospi.inc
Log Message:
-----------
libclc: Update acospi (#188455)
This was originally ported from rocm device libs in
084124a8fab6fd71d49ac4928d17c3ef8b350ead. Merge in more
recent changes.
Commit: c84397a6b8064b18b378306d212175eb374fbd79
https://github.com/llvm/llvm-project/commit/c84397a6b8064b18b378306d212175eb374fbd79
Author: Ruoyu Qiu <cabbaken at outlook.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M llvm/lib/Analysis/DependenceAnalysis.cpp
Log Message:
-----------
[DA] Optimize parity check in weakCrossingSIVtest (NFC) (#188437)
This patch simplifies the logic used to determine if the `Distance`
is divisible by 2. Previously, this was done by allocating an APInt
and performing a signed remainder (`srem`) operation.
Since `Distance` is an APInt, we can more efficiently check if it
is odd by directly inspecting the least significant bit (`Distance[0]`).
This avoids an expensive division operation and APInt allocation
while making the code more concise.
Signed-off-by: Ruoyu Qiu <cabbaken at outlook.com>
Commit: b8ababdadd2d4ca7d2586b4afdc1e69b66c2f0d1
https://github.com/llvm/llvm-project/commit/b8ababdadd2d4ca7d2586b4afdc1e69b66c2f0d1
Author: Varad Rahul Kamthe <133588066+varadk27 at users.noreply.github.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
Log Message:
-----------
[MLIR][NVVM] NFC: Refactor NVVM op definitions in NVVMOps.td (#188436)
Refactor `DotAccumulate4WayOp`, `DotAccumulate2WayOp`,
`CpAsyncBulkPrefetchOp`, and `CpAsyncBulkTensorPrefetchOp` Ops to use
the new `NVVM_VoidIntrinsicOp` and `NVVM_SingleResultIntrinsicOp` base
classes, removing redundant `llvmBuilder` and `extraClassDeclaration`
boilerplate. No functional changes.
Commit: 2baa2cdce97eb3b548d193247e1692a95cb694b5
https://github.com/llvm/llvm-project/commit/2baa2cdce97eb3b548d193247e1692a95cb694b5
Author: Victor Campos <victor.campos at arm.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M libc/hdr/types/rsize_t.h
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/rsize_t.h
M libc/include/stdio.yaml
M libc/include/stdlib.yaml
M libc/include/string.yaml
M libc/include/time.yaml
M libc/include/wchar.yaml
Log Message:
-----------
[libc] Follow up on Annex K's rsize_t (#187707)
- Fix header guard name.
- Define `__STDC_WANT_LIB_EXT1__` in `hdr/types/rsize_t.h` so that the
type is available for internal use.
- In accordance to the standard, make `stdio.h`, `stdlib.h`, `string.h`,
`time.h` and `wchar.h` define the type. It should already be available
in `stddef.h` as it's provided by Clang, not LLVM libc.
Commit: 8430b0800140ef686660e36bc950cb29131b3681
https://github.com/llvm/llvm-project/commit/8430b0800140ef686660e36bc950cb29131b3681
Author: Davide Grohmann <davide.grohmann at arm.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td
M mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops.mlir
M mlir/test/Target/SPIRV/tosa-ops.mlir
Log Message:
-----------
[mlir][spirv] Add last 4 data layout ops in TOSA Ext Inst Set (#188199)
This patch introduces the following reduction operators:
spirv.Tosa.Reverse
spirv.Tosa.Slice
spirv.Tosa.Tile
spirv.Tosa.Transpose
Also dialect and serialization round-trip tests have been added.
Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
Commit: 314a94c26f6ad71b5cfaac5ca74392ab2f8580eb
https://github.com/llvm/llvm-project/commit/314a94c26f6ad71b5cfaac5ca74392ab2f8580eb
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M flang/include/flang/Semantics/openmp-utils.h
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/openmp-utils.cpp
M flang/test/Semantics/OpenMP/do-collapse.f90
M flang/test/Semantics/OpenMP/do-concurrent-collapse.f90
M flang/test/Semantics/OpenMP/do08.f90
M flang/test/Semantics/OpenMP/do13.f90
M flang/test/Semantics/OpenMP/do15.f90
M flang/test/Semantics/OpenMP/do16.f90
M flang/test/Semantics/OpenMP/do22.f90
M flang/test/Semantics/OpenMP/tile07.f90
A flang/test/Semantics/OpenMP/tile09.f90
Log Message:
-----------
[flang][OpenMP] Provide reasons for calculated depths (#187781)
If the depth (either semantic or perfect) was limited by some factor,
include the reason for what caused the reduction.
Issue: https://github.com/llvm/llvm-project/issues/185287
Commit: 2fc7fbeab04b9753d4c801e27abdbafaedc1c34e
https://github.com/llvm/llvm-project/commit/2fc7fbeab04b9753d4c801e27abdbafaedc1c34e
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-03-25 (Wed, 25 Mar 2026)
Changed paths:
M .github/workflows/bazel-checks.yml
M .github/workflows/build-ci-container-tooling.yml
M .github/workflows/build-ci-container-windows.yml
M .github/workflows/build-ci-container.yml
M .github/workflows/build-libc-container.yml
M .github/workflows/build-metrics-container.yml
M .github/workflows/check-ci.yml
M .github/workflows/ci-post-commit-analyzer.yml
M .github/workflows/commit-access-greeter.yml
M .github/workflows/commit-access-review.yml
M .github/workflows/docs.yml
M .github/workflows/email-check.yaml
M .github/workflows/gha-codeql.yml
M .github/workflows/hlsl-test-all.yaml
M .github/workflows/ids-check.yml
M .github/workflows/issue-subscriber.yml
M .github/workflows/issue-write.yml
M .github/workflows/libc-fullbuild-tests.yml
M .github/workflows/libc-overlay-tests.yml
M .github/workflows/libclang-abi-tests.yml
M .github/workflows/libclang-python-tests.yml
M .github/workflows/libcxx-build-and-test.yaml
M .github/workflows/libcxx-build-containers.yml
M .github/workflows/libcxx-check-generated-files.yml
M .github/workflows/libcxx-run-benchmarks.yml
M .github/workflows/lldb-pylint-action.yml
M .github/workflows/llvm-abi-tests.yml
M .github/workflows/merged-prs.yml
M .github/workflows/mlir-spirv-tests.yml
M .github/workflows/new-prs.yml
M .github/workflows/pr-code-format.yml
M .github/workflows/pr-code-lint.yml
M .github/workflows/pr-subscriber.yml
M .github/workflows/premerge.yaml
M .github/workflows/prune-branches.yml
M .github/workflows/release-asset-audit.yml
M .github/workflows/release-binaries.yml
M .github/workflows/release-documentation.yml
M .github/workflows/release-doxygen.yml
M .github/workflows/release-sources.yml
M .github/workflows/release-tasks.yml
M .github/workflows/spirv-tests.yml
M .github/workflows/sycl-tests.yml
M .github/workflows/test-unprivileged-download-artifact.yml
M .github/workflows/version-check.yml
A .github/workflows/zizmor.yml
M .mailmap
M bolt/docs/index.rst
A bolt/docs/profiles.md
M bolt/include/bolt/Profile/DataAggregator.h
M bolt/include/bolt/Profile/DataReader.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Core/BinaryEmitter.cpp
M bolt/lib/Passes/AsmDump.cpp
M bolt/lib/Profile/DataAggregator.cpp
A bolt/test/X86/Inputs/pre-aggregated-buildid.txt
A bolt/test/X86/pre-aggregated-perf-buildid.test
M clang-tools-extra/Maintainers.rst
M clang-tools-extra/clang-tidy/bugprone/PointerArithmeticOnPolymorphicObjectCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/StdNamespaceModificationCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseStdFormatCheck.cpp
M clang-tools-extra/clangd/CMakeLists.txt
A clang-tools-extra/clangd/remap/CMakeLists.txt
A clang-tools-extra/clangd/remap/RemapMain.cpp
M clang-tools-extra/clangd/test/CMakeLists.txt
A clang-tools-extra/clangd/test/remap.test
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/std/cstddef
M clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/std/stddef.h
M clang-tools-extra/test/clang-tidy/checkers/bugprone/pointer-arithmetic-on-polymorphic-object-all.cpp
A clang-tools-extra/test/clang-tidy/checkers/bugprone/std-namespace-modification-implicit.cpp
A clang-tools-extra/test/clang-tidy/checkers/modernize/use-std-format-macro.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/implicit-bool-conversion-cxx98.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/implicit-bool-conversion.cpp
M clang/Maintainers.md
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/OpenMPSupport.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/ThreadSafetyAnalysis.rst
M clang/include/clang/AST/ASTMutationListener.h
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/ExternalASTSource.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/Facts.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/Loans.h
M clang/include/clang/Analysis/Analyses/ThreadSafety.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
A clang/include/clang/Basic/HLSLIntrinsics.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/Format/Format.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Serialization/ASTWriter.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/CoreEngine.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/ExplodedGraph.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/Analysis/FlowSensitive/Models/UncheckedOptionalAccessModel.cpp
M clang/lib/Analysis/LifetimeSafety/Checker.cpp
M clang/lib/Analysis/LifetimeSafety/Facts.cpp
M clang/lib/Analysis/LifetimeSafety/FactsGenerator.cpp
M clang/lib/Analysis/LifetimeSafety/Loans.cpp
M clang/lib/Analysis/LifetimeSafety/MovedLoans.cpp
M clang/lib/Analysis/ThreadSafety.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
A clang/lib/CIR/CodeGen/CIRGenBuiltinRISCV.cpp
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/Targets/NVPTX.cpp
M clang/lib/CodeGen/Targets/RISCV.cpp
M clang/lib/DependencyScanning/DependencyScannerImpl.cpp
M clang/lib/Driver/CMakeLists.txt
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/lib/Frontend/MultiplexConsumer.cpp
M clang/lib/Headers/CMakeLists.txt
M clang/lib/Headers/altivec.h
M clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h
M clang/lib/Headers/hlsl/hlsl_intrinsics.h
M clang/lib/Headers/ptrauth.h
M clang/lib/Lex/PPDirectives.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.h
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaCast.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaModule.cpp
M clang/lib/Sema/SemaPPC.cpp
M clang/lib/Sema/SemaSYCL.cpp
M clang/lib/Sema/SemaStmtAttr.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/StaticAnalyzer/Checkers/CStringChecker.cpp
M clang/lib/StaticAnalyzer/Core/CoreEngine.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineCXX.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineCallAndReturn.cpp
M clang/lib/Tooling/InterpolatingCompilationDatabase.cpp
M clang/test/AST/HLSL/Texture2D-scalar-AST.hlsl
M clang/test/AST/HLSL/Texture2D-vector-AST.hlsl
A clang/test/AST/ast-dump-implicit-align-val.cpp
M clang/test/ASTSYCL/ast-dump-sycl-kernel-call-stmt.cpp
M clang/test/Analysis/bstring.cpp
M clang/test/Analysis/malloc.c
M clang/test/C/C2y/n3622.c
A clang/test/CIR/CodeGen/cleanup-scope-return-in-loop.cpp
A clang/test/CIR/CodeGen/new-array-size-conv.cpp
M clang/test/CIR/CodeGen/new.cpp
A clang/test/CIR/CodeGen/rtti-member-pointer.cpp
A clang/test/CIR/CodeGen/rtti-qualfn.cpp
M clang/test/CIR/CodeGen/throws.cpp
M clang/test/CIR/IR/invalid-func.cir
M clang/test/CIR/IR/invalid-linkage.cir
M clang/test/CIR/Transforms/bit.cir
M clang/test/CXX/module/dcl.dcl/dcl.module/p1.cpp
A clang/test/ClangScanDeps/p1689-suppress-warnings.cppm
M clang/test/CodeGen/PowerPC/altivec-ct.c
M clang/test/CodeGen/PowerPC/builtins-ppc-32bit-vec-ll.c
M clang/test/CodeGen/PowerPC/builtins-ppc-crypto.c
M clang/test/CodeGen/PowerPC/builtins-ppc-error.c
M clang/test/CodeGen/PowerPC/builtins-ppc-p8vector.c
M clang/test/CodeGen/PowerPC/builtins-ppc-p9vector.c
M clang/test/CodeGen/PowerPC/builtins-ppc-quadword-char.c
M clang/test/CodeGen/PowerPC/builtins-ppc-quadword-noi128.c
M clang/test/CodeGen/PowerPC/builtins-ppc-quadword.c
M clang/test/CodeGen/PowerPC/builtins-ppc-xl-xst.c
M clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
M clang/test/CodeGen/PowerPC/ppc-vector-compare.cpp
M clang/test/CodeGen/RISCV/abi-empty-structs.c
M clang/test/CodeGen/RISCV/bfloat-abi.c
M clang/test/CodeGen/RISCV/riscv32-abi.c
M clang/test/CodeGen/RISCV/riscv64-abi.c
M clang/test/CodeGenHLSL/BasicFeatures/AggregateSplatCast.hlsl
M clang/test/CodeGenHLSL/BasicFeatures/InitLists.hlsl
A clang/test/CodeGenHLSL/builtins/WaveActiveBitAnd-errors.hlsl
A clang/test/CodeGenHLSL/builtins/WaveActiveBitAnd.hlsl
M clang/test/CodeGenHLSL/resources/ByteAddressBuffers-methods.hlsl
M clang/test/CodeGenHLSL/resources/StructuredBuffers-methods-lib.hlsl
M clang/test/CodeGenHLSL/resources/StructuredBuffers-methods-ps.hlsl
M clang/test/CodeGenHLSL/resources/StructuredBuffers-subscripts.hlsl
A clang/test/CodeGenHLSL/resources/Texture2D-Subscript.hlsl
M clang/test/CodeGenHLSL/resources/TypedBuffers-methods.hlsl
M clang/test/CodeGenHLSL/resources/TypedBuffers-subscript.hlsl
M clang/test/CodeGenSYCL/kernel-caller-entry-point.cpp
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/InstallAPI/extra-exclude-headers.test
M clang/test/InstallAPI/hiddens.test
M clang/test/Misc/amdgcn.languageOptsOpenCL.cl
A clang/test/Modules/class-instantiate-no-change-02.cppm
A clang/test/Modules/special-member-definitions.cppm
M clang/test/Parser/cxx-altivec-bool-128.cpp
M clang/test/Parser/cxx-altivec.cpp
M clang/test/Preprocessor/riscv-target-features.c
A clang/test/Sema/Inputs/warn-unused-but-set-static-global-header.h
A clang/test/Sema/PowerPC/ppc-dmf-mma-builtin-err.c
M clang/test/Sema/builtins-bcd-format-conversion.c
M clang/test/Sema/builtins-bcd-transform.c
M clang/test/Sema/builtins-ppc.c
M clang/test/Sema/code_align.c
M clang/test/Sema/warn-lifetime-safety-dataflow.cpp
M clang/test/Sema/warn-lifetime-safety.cpp
M clang/test/Sema/warn-thread-safety-analysis.c
A clang/test/Sema/warn-unused-but-set-static-global.c
A clang/test/Sema/warn-unused-but-set-static-global.cpp
M clang/test/SemaCXX/builtin-classify-type.cpp
M clang/test/SemaCXX/cxx2b-deducing-this.cpp
M clang/test/SemaCXX/thread-safety-annotations.h
M clang/test/SemaCXX/warn-thread-safety-analysis.cpp
M clang/test/SemaCXX/warn-thread-safety-parsing.cpp
M clang/test/SemaCXX/warn-variable-not-needed.cpp
M clang/test/SemaHLSL/BuiltIns/resource_getpointer-errors.hlsl
A clang/test/SemaHLSL/Resources/Texture2D-Subscript.hlsl
M clang/test/SemaTemplate/stack-exhaustion.cpp
A clang/test/TableGen/hlsl-intrinsics.td
M clang/unittests/AST/ASTImporterTest.cpp
M clang/unittests/Analysis/FlowSensitive/MockHeaders.cpp
M clang/unittests/Analysis/FlowSensitive/UncheckedOptionalAccessModelTest.cpp
M clang/unittests/Analysis/LifetimeSafetyTest.cpp
M clang/unittests/Tooling/CompilationDatabaseTest.cpp
M clang/utils/TableGen/CMakeLists.txt
M clang/utils/TableGen/ClangOpcodesEmitter.cpp
A clang/utils/TableGen/HLSLEmitter.cpp
M clang/utils/TableGen/TableGen.cpp
M clang/utils/TableGen/TableGenBackends.h
M compiler-rt/cmake/Modules/CompilerRTUtils.cmake
M compiler-rt/cmake/base-config-ix.cmake
M compiler-rt/cmake/caches/GPU.cmake
M compiler-rt/lib/builtins/CMakeLists.txt
M compiler-rt/lib/builtins/crtbegin.c
M compiler-rt/lib/builtins/emutls.c
M compiler-rt/lib/fuzzer/FuzzerInterceptors.cpp
M compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
M compiler-rt/lib/scudo/standalone/tests/common_test.cpp
M compiler-rt/test/CMakeLists.txt
A compiler-rt/test/asan/TestCases/disable_container_overflow_checks.c
R compiler-rt/test/asan/TestCases/disable_container_overflow_checks.cpp
A compiler-rt/test/asan/TestCases/stack_container_dynamic_lib.c
R compiler-rt/test/asan/TestCases/stack_container_dynamic_lib.cpp
M compiler-rt/test/builtins/CMakeLists.txt
M compiler-rt/test/builtins/Unit/lit.cfg.py
M compiler-rt/test/builtins/Unit/lit.site.cfg.py.in
M compiler-rt/test/lit.common.cfg.py
M flang-rt/include/flang-rt/runtime/format-implementation.h
M flang-rt/include/flang-rt/runtime/format.h
M flang-rt/lib/cuda/registration.cpp
M flang-rt/lib/runtime/edit-output.cpp
M flang-rt/lib/runtime/io-api.cpp
M flang-rt/lib/runtime/io-stmt.cpp
M flang-rt/lib/runtime/trampoline.cpp
M flang-rt/unittests/Runtime/CMakeLists.txt
A flang-rt/unittests/Runtime/LeadingZeroTest.cpp
M flang-rt/unittests/Runtime/Stop.cpp
M flang/docs/Extensions.md
M flang/docs/F202X.md
M flang/docs/FortranStandardsSupport.md
M flang/include/flang/Common/format.h
M flang/include/flang/Evaluate/tools.h
M flang/include/flang/Optimizer/Transforms/RuntimeFunctions.inc
M flang/include/flang/Parser/format-specification.h
M flang/include/flang/Parser/openmp-utils.h
M flang/include/flang/Parser/parse-tree.h
M flang/include/flang/Parser/tools.h
M flang/include/flang/Runtime/CUDA/registration.h
M flang/include/flang/Runtime/io-api.h
M flang/include/flang/Semantics/openmp-utils.h
M flang/include/flang/Support/Fortran.h
M flang/lib/Evaluate/tools.cpp
M flang/lib/Lower/IO.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/HLFIR/Transforms/InlineHLFIRAssign.cpp
M flang/lib/Optimizer/OpenACC/Support/RegisterOpenACCExtensions.cpp
M flang/lib/Optimizer/OpenACC/Transforms/ACCDeclareActionConversion.cpp
M flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp
M flang/lib/Optimizer/Transforms/FIRToMemRef.cpp
M flang/lib/Parser/io-parsers.cpp
M flang/lib/Parser/openmp-utils.cpp
M flang/lib/Parser/tools.cpp
M flang/lib/Parser/unparse.cpp
M flang/lib/Semantics/canonicalize-do.cpp
M flang/lib/Semantics/check-cuda.cpp
M flang/lib/Semantics/check-io.cpp
M flang/lib/Semantics/openmp-utils.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/resolve-labels.cpp
M flang/test/Fir/OpenACC/declare-action-conversion.fir
M flang/test/Fir/OpenACC/offload-livein-value-canonicalization.fir
M flang/test/Fir/declare_value-codegen.fir
A flang/test/HLFIR/inline-hlfir-assign-allocatable-expr.fir
A flang/test/Integration/OpenMP/taskloop-bounds-cast.f90
M flang/test/Integration/debug-allocatable-1.f90
M flang/test/Integration/debug-common-block-1.f90
M flang/test/Integration/debug-complex-1.f90
M flang/test/Integration/debug-complex-2.f90
M flang/test/Integration/debug-fixed-array-type-2.f90
M flang/test/Integration/debug-local-var-2.f90
M flang/test/Integration/debug-module-2.f90
M flang/test/Integration/debug-proc-ptr-e2e.f90
M flang/test/Integration/debug-ptr-type.f90
A flang/test/Lower/CUDA/cuda-data-transfer-implicit.cuf
M flang/test/Lower/CUDA/cuda-data-transfer.cuf
M flang/test/Lower/CUDA/cuda-managed.cuf
M flang/test/Lower/Intrinsics/minval.f90
M flang/test/Lower/Intrinsics/modulo.f90
M flang/test/Lower/Intrinsics/move_alloc.f90
M flang/test/Lower/Intrinsics/mvbits.f90
M flang/test/Lower/Intrinsics/not.f90
M flang/test/Lower/Intrinsics/pack.f90
M flang/test/Lower/Intrinsics/parity.f90
M flang/test/Lower/Intrinsics/popcnt.f90
M flang/test/Lower/Intrinsics/poppar.f90
M flang/test/Lower/Intrinsics/present.f90
M flang/test/Lower/OpenACC/acc-declare.f90
M flang/test/Lower/OpenMP/composite_simd_linear.f90
M flang/test/Lower/OpenMP/distribute-parallel-do-simd.f90
M flang/test/Lower/OpenMP/distribute-simd.f90
A flang/test/Lower/OpenMP/indirect-reference-privatization.f90
M flang/test/Lower/OpenMP/loop-pointer-variable.f90
M flang/test/Lower/OpenMP/ordered-simd.f90
M flang/test/Lower/OpenMP/parallel-lastprivate-clause-scalar.f90
R flang/test/Lower/OpenMP/privatize_predetermined_only_when_defined_by_eval.f90
M flang/test/Lower/OpenMP/wsloop-simd.f90
M flang/test/Semantics/OpenMP/tile09.f90
A flang/test/Semantics/bug2436.f
A flang/test/Semantics/canondo18.f90
A flang/test/Semantics/io18.f90
A flang/test/Transforms/FIRToMemRef/array-coor-slice-shift.mlir
M flang/test/Transforms/debug-allocatable-1.fir
M flang/test/Transforms/debug-associate-component.fir
M flang/test/Transforms/debug-complex-1.fir
M flang/test/Transforms/debug-derived-type-1.fir
M flang/test/Transforms/debug-fixed-array-type.fir
M flang/test/Transforms/debug-fn-info.fir
M flang/test/Transforms/debug-index-type.fir
M flang/test/Transforms/debug-local-var.fir
M flang/test/Transforms/debug-module-1.fir
M flang/test/Transforms/debug-module-2.fir
M flang/test/Transforms/debug-proc-ptr.fir
M flang/test/Transforms/debug-ptr-type.fir
M flang/test/Transforms/debug-vector-type.fir
M flang/test/Transforms/set-runtime-call-attributes.fir
M flang/test/Transforms/verify-known-runtime-functions.fir
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/CMakeLists.txt
M libc/docs/dev/cmake_build_rules.rst
M libc/docs/dev/entrypoints.rst
M libc/docs/dev/fuzzing.rst
M libc/docs/dev/implementation_standard.rst
M libc/docs/dev/source_tree_layout.rst
M libc/docs/dev/undefined_behavior.rst
M libc/docs/headers/index.rst
M libc/docs/porting.rst
M libc/hdr/types/rsize_t.h
M libc/include/CMakeLists.txt
M libc/include/errno.h.def
M libc/include/llvm-libc-macros/linux/sys-stat-macros.h
M libc/include/llvm-libc-types/rsize_t.h
M libc/include/stdio.yaml
M libc/include/stdlib-malloc.yaml
M libc/include/stdlib.yaml
M libc/include/string.yaml
M libc/include/sys/stat.yaml
M libc/include/time.yaml
M libc/include/wchar.yaml
M libc/shared/math/cbrtf.h
M libc/shared/rpc.h
M libc/shared/rpc_util.h
M libc/src/__support/CPP/bit.h
M libc/src/__support/FPUtil/NearestIntegerOperations.h
M libc/src/__support/FPUtil/bfloat16.h
M libc/src/__support/FPUtil/comparison_operations.h
M libc/src/__support/FPUtil/generic/add_sub.h
M libc/src/__support/FPUtil/generic/div.h
M libc/src/__support/FPUtil/generic/mul.h
M libc/src/__support/FPUtil/rounding_mode.h
M libc/src/__support/OSUtil/darwin/aarch64/syscall.h
M libc/src/__support/OSUtil/linux/aarch64/syscall.h
M libc/src/__support/OSUtil/linux/arm/syscall.h
M libc/src/__support/OSUtil/linux/i386/syscall.h
M libc/src/__support/OSUtil/linux/riscv/syscall.h
M libc/src/__support/OSUtil/linux/syscall_wrappers/CMakeLists.txt
A libc/src/__support/OSUtil/linux/syscall_wrappers/utimensat.h
M libc/src/__support/OSUtil/linux/x86_64/syscall.h
M libc/src/__support/math/CMakeLists.txt
M libc/src/__support/math/acosf.h
M libc/src/__support/math/acoshf_utils.h
M libc/src/__support/math/asinf.h
M libc/src/__support/math/ceil.h
M libc/src/__support/math/ceilbf16.h
M libc/src/__support/math/ceilf.h
M libc/src/__support/math/ceilf128.h
M libc/src/__support/math/ceilf16.h
M libc/src/__support/math/ceill.h
M libc/src/__support/math/inv_trigf_utils.h
M libc/src/math/atanpif16.h
M libc/src/math/generic/logf.cpp
M libc/src/math/totalorderbf16.h
M libc/src/math/totalordermagbf16.h
M libc/src/string/memory_utils/utils.h
M libc/src/sys/stat/CMakeLists.txt
M libc/src/sys/stat/linux/CMakeLists.txt
A libc/src/sys/stat/linux/utimensat.cpp
A libc/src/sys/stat/utimensat.h
M libc/src/sys/time/linux/CMakeLists.txt
M libc/src/sys/time/linux/utimes.cpp
M libc/test/shared/CMakeLists.txt
A libc/test/shared/shared_math_constexpr_test.cpp
M libc/test/shared/shared_math_test.cpp
M libc/test/src/math/acoshf_test.cpp
M libc/test/src/math/asinhf_test.cpp
M libc/test/src/math/atanhf_test.cpp
M libc/test/src/sys/stat/CMakeLists.txt
A libc/test/src/sys/stat/utimensat_test.cpp
M libc/utils/libctest/format.py
M libclc/clc/include/clc/integer/gentype.inc
A libclc/clc/include/clc/math/clc_atan_helpers.h
A libclc/clc/include/clc/math/clc_atan_helpers_decl.inc
M libclc/clc/include/clc/math/clc_ep_decl.inc
R libclc/clc/include/clc/math/clc_ep_log.h
R libclc/clc/include/clc/math/clc_ep_log_decl.inc
M libclc/clc/include/clc/math/clc_lgamma_r.h
A libclc/clc/include/clc/math/clc_lgamma_r_decl.inc
M libclc/clc/include/clc/math/gentype.inc
M libclc/clc/include/clc/math/math.h
M libclc/clc/include/clc/relational/binary_decl.inc
M libclc/clc/include/clc/relational/unary_decl.inc
M libclc/clc/include/clc/shared/binary_with_out_arg_scalarize.inc
A libclc/clc/include/clc/shared/unary_with_out_arg_scalarize_loop.inc
M libclc/clc/lib/generic/CMakeLists.txt
M libclc/clc/lib/generic/atomic/clc_atomic_exchange.cl
M libclc/clc/lib/generic/atomic/clc_atomic_load.cl
M libclc/clc/lib/generic/atomic/clc_atomic_store.cl
M libclc/clc/lib/generic/common/clc_sign.inc
M libclc/clc/lib/generic/conversion/clc_convert_float.inc
M libclc/clc/lib/generic/conversion/clc_convert_float2float.cl
M libclc/clc/lib/generic/conversion/clc_convert_int2float.cl
M libclc/clc/lib/generic/math/clc_acosh.cl
M libclc/clc/lib/generic/math/clc_acosh.inc
M libclc/clc/lib/generic/math/clc_acospi.cl
M libclc/clc/lib/generic/math/clc_acospi.inc
M libclc/clc/lib/generic/math/clc_asin.cl
M libclc/clc/lib/generic/math/clc_asin.inc
M libclc/clc/lib/generic/math/clc_asinh.cl
M libclc/clc/lib/generic/math/clc_asinh.inc
M libclc/clc/lib/generic/math/clc_asinpi.cl
M libclc/clc/lib/generic/math/clc_asinpi.inc
M libclc/clc/lib/generic/math/clc_atan.cl
M libclc/clc/lib/generic/math/clc_atan.inc
A libclc/clc/lib/generic/math/clc_atan_helpers.cl
A libclc/clc/lib/generic/math/clc_atan_helpers.inc
M libclc/clc/lib/generic/math/clc_atanh.cl
M libclc/clc/lib/generic/math/clc_atanh.inc
M libclc/clc/lib/generic/math/clc_atanpi.cl
M libclc/clc/lib/generic/math/clc_atanpi.inc
M libclc/clc/lib/generic/math/clc_cosh.cl
M libclc/clc/lib/generic/math/clc_cosh.inc
M libclc/clc/lib/generic/math/clc_ep.cl
M libclc/clc/lib/generic/math/clc_ep.inc
R libclc/clc/lib/generic/math/clc_ep_log.cl
R libclc/clc/lib/generic/math/clc_ep_log.inc
M libclc/clc/lib/generic/math/clc_expm1.cl
M libclc/clc/lib/generic/math/clc_expm1.inc
M libclc/clc/lib/generic/math/clc_lgamma_r.cl
M libclc/clc/lib/generic/math/clc_lgamma_r.inc
A libclc/clc/lib/generic/math/clc_lgamma_r_stret.inc
M libclc/clc/lib/generic/math/clc_log1p.cl
M libclc/clc/lib/generic/math/clc_log1p.inc
M libclc/clc/lib/generic/math/clc_sincos_helpers.inc
M libclc/clc/lib/generic/math/clc_sinh.cl
M libclc/clc/lib/generic/math/clc_sinh.inc
M libclc/clc/lib/generic/math/clc_tanh.cl
M libclc/clc/lib/generic/math/clc_tanh.inc
M libclc/clc/lib/generic/math/clc_tgamma.cl
A libclc/clc/lib/generic/math/clc_tgamma.inc
M libclc/opencl/lib/generic/relational/relational_binary_def.inc
M libclc/opencl/lib/generic/relational/relational_unary_def.inc
M libcxx/docs/ReleaseNotes/23.rst
M libcxx/include/__iterator/wrap_iter.h
M libcxx/include/ext/hash_map
A libcxx/test/extensions/gnu/hash_map/non_standard_layout.pass.cpp
A libcxx/test/extensions/gnu/hash_multimap/non_standard_layout.pass.cpp
M lld/ELF/LinkerScript.cpp
A lld/test/wasm/lto/thinlto-shared-memory-atomics.ll
M lld/wasm/LTO.cpp
M lldb/bindings/python/python-wrapper.swig
M lldb/docs/resources/formatterbytecode.rst
M lldb/docs/use/troubleshooting.rst
M lldb/examples/python/formatter_bytecode.py
M lldb/packages/Python/lldbsuite/test/configuration.py
M lldb/packages/Python/lldbsuite/test/decorators.py
M lldb/packages/Python/lldbsuite/test/dotest.py
M lldb/packages/Python/lldbsuite/test/dotest_args.py
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionSourceCode.cpp
M lldb/source/Plugins/Process/FreeBSD-Kernel-Core/ProcessFreeBSDKernelCore.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.h
M lldb/source/Target/ProcessTrace.cpp
M lldb/source/Target/Thread.cpp
A lldb/test/API/lang/cpp/non-type-template-param-member-ptr/Makefile
A lldb/test/API/lang/cpp/non-type-template-param-member-ptr/TestCppNonTypeTemplateParamPtrToMember.py
A lldb/test/API/lang/cpp/non-type-template-param-member-ptr/main.cpp
M lldb/test/API/lit.cfg.py
M lldb/test/API/lit.site.cfg.py.in
M lldb/test/CMakeLists.txt
M lldb/test/Shell/ScriptInterpreter/Python/Inputs/FormatterBytecode/RigidArrayLLDBFormatterC.txt
M lldb/test/Shell/ScriptInterpreter/Python/Inputs/FormatterBytecode/RigidArrayLLDBFormatterSwift.txt
M lldb/unittests/Process/ProcessTraceTest.cpp
M lldb/utils/lldb-dotest/CMakeLists.txt
M lldb/utils/lldb-dotest/lldb-dotest.in
M llvm/docs/Coroutines.rst
M llvm/docs/LangRef.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/ADT/GenericUniformityImpl.h
M llvm/include/llvm/ADT/PointerUnion.h
M llvm/include/llvm/ADT/StringSwitch.h
M llvm/include/llvm/ADT/Uniformity.h
M llvm/include/llvm/Analysis/LazyValueInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/include/llvm/CodeGen/ExpandPostRAPseudos.h
M llvm/include/llvm/ExecutionEngine/Orc/Core.h
M llvm/include/llvm/ExecutionEngine/Orc/EPCGenericJITLinkMemoryManager.h
M llvm/include/llvm/ExecutionEngine/Orc/SelfExecutorProcessControl.h
M llvm/include/llvm/IR/Instructions.h
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/include/llvm/MC/MCELFStreamer.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/MC/MCWinCOFFStreamer.h
M llvm/include/llvm/Support/KnownBits.h
A llvm/include/llvm/Support/NVVMAttributes.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/InstrMaps.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/UniformityAnalysis.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/AsmPrinter/WinCFGuard.cpp
M llvm/lib/CodeGen/MachineSink.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/DebugInfo/BTF/BTFParser.cpp
M llvm/lib/DebugInfo/DWARF/DWARFCompileUnit.cpp
M llvm/lib/DebugInfo/DWARF/DWARFDebugAbbrev.cpp
M llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp
M llvm/lib/DebugInfo/DWARF/DWARFDebugArangeSet.cpp
M llvm/lib/ExecutionEngine/Orc/Core.cpp
M llvm/lib/ExecutionEngine/Orc/EPCGenericJITLinkMemoryManager.cpp
M llvm/lib/ExecutionEngine/Orc/SelfExecutorProcessControl.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/FuzzMutate/RandomIRBuilder.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/MCELFStreamer.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/MC/MCWinCOFFStreamer.cpp
M llvm/lib/Object/ELF.cpp
M llvm/lib/Support/APFloat.cpp
M llvm/lib/Support/DivisionByConstantInfo.cpp
M llvm/lib/Support/Parallel.cpp
M llvm/lib/Support/Unix/Process.inc
M llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
A llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
A llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonLoadStoreWidening.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXCtorDtorLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXGenericToNVVM.cpp
M llvm/lib/Target/NVPTX/NVPTXImageOptimizer.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp
M llvm/lib/Target/NVPTX/NVVMProperties.cpp
M llvm/lib/Target/NVPTX/NVVMProperties.h
M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVInstrPredicates.td
M llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVVSETVLIInfoAnalysis.cpp
M llvm/lib/Target/SPIRV/Analysis/SPIRVConvergenceRegionAnalysis.h
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVBaseInfo.h
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.h
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVTargetStreamer.h
M llvm/lib/Target/SPIRV/SPIRV.h
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVCBufferAccess.h
M llvm/lib/Target/SPIRV/SPIRVCommandLine.h
A llvm/lib/Target/SPIRV/SPIRVCtorDtorLowering.cpp
A llvm/lib/Target/SPIRV/SPIRVCtorDtorLowering.h
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVLegalizeZeroSizeArrays.h
M llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.h
M llvm/lib/Target/SPIRV/SPIRVMetadata.h
M llvm/lib/Target/SPIRV/SPIRVPushConstantAccess.h
M llvm/lib/Target/SPIRV/SPIRVStructurizerWrapper.h
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/SPIRV/SPIRVTypeInst.h
M llvm/lib/Target/Sparc/SparcInstrInfo.cpp
M llvm/lib/Target/WebAssembly/CMakeLists.txt
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
A llvm/lib/Target/WebAssembly/WebAssemblyReduceToAnyAllTrue.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
M llvm/lib/Target/X86/X86AsmPrinter.h
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
M llvm/lib/Transforms/Coroutines/SpillUtils.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BottomUpVec.cpp
M llvm/lib/Transforms/Vectorize/VPlanHelpers.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Analysis/CostModel/RISCV/rvv-extractelement.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-insertelement.ll
M llvm/test/Analysis/DependenceAnalysis/SameSDLoops.ll
M llvm/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll
A llvm/test/Analysis/DependenceAnalysis/weak-crossing-siv-coeff-may-zero.ll
A llvm/test/Analysis/UniformityAnalysis/AMDGPU/uniform_intrinsic.ll
M llvm/test/CodeGen/AArch64/cls.ll
M llvm/test/CodeGen/AArch64/insertextract.ll
M llvm/test/CodeGen/AArch64/pr61549.ll
M llvm/test/CodeGen/AArch64/rem-by-const.ll
A llvm/test/CodeGen/AArch64/sink-and-fold-unique-operand.mir
M llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.live.mask.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
A llvm/test/CodeGen/AMDGPU/atomic_optimizations_single_lane.ll
A llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
A llvm/test/CodeGen/AMDGPU/coexec-sched-warning.mir
M llvm/test/CodeGen/AMDGPU/cube.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubeid.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubema.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubesc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cubetc.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pknorm.u16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.permute.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.compr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane32.swap.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.m0.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
M llvm/test/CodeGen/AMDGPU/permlane16_opsel.ll
A llvm/test/CodeGen/AMDGPU/promote-alloca-placeholder-replacement.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-use-after-erase.ll
M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
M llvm/test/CodeGen/ARM/combine-vmovdrr.ll
M llvm/test/CodeGen/ARM/pr122670-regression.ll
M llvm/test/CodeGen/ARM/vld2.ll
M llvm/test/CodeGen/DirectX/MemIntrinsics/memcpy-pointee.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll
A llvm/test/CodeGen/DirectX/WaveActiveBitAnd.ll
M llvm/test/CodeGen/DirectX/forward_handle_on_alloca.ll
A llvm/test/CodeGen/Hexagon/load-widen-addasl.mir
A llvm/test/CodeGen/Hexagon/store-widen-addasl.mir
M llvm/test/CodeGen/LoongArch/fsqrt-reciprocal-estimate.ll
M llvm/test/CodeGen/LoongArch/lasx/fsqrt-reciprocal-estimate.ll
M llvm/test/CodeGen/LoongArch/lasx/issue170976.ll
M llvm/test/CodeGen/LoongArch/lsx/fsqrt-reciprocal-estimate.ll
M llvm/test/CodeGen/NVPTX/i1-int-to-fp.ll
M llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg-mir.ll
M llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
M llvm/test/CodeGen/PowerPC/aix32-p8-scalar_vector_conversions.ll
M llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
M llvm/test/CodeGen/PowerPC/mergeable-string-pool-large.ll
M llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll
M llvm/test/CodeGen/PowerPC/pr59074.ll
M llvm/test/CodeGen/PowerPC/signbit-shift.ll
M llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/wide-scalar-shift-by-byte-multiple-legalization.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/features-info.ll
A llvm/test/CodeGen/RISCV/fold-addi-loadstore-cpi.mir
M llvm/test/CodeGen/RISCV/pr148084.ll
M llvm/test/CodeGen/RISCV/rvv/cttz-elts.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vector-extract-last-active.ll
A llvm/test/CodeGen/RISCV/sfb-merge-base-offset.ll
M llvm/test/CodeGen/RISCV/urem-lkk.ll
M llvm/test/CodeGen/RISCV/xaluo.ll
M llvm/test/CodeGen/RISCV/xqcisls.ll
M llvm/test/CodeGen/RISCV/xtheadmemidx.ll
A llvm/test/CodeGen/SPIRV/bool-vector-bitcast.ll
A llvm/test/CodeGen/SPIRV/ctor-dtor-lowering-ir.ll
A llvm/test/CodeGen/SPIRV/ctor-dtor-lowering.ll
A llvm/test/CodeGen/SPIRV/ctor-dtor-no-openmp-ir.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveBitAnd.ll
M llvm/test/CodeGen/SPIRV/llc-pipeline.ll
A llvm/test/CodeGen/SPIRV/llvm-intrinsics/masked-load-store.ll
M llvm/test/CodeGen/SPIRV/transcoding/BuildNDRange.ll
R llvm/test/CodeGen/SPIRV/transcoding/BuildNDRange_2.ll
A llvm/test/CodeGen/SPIRV/transcoding/BuildNDRange_no_sret.ll
M llvm/test/CodeGen/VE/Scalar/ctlz.ll
A llvm/test/CodeGen/WebAssembly/any-all-true.ll
M llvm/test/CodeGen/WebAssembly/load-ext.ll
A llvm/test/CodeGen/WinCFGuard/cfguard-alias.ll
M llvm/test/CodeGen/X86/avx512-insert-extract.ll
M llvm/test/CodeGen/X86/bitcnt-big-integer.ll
M llvm/test/CodeGen/X86/clmul-vector.ll
M llvm/test/CodeGen/X86/divmod128.ll
M llvm/test/CodeGen/X86/i128-udiv.ll
M llvm/test/CodeGen/X86/known-bits.ll
M llvm/test/CodeGen/X86/npm-asmprint.ll
A llvm/test/CodeGen/X86/post-ra-pseudos.mir
M llvm/test/CodeGen/X86/vec-strict-cmp-128.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
M llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
M llvm/test/Instrumentation/AddressSanitizer/remove-memory-effects.ll
M llvm/test/MC/AMDGPU/gfx1250_asm_wmma_w32.s
M llvm/test/MC/AMDGPU/gfx1250_asm_wmma_w32_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_wmma_w32.txt
A llvm/test/MC/Hexagon/checker-solo-cof-slots.s
A llvm/test/MC/Hexagon/elf-reloc-variants.s
A llvm/test/MC/Hexagon/packet-constraint-checks.s
A llvm/test/MC/Hexagon/reloc-data-sizes.s
A llvm/test/MC/Hexagon/reloc-tls-gd.s
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/test/MC/RISCV/rv32p-invalid.s
M llvm/test/MC/RISCV/rv32p-valid.s
M llvm/test/MC/RISCV/rv64p-invalid.s
M llvm/test/MC/RISCV/rv64p-valid.s
R llvm/test/MC/RISCV/xrivosvisni-valid.s
A llvm/test/Transforms/Coroutines/coro-alloca-10.ll
A llvm/test/Transforms/Coroutines/coro-split-addrspace.ll
M llvm/test/Transforms/GVN/PRE/no-pre-load-for-token-like.ll
M llvm/test/Transforms/GVN/no-sink-dxgetpointer.ll
A llvm/test/Transforms/InstCombine/nanless-canonicalize-combine.ll
A llvm/test/Transforms/JumpThreading/update-bpi-bfi-unfold-select.ll
M llvm/test/Transforms/LoopFusion/da_separate_loops.ll
M llvm/test/Transforms/LoopVectorize/2016-07-27-loop-vec.ll
A llvm/test/Transforms/LoopVectorize/AArch64/binop-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-factors.ll
M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-widen-inductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/f128-fmuladd-reduction.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/gather-do-not-vectorize-addressing.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-runtime-checks.ll
M llvm/test/Transforms/LoopVectorize/AArch64/intrinsiccost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/low_trip_count_predicates.ll
M llvm/test/Transforms/LoopVectorize/AArch64/neon-inloop-reductions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/nontemporal-load-store.ll
M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-epilogue.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-sub-epilogue-vec.ll
M llvm/test/Transforms/LoopVectorize/AArch64/pr33053.ll
M llvm/test/Transforms/LoopVectorize/AArch64/pr36032.ll
M llvm/test/Transforms/LoopVectorize/AArch64/predicated-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/prefer-fixed-if-equal-to-scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-illegal-type.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-invalid-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-known-trip-count.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reg-pressure-spills.ll
M llvm/test/Transforms/LoopVectorize/ARM/prefer-tail-loop-folding.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-allowed.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-counting-down.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-loop-hint.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-not-allowed.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-prefer-flag.ll
M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-reductions-allowed.ll
M llvm/test/Transforms/LoopVectorize/Hexagon/minimum-vf.ll
M llvm/test/Transforms/LoopVectorize/LoongArch/loongarch-interleaved.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/exit-branch-cost.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/interleave_IC.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization-profitability.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/predcost.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/vectorize-bswap.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-call.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/widened-massv-vfabi-attr.ll
M llvm/test/Transforms/LoopVectorize/RISCV/illegal-type.ll
M llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-interleaved.ll
M llvm/test/Transforms/LoopVectorize/Sparc/no-vectorize.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/mem-interleaving-costs-03.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/predicated-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/VE/disable_lv.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-half.ll
M llvm/test/Transforms/LoopVectorize/X86/amdlibm-calls.ll
M llvm/test/Transforms/LoopVectorize/X86/conversion-cost.ll
A llvm/test/Transforms/LoopVectorize/X86/cost-divisor-overflow.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/X86/epilog-vectorization-inductions.ll
M llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll
M llvm/test/Transforms/LoopVectorize/X86/gather_scatter.ll
M llvm/test/Transforms/LoopVectorize/X86/int128_no_gather.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave_short_tc.ll
M llvm/test/Transforms/LoopVectorize/X86/interleaved-accesses-use-after-free.ll
M llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
M llvm/test/Transforms/LoopVectorize/X86/pr35432.ll
M llvm/test/Transforms/LoopVectorize/X86/pr54634.ll
M llvm/test/Transforms/LoopVectorize/X86/reg-usage-debug.ll
M llvm/test/Transforms/LoopVectorize/X86/scatter_crash.ll
M llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
M llvm/test/Transforms/LoopVectorize/X86/tail_folding_and_assume_safety.ll
M llvm/test/Transforms/LoopVectorize/X86/tail_loop_folding.ll
M llvm/test/Transforms/LoopVectorize/X86/transform-narrow-interleave-to-widen-memory-epilogue-vec.ll
M llvm/test/Transforms/LoopVectorize/X86/transform-narrow-interleave-to-widen-memory.ll
M llvm/test/Transforms/LoopVectorize/X86/uniformshift.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-store-accesses-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-pr39099.ll
M llvm/test/Transforms/LoopVectorize/diag-missing-instr-debug-loc.ll
M llvm/test/Transforms/LoopVectorize/diag-with-hotness-info-2.ll
M llvm/test/Transforms/LoopVectorize/diag-with-hotness-info.ll
M llvm/test/Transforms/LoopVectorize/discriminator.ll
M llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-const-TC.ll
M llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-divisible-TC.ll
M llvm/test/Transforms/LoopVectorize/epilog-iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-any-of-reductions.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-reductions.ll
M llvm/test/Transforms/LoopVectorize/explicit_outer_detection.ll
M llvm/test/Transforms/LoopVectorize/explicit_outer_nonuniform_inner.ll
M llvm/test/Transforms/LoopVectorize/explicit_outer_uniform_diverg_branch.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-complex.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/fix-reduction-dbg.ll
M llvm/test/Transforms/LoopVectorize/forked-pointers.ll
M llvm/test/Transforms/LoopVectorize/induction-ptrcasts.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-1.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-2.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-masked-group.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-uniform-load.ll
M llvm/test/Transforms/LoopVectorize/libcall-remark.ll
M llvm/test/Transforms/LoopVectorize/memdep-fold-tail.ll
M llvm/test/Transforms/LoopVectorize/memdep.ll
M llvm/test/Transforms/LoopVectorize/memory-dep-remarks.ll
M llvm/test/Transforms/LoopVectorize/middle-block-dbg.ll
M llvm/test/Transforms/LoopVectorize/no_array_bounds_scalable.ll
M llvm/test/Transforms/LoopVectorize/nounroll.ll
M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction-index-width-smaller-than-iv-width.ll
M llvm/test/Transforms/LoopVectorize/pr30654-phiscev-sext-trunc.ll
M llvm/test/Transforms/LoopVectorize/pr31098.ll
M llvm/test/Transforms/LoopVectorize/pr33706.ll
M llvm/test/Transforms/LoopVectorize/pr35773.ll
M llvm/test/Transforms/LoopVectorize/pr38800.ll
M llvm/test/Transforms/LoopVectorize/pr39099.ll
M llvm/test/Transforms/LoopVectorize/pr51614-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/runtime-check.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-counting-down.ll
M llvm/test/Transforms/LoopVectorize/unroll-novec-memcheck-metadata.ll
M llvm/test/Transforms/LoopVectorize/vect-phiscev-sext-trunc.ll
M llvm/test/Transforms/LoopVectorize/vectorizeVFone.ll
M llvm/test/Transforms/PhaseOrdering/X86/pr48844-br-to-switch-vectorization.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/icmp-wrong-bitwidth.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/trunc-insertion.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/unprofitable-alternate-subtree.ll
A llvm/test/Transforms/SLPVectorizer/WebAssembly/simd-splat-shuffle-cost.ll
A llvm/test/Transforms/SLPVectorizer/X86/reduction-across-different-bb.ll
A llvm/test/Transforms/SLPVectorizer/order-reduction-infinite-loop.ll
M llvm/test/Transforms/SandboxVectorizer/bottomup_basic.ll
M llvm/test/Transforms/SandboxVectorizer/external_uses.ll
M llvm/test/Transforms/SandboxVectorizer/scheduler.ll
M llvm/test/Transforms/SimplifyCFG/DirectX/no-sink-dxgetpointer.ll
M llvm/test/Transforms/SimplifyCFG/token_like_type.ll
M llvm/test/tools/llc/mattr-mcpu-help.ll
M llvm/test/tools/llc/mtune.ll
A llvm/test/tools/llvm-lipo/remove.test
A llvm/test/tools/opt/mattr-mcpu-help.ll
A llvm/test/tools/sancov/XCOFF/lit.local.cfg
A llvm/test/tools/sancov/XCOFF/xcoff-sancov-symbols.test
M llvm/tools/llc/llc.cpp
M llvm/tools/llvm-lipo/LipoOpts.td
M llvm/tools/llvm-lipo/llvm-lipo.cpp
M llvm/tools/llvm-ml/Disassembler.cpp
M llvm/tools/llvm-symbolizer/llvm-symbolizer.cpp
M llvm/tools/opt/optdriver.cpp
M llvm/tools/sancov/sancov.cpp
M llvm/unittests/ADT/PointerUnionTest.cpp
M llvm/unittests/ADT/StringSwitchTest.cpp
M llvm/unittests/DebugInfo/DWARF/DWARFExpressionCopyBytesTest.cpp
M llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp
M llvm/unittests/ExecutionEngine/Orc/EPCGenericJITLinkMemoryManagerTest.cpp
M llvm/unittests/FuzzMutate/StrategiesTest.cpp
M llvm/unittests/IR/PatternMatch.cpp
M llvm/unittests/MC/DwarfLineTableHeaders.cpp
M llvm/unittests/SandboxIR/TrackerTest.cpp
M llvm/unittests/Support/FormatVariadicTest.cpp
M llvm/unittests/Support/KnownBitsTest.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/InstrMapsTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
M llvm/utils/git/github-automation.py
M llvm/utils/gn/secondary/lldb/test/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn
M mlir/docs/Bindings/Python.md
M mlir/include/mlir/Bindings/Python/IRCore.h
M mlir/include/mlir/Conversion/ControlFlowToSCF/ControlFlowToSCF.h
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/SCF/IR/SCF.h
M mlir/include/mlir/Dialect/SCF/IR/SCFOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td
M mlir/include/mlir/Dialect/X86/X86.td
M mlir/include/mlir/Dialect/XeGPU/TransformOps/XeGPUTransformOps.td
M mlir/include/mlir/IR/OpImplementation.h
M mlir/include/mlir/Interfaces/MemorySlotInterfaces.td
M mlir/include/mlir/Transforms/CFGToSCF.h
M mlir/include/mlir/Transforms/Passes.td
M mlir/lib/AsmParser/AsmParserImpl.h
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Conversion/ControlFlowToSCF/ControlFlowToSCF.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/TilingInterfaceImpl.cpp
M mlir/lib/Dialect/Math/Transforms/PolynomialApproximation.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefMemorySlot.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/lib/Dialect/SCF/IR/CMakeLists.txt
A mlir/lib/Dialect/SCF/IR/MemorySlot.cpp
M mlir/lib/Dialect/Shard/Transforms/ShardingPropagation.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaReduceTransposes.cpp
M mlir/lib/Dialect/X86/IR/X86Dialect.cpp
M mlir/lib/Dialect/X86/Transforms/ShuffleVectorFMAOps.cpp
M mlir/lib/Dialect/X86/Transforms/VectorContractBF16ToFMA.cpp
M mlir/lib/Dialect/X86/Transforms/VectorContractToPackedTypeDotProduct.cpp
M mlir/lib/Dialect/XeGPU/TransformOps/XeGPUTransformOps.cpp
M mlir/lib/Pass/PassRegistry.cpp
M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
M mlir/lib/Transforms/Mem2Reg.cpp
M mlir/lib/Transforms/Utils/CFGToSCF.cpp
M mlir/python/mlir/dialects/transform/xegpu.py
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
M mlir/test/Conversion/ArithToLLVM/convert-nd-vector-to-llvmir.mlir
A mlir/test/Conversion/ControlFlowToSCF/invalid.mlir
M mlir/test/Conversion/ControlFlowToSCF/unknown-cf-op.mlir
M mlir/test/Conversion/MemRefToLLVM/expand-then-convert-to-llvm.mlir
M mlir/test/Dialect/Affine/ops.mlir
M mlir/test/Dialect/Arith/canonicalize.mlir
M mlir/test/Dialect/Arith/invalid.mlir
M mlir/test/Dialect/Arith/ops.mlir
M mlir/test/Dialect/Builtin/Bytecode/builtin_fixed.mlir
M mlir/test/Dialect/LLVMIR/mem2reg.mlir
M mlir/test/Dialect/Linalg/invalid.mlir
M mlir/test/Dialect/Linalg/transform-tile-reduction.mlir
M mlir/test/Dialect/MemRef/expand-strided-metadata.mlir
M mlir/test/Dialect/MemRef/mem2reg.mlir
A mlir/test/Dialect/SCF/mem2reg-reject.mlir
A mlir/test/Dialect/SCF/mem2reg.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops.mlir
M mlir/test/Dialect/XeGPU/transform-ops-invalid.mlir
M mlir/test/Dialect/XeGPU/transform-ops.mlir
M mlir/test/IR/enum-attr-roundtrip.mlir
M mlir/test/Interfaces/TilingInterface/tile-and-fuse-with-reduction-tiling.mlir
A mlir/test/Target/LLVMIR/openmp-taskloop-bounds-cast.mlir
M mlir/test/Target/SPIRV/tosa-ops.mlir
M mlir/test/Transforms/mem2reg.mlir
M mlir/test/lib/Dialect/Test/TestEnumDefs.td
M mlir/test/lib/Dialect/Test/TestOpsSyntax.td
M mlir/test/python/dialects/transform_xegpu_ext.py
M mlir/tools/mlir-tblgen/EnumsGen.cpp
M offload/plugins-nextgen/amdgpu/src/rtl.cpp
M offload/plugins-nextgen/common/include/PluginInterface.h
M offload/plugins-nextgen/common/include/RPC.h
M offload/plugins-nextgen/common/src/PluginInterface.cpp
M offload/plugins-nextgen/common/src/RPC.cpp
M offload/plugins-nextgen/level_zero/include/L0Device.h
M offload/plugins-nextgen/level_zero/include/L0Kernel.h
M offload/plugins-nextgen/level_zero/include/L0Trace.h
M offload/plugins-nextgen/level_zero/src/L0Context.cpp
M offload/plugins-nextgen/level_zero/src/L0Device.cpp
M offload/plugins-nextgen/level_zero/src/L0Kernel.cpp
M offload/plugins-nextgen/level_zero/src/L0Plugin.cpp
M offload/plugins-nextgen/level_zero/src/L0Program.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/kparzysz/e15-length-reason
Compare: https://github.com/llvm/llvm-project/compare/398af19c8eb7...2fc7fbeab04b
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