[all-commits] [llvm/llvm-project] 94239b: [AMDGPU][GlobalISel] Add RegBankLegalize rules for...

[Anshil Gandhi via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 94239b34508d48434f73b1b8ae874e9ec6d83d2b
      https://github.com/llvm/llvm-project/commit/94239b34508d48434f73b1b8ae874e9ec6d83d2b
  Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
  Date:   2026-03-23 (Mon, 23 Mar 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
    M llvm/test/CodeGen/AMDGPU/permlane16_opsel.ll

  Log Message:
  -----------
  [AMDGPU][GlobalISel] Add RegBankLegalize rules for permlane16/permlanex16 (#187906)

Add RegBankLegalize rules for the amdgcn_permlane16
and amdgcn_permlanex16 intrinsics. Both intrinsics
are sources of divergence, so only the divergent
case is needed: result, old, and src0 map to VGPR,
while src1 and src2 are SGPR with ReadFirstLane if
divergent.

Update the GISEL RUN lines in llvm.amdgcn.permlane.ll
and permlane16_opsel.ll to use -new-reg-bank-select,
and regenerate check lines. The v8i16 test cases now
produce identical SDAG/GISEL output so their checks
are unified.



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