[all-commits] [llvm/llvm-project] c4b01e: [LoongArch] Mark VPICK_ZEXT_ELT as zero-extending ...

[hev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c4b01ec20d3e845d348b0b005102b1301a8550ca
      https://github.com/llvm/llvm-project/commit/c4b01ec20d3e845d348b0b005102b1301a8550ca
  Author: hev <wangrui at loongson.cn>
  Date:   2026-03-23 (Mon, 23 Mar 2026)

  Changed paths:
    M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
    M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
    M llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve2gr.ll
    M llvm/test/CodeGen/LoongArch/lsx/intrinsic-pickve2gr.ll

  Log Message:
  -----------
  [LoongArch] Mark VPICK_ZEXT_ELT as zero-extending in computeKnownBits (#187177)

Teach computeKnownBitsForTargetNode that VPICK_ZEXT_ELT produces a
zero-extended result.

VPICK_ZEXT_ELT extracts a narrower element (e.g. i16) and returns it in
a larger integer type (e.g. i64) with the upper bits guaranteed to be
zero. However, without KnownBits information, LLVM treats the upper bits
as unknown, which inhibits optimizations.

By marking all bits above the source element width as known zero, this
enables DAG combine and other optimizations to eliminate redundant
operations such as AND masks and SIGN_EXTEND_INREG.

For example, this allows patterns like:

  (sign_extend_inreg (VPICK_ZEXT_ELT ...), i32)

to be simplified when the sign bit is known to be zero.



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