[all-commits] [llvm/llvm-project] b44434: Improved ISD::SRL handling in isKnownToBeAPowerOfT...

[Iasonaskrpr via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b44434474e7812dab35f635fc18a9564e9aa1c01
      https://github.com/llvm/llvm-project/commit/b44434474e7812dab35f635fc18a9564e9aa1c01
  Author: Iasonaskrpr <126663668+Iasonaskrpr at users.noreply.github.com>
  Date:   2026-03-14 (Sat, 14 Mar 2026)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/X86/known-pow2.ll

  Log Message:
  -----------
  Improved ISD::SRL handling in isKnownToBeAPowerOfTwo (#182562)

Fixes #181651

Added DemandedElts argument to isConstOrConstSplat and to
isKnowTobePowerOfTwo calls and OrZero || isKnownNeverZero(Val, Depth) is
checked before isKnowTobePowerOfTwo. Also added unit tests.



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