[all-commits] [llvm/llvm-project] bc5c3a: [X86] Add correct model values for znver1, znver2 ...

[Gergo Stomfai via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bc5c3a07fb8d70a20946976a5950db2f3f87d122
      https://github.com/llvm/llvm-project/commit/bc5c3a07fb8d70a20946976a5950db2f3f87d122
  Author: Gergo Stomfai <stomfaig at gmail.com>
  Date:   2026-03-13 (Fri, 13 Mar 2026)

  Changed paths:
    M llvm/lib/Target/X86/X86ScheduleZnver1.td
    M llvm/lib/Target/X86/X86ScheduleZnver2.td
    M llvm/test/tools/llvm-mca/X86/Znver1/resources-x86_64.s
    M llvm/test/tools/llvm-mca/X86/Znver2/resources-x86_64.s

  Log Message:
  -----------
  [X86] Add correct model values for znver1, znver2 shld, shrd (#186175)

Values are from Agner Fog's tables, which also match uops.info expect for latency, which for which I used a similar pattern as in zvner3 and 4



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