[all-commits] [llvm/llvm-project] db7e0d: [RISCV][MC] Add support of Zvzip extension (#185614)

[Pengcheng Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: db7e0daa85480dbd9be9dfdb5701479aa760b03d
      https://github.com/llvm/llvm-project/commit/db7e0daa85480dbd9be9dfdb5701479aa760b03d
  Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
  Date:   2026-03-11 (Wed, 11 Mar 2026)

  Changed paths:
    M clang/test/Driver/print-supported-extensions-riscv.c
    M clang/test/Preprocessor/riscv-target-features.c
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.md
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    A llvm/lib/Target/RISCV/RISCVInstrInfoZvzip.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/CodeGen/RISCV/features-info.ll
    M llvm/test/MC/RISCV/attribute-arch.s
    A llvm/test/MC/RISCV/rvv/zvzip-invalid.s
    A llvm/test/MC/RISCV/rvv/zvzip.s
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISCV][MC] Add support of Zvzip extension (#185614)

This adds the initial support of the `Zvzip` standard extension for
reordering structured data in vector registers.

Doc:

*
https://github.com/ved-rivos/riscv-isa-manual/blob/zvzip/src/zvzip.adoc
*
https://github.com/riscv/riscv-opcodes/blob/master/extensions/unratified/rv_zvzip.

Co-Authored-By: wangboyao <wangboyao at bytedance.com>

---------

Co-authored-by: wangboyao <wangboyao at bytedance.com>



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