[all-commits] [llvm/llvm-project] 53a2fd: [DAGCombiner] Combine (fshl A, B, S) | (fshr C, D, ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 53a2fd99aa7d55051db03b6f389814c6b6741502
      https://github.com/llvm/llvm-project/commit/53a2fd99aa7d55051db03b6f389814c6b6741502
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2026-03-10 (Tue, 10 Mar 2026)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/X86/icmp-shift-opt.ll

  Log Message:
  -----------
  [DAGCombiner] Combine (fshl A, B, S) | (fshr C, D, BW-S) --> (fshl (A|C), (B|D), S) (#180889)

This is similar to the FSHL/FSHR handling in
hoistLogicOpWithSameOpcodeHands.
Here the opcodes aren't exactly the same, but the operations are
equivalent.

Fixes regressions from #180888



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