[all-commits] [llvm/llvm-project] 48473d: [RISCV] Handle sign_extend of i32 in insert_vector...

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 48473ddcc75b49ff9d8c912d86b98be33c861ccf
      https://github.com/llvm/llvm-project/commit/48473ddcc75b49ff9d8c912d86b98be33c861ccf
  Author: Jim Lin <jim at andestech.com>
  Date:   2026-03-10 (Tue, 10 Mar 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll

  Log Message:
  -----------
  [RISCV] Handle sign_extend of i32 in insert_vector_elt for RV32 (#185548)

On RV32 with <N x i64> vectors, inserting a value that is a
sign_extend of an i32 only uses the lower 32 bits, so it can be
lowered without scalar legalization, same as i32 constants.



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