[all-commits] [llvm/llvm-project] 43a0e5: [Hexagon] Add new register input/output types for ...

[Fateme Hosseini via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 43a0e59a34b15183d01cf2ce0eb0e9c9f9606048
      https://github.com/llvm/llvm-project/commit/43a0e59a34b15183d01cf2ce0eb0e9c9f9606048
  Author: Fateme Hosseini <Fhossein at qti.qualcomm.com>
  Date:   2026-03-09 (Mon, 09 Mar 2026)

  Changed paths:
    M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
    M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
    M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h

  Log Message:
  -----------
  [Hexagon] Add new register input/output types for qf instructions (#184398)

The v81 iset has been updated with input and output register
types/extensions for instructions. Currently, it supports qf32/qf16
register types. This patch implements a qf reg type lookup to query
these types. In the future, the register type extractor can be improved
and more APIs can be added to support other register types.

Co-authored-by: <santdas at qti.qualcomm.com>



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