[all-commits] [llvm/llvm-project] 404b3e: [CIR][AArch64] Add support for the remaining `vceq...

[Andrzej Warzyński via All-commits]

  Branch: refs/heads/users/banach-space/cir/vceqz
  Home:   https://github.com/llvm/llvm-project
  Commit: 404b3ea55322d6b97f951c035dd3da7e9b83732f
      https://github.com/llvm/llvm-project/commit/404b3ea55322d6b97f951c035dd3da7e9b83732f
  Author: Andrzej Warzynski <andrzej.warzynski at arm.com>
  Date:   2026-03-09 (Mon, 09 Mar 2026)

  Changed paths:
    M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
    M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
    M clang/test/CodeGen/AArch64/neon-intrinsics.c
    M clang/test/CodeGen/AArch64/neon/fullfp16.c
    M clang/test/CodeGen/AArch64/neon/intrinsics.c
    M clang/test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c

  Log Message:
  -----------
  [CIR][AArch64] Add support for the remaining `vceqz` builtins

Implement the remaining CIR lowerings for the AdvSIMD (Neon)
`vceqz` intrinsic group (bitwise equal to zero).

Most variants of `vceqz` variant were already supported; this patch
completes the rest of the group [1] that was left as a TODO.

Tests for these intrinsics are moved from:
  * test/CodeGen/AArch64/neon_intrinsics.c
  * test/CodeGen/AArch64/v8.2a-fp16-intrinsics.c

to:
  * test/CodeGen/AArch64/neon/intrinsics.c
  * test/CodeGen/AArch64/neon/fullfp16,

respectively.

The implementation largely mirrors the existing lowering in
CodeGen/TargetBuiltins/ARM.cpp.

Reference:
[1] https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#bitwise-equal-to-zero



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