[all-commits] [llvm/llvm-project] a7e4d0: [AMDGPU] Add structural stall heuristic to schedul...

[Austin Kerbow via All-commits]

  Branch: refs/heads/users/kerbowa/structural-vs-latency-stall-heuristic
  Home:   https://github.com/llvm/llvm-project
  Commit: a7e4d0968b0ce47d4f3ea47073f95a2c87089acf
      https://github.com/llvm/llvm-project/commit/a7e4d0968b0ce47d4f3ea47073f95a2c87089acf
  Author: Austin Kerbow <Austin.Kerbow at amd.com>
  Date:   2026-03-08 (Sun, 08 Mar 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
    M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
    M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
    M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
    M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
    M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir

  Log Message:
  -----------
  [AMDGPU] Add structural stall heuristic to scheduling strategies

Implements a structural stall heuristic that considers both resource
hazards and latency constraints when selecting instructions. In coexec,
this changes the pending queue from a binary “not ready to issue”
distinction into part of a unified candidate comparison. Pending
instructions still identify structural stalls in the current cycle, but
they are now evaluated directly against available instructions by stall
cost, making the heuristics both more intuitive and more expressive.

- Add getStructuralStallCycles() to GCNSchedStrategy that computes the
number of cycles an instruction must wait due to:
  - Resource conflicts on unbuffered resources (from the SchedModel)
  - Sequence-dependent hazards (from GCNHazardRecognizer)

- Add getHazardWaitStates() to GCNHazardRecognizer that returns the number
of wait states until all hazards for an instruction are resolved,
providing cycle-accurate hazard information for scheduling heuristics.


  Commit: ed37edef1134c4a792c88dcc8ccf196f7119fe2f
      https://github.com/llvm/llvm-project/commit/ed37edef1134c4a792c88dcc8ccf196f7119fe2f
  Author: Austin Kerbow <Austin.Kerbow at amd.com>
  Date:   2026-03-08 (Sun, 08 Mar 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir

  Log Message:
  -----------
  Update coexec-sched-effective-stall.mir


Compare: https://github.com/llvm/llvm-project/compare/32eb4505662c...ed37edef1134

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