[all-commits] [llvm/llvm-project] 1c16ad: [LLVM][AArch64] Add native ct.select support for A...

[Julius Alexandre via All-commits]

  Branch: refs/heads/users/wizardengineer/ct-select-aarch64
  Home:   https://github.com/llvm/llvm-project
  Commit: 1c16ad4fadd9b8533bd2a340a526ec23fe129aba
      https://github.com/llvm/llvm-project/commit/1c16ad4fadd9b8533bd2a340a526ec23fe129aba
  Author: wizardengineer <juliuswoosebert at gmail.com>
  Date:   2026-03-07 (Sat, 07 Mar 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64MCInstLower.cpp
    A llvm/test/CodeGen/AArch64/ctselect.ll

  Log Message:
  -----------
  [LLVM][AArch64] Add native ct.select support for ARM64

This patch implements architecture-specific lowering for ct.select on AArch64
using CSEL (conditional select) instructions for constant-time selection.

Implementation details:
- Uses CSEL family of instructions for scalar integer types
- Uses FCSEL for floating-point types (F16, BF16, F32, F64)
- Post-RA MC lowering to convert pseudo-instructions to real CSEL/FCSEL
- Handles vector types appropriately
- Comprehensive test coverage for AArch64

The implementation includes:
- ISelLowering: Custom lowering to CTSELECT pseudo-instructions
- InstrInfo: Pseudo-instruction definitions and patterns
- MCInstLower: Post-RA lowering of pseudo-instructions to actual CSEL/FCSEL
- Proper handling of condition codes for constant-time guarantees



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