[all-commits] [llvm/llvm-project] f7ca74: [RISCV] Add register overlap checks to the assembl...

[joshua-arch1 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f7ca74f600cb6360b4255fc849ac21dd13a56a4c
      https://github.com/llvm/llvm-project/commit/f7ca74f600cb6360b4255fc849ac21dd13a56a4c
  Author: joshua-arch1 <cooper.joshua at linux.alibaba.com>
  Date:   2026-03-05 (Thu, 05 Mar 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    A llvm/test/MC/RISCV/rvv/zvlsseg-invalid.s

  Log Message:
  -----------
  [RISCV] Add register overlap checks to the assembler for vector indexed segment load (#184569)

The destination vector register group cannot overlap the source vector
register group for vector indexed segment load. This patch is to add
register overlap checks to the assembler.



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