[all-commits] [llvm/llvm-project] 50826f: [mlir][MemRef] Add position-based matching heurist...
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Thu Mar 5 17:07:55 PST 2026
Branch: refs/heads/users/vitalybuka/spr/libcstring-improve-constexpr-performance
Home: https://github.com/llvm/llvm-project
Commit: 50826f9c3b9c31bcc77846ba00ef106d0e0abc83
https://github.com/llvm/llvm-project/commit/50826f9c3b9c31bcc77846ba00ef106d0e0abc83
Author: Abhishek Varma <avarma094 at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/test/Dialect/MemRef/canonicalize.mlir
M mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
Log Message:
-----------
[mlir][MemRef] Add position-based matching heuristics for rank-reduction with dynamic strides (#184334)
When multiple source dimensions have multiple unit dimensions,
stride-based disambiguation can be wrong with dynamic strides. Add
position-based matching: for each result dimension in order, pick the
leftmost unmatched source dimension with the same size; unmatched source
dims are dropped.
Example: subview from memref<1x8x1x3> to memref<1x8x3>. Both dim 0 and
dim 2 have size 1. Stride-based logic cannot distinguish when strides
are dynamic. Position-based matching correctly drops dim 2 (middle unit
dim) instead of dim 0.
When we have non-trivial static strides, we make use of the stride-based
logic, else we fall back to position-based logic as introduced by this
patch.
INPUT :-
```
func.func @fold_rank_reducing_subview_1x8x1x3_to_1x8x3_drop_middle_unit_dim(
%arg0 : memref<?x?x?x?xf32, strided<[?, ?, ?, ?], offset: ?>>,
%arg1 : index, %arg2 : index, %arg3 : index, %arg4 : index) -> f32 {
%c0 = arith.constant 0 : index
%0 = memref.subview %arg0[0, 0, 0, 0][1, 8, 1, 3][1, 1, 1, 1]
: memref<?x?x?x?xf32, strided<[?, ?, ?, ?], offset: ?>> to
memref<1x8x3xf32, strided<[?, ?, ?], offset: ?>>
%1 = memref.load %0[%c0, %arg1, %arg2] : memref<1x8x3xf32, strided<[?, ?, ?], offset: ?>>
return %1 : f32
}
```
WITHOUT this patch we get :-
```
memref.load %0[%c0, %c0, %arg1, %arg2]
```
WITH this patch we get :-
```
memref.load %0[%c0, %arg1, %c0, %arg2]
```
Signed-off-by: Abhishek Varma <abhvarma at amd.com>
Commit: b414d7795d2965ffaa9457a7e56dca76fd07cce1
https://github.com/llvm/llvm-project/commit/b414d7795d2965ffaa9457a7e56dca76fd07cce1
Author: Kirill Vedernikov <kvedernikov at nvidia.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-block-scale-shared.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-block-scale-tensor.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-invalid.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-sp-block-scale-shared.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-sp-block-scale-tensor.mlir
Log Message:
-----------
[MLIR][NVVM] Unify and move to a single tcgen05_mma_kind attr for all tcgen05.mma Ops (#184433)
This change unifies using of `tcgen05_mma_kind` attribute for
tcgen05.mma Ops in MLIR.
Before this change there were two block scale attributes used for
tcgen05.mma Ops. One was `MMABlockScaleKindAttr` with `mxf8f6f4`, `mxf4`
and `fxf4nvf4` values used for `tcgen05.mma.block_scale` and
`tcgen05.mma.sp.block_scale`. Another one was `Tcgen05MMAKindAttr` with
`f16`, `tf32`, `f8f6f4` and `i8` values used for `tcgen05.mma`,
`tcgen05.mma.sp`, `tcgen05.mma.ws` and `tcgen05.mma.ws.sp`.
`Tcgen05MMAKindAttr` has been extended with values from
`MMABlockScaleKindAttr`. Now there is `tcgen05_mma_kind` attribute only
for all `tcgen05.mma` Ops in MLIR.
Backward compatibility is not supported. Existing tests and scripts
should be updated to use `tcgen05_mma_kind` attribute instead of
`block_scale_kind` for all tcgen05.mma MLIR Ops.
Commit: d998a70c86389a1b9c44413270897c0cb8472374
https://github.com/llvm/llvm-project/commit/d998a70c86389a1b9c44413270897c0cb8472374
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M libclc/CMakeLists.txt
Log Message:
-----------
libclc: Fix checking for arch including OS in wrong place (#184683)
Commit: d5378dafa2af38164c2577a36c7a6c6aa0249d9f
https://github.com/llvm/llvm-project/commit/d5378dafa2af38164c2577a36c7a6c6aa0249d9f
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZInstrVector.td
A llvm/test/CodeGen/SystemZ/fminimumnum-fmaximumnum.ll
Log Message:
-----------
[SystemZ] Mark fminimumnum/fmaximumnum as legal (#184595)
In M=4 mode, the behavior matches IEEE 754-2019 minimumNumber, except
that if both operands are sNaN, the result will be sNaN rather than
qNaN. However, this is explicitly allowed for LLVM's minimumnum
intrinsic, as canonicalization can be omitted for non-constrainted FP.
As such, mark fminimumnum/fmaximumnum as legal, and lower them the same
way as fminnum/fmaxnum. In the future, we may wish to switch those to
use M=0 instead, to match IEEE 754-2008 maxNum/minNum instead.
Commit: b0da64ea01d204f3c06d2592f4887b20439a5100
https://github.com/llvm/llvm-project/commit/b0da64ea01d204f3c06d2592f4887b20439a5100
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M .ci/monolithic-linux.sh
Log Message:
-----------
[CI] Enable LTO linker plugin tests (#184076)
We've recently had two instances of test failures for the LTO linker
plugin being introduced. Build and test the LTO linker plugin in
pre-merge CI to avoid this.
Commit: 825129378e0f1a6671de77aa8e221a4838fd8219
https://github.com/llvm/llvm-project/commit/825129378e0f1a6671de77aa8e221a4838fd8219
Author: Luke Lau <luke at igalia.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
A llvm/test/Transforms/LoopVectorize/VPlan/tail-folding.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-after-all.ll
Log Message:
-----------
[VPlan] Move tail folding out of VPlanPredicator. NFC (#176143)
Currently the logic for introducing a header mask and predicating the
vector loop region is done inside introduceMasksAndLinearize.
This splits the tail folding part out into an individual VPlan transform
so that VPlanPredicator.cpp doesn't need to worry about tail folding,
which seemed to be a temporary measure according to a comment in
VPlanTransforms.h.
To perform tail folding independently, this splits the "body" of the
vector loop region between the phis in the header and the branch + iv
increment in the latch:
Before:
```
+-------------------------------------------+
|%iv = ... |
|... |
|%iv.next = add %iv, vfxuf |
|branch-on-count %iv.next, vector-trip-count|
+-------------------------------------------+
```
After:
```
+-------------------------------------------+
|%iv = ... |
|%wide.iv = widen-canonical-iv ... |
|%header-mask = icmp ule %wide.iv, BTC |---+
|branch-on-cond %header-mask | |
+-------------------------------------------+ |
| |
v |
+-------------------------------------------+ |
|... | |
+-------------------------------------------+ |
| |
v |
+-------------------------------------------+ |
|%iv.next = add %iv, vfxuf |<--+
|branch-on-count %iv.next, vector-trip-count|
+-------------------------------------------+
```
Phis are then inserted in the latch for any value in the loop body that
have outside uses, with poison as their incoming value from the header
edge.
The motivation for this is to allow us to share the same "predicate all
successor blocks" type of predication we do for tail folding, but for
early-exit loops in #172454. This may also allow us to directly emit an
EVL based header mask, instead of having to match + transform the
existing header mask in addExplicitVectorLength.
This also allows us to eventually handle recurrences in the same
transform, avoiding the need to special case tail folding in
addReductionResultComputation.
Commit: 3b657524b69f49165377ff507f0d024633bfa37b
https://github.com/llvm/llvm-project/commit/3b657524b69f49165377ff507f0d024633bfa37b
Author: David Green <david.green at arm.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/clmul-fixed.ll
Log Message:
-----------
[AArch64] Enabled and regenerate clmul-fixed.ll. NFC (#184628)
The v2i64 tests are now fixed. The disabled ones in clmul-scalable.ll
require i128 vectors which are generally not supported.
Commit: 17e783b241acb3070edde48ae52cc5b4c1b2b03c
https://github.com/llvm/llvm-project/commit/17e783b241acb3070edde48ae52cc5b4c1b2b03c
Author: Srinivasa Ravi <srinivasar at nvidia.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
A mlir/test/Dialect/LLVMIR/nvvm-canonicalize.mlir
A mlir/test/Target/LLVMIR/nvvm/addf/addf.mlir
A mlir/test/Target/LLVMIR/nvvm/addf/addf_invalid.mlir
A mlir/test/Target/LLVMIR/nvvm/addf/addf_vector.mlir
Log Message:
-----------
[MLIR][NVVM] Add nvvm.addf and nvvm.subf Ops (#179162)
Adds `nvvm.addf` and `nvvm.subf` Ops to the NVVM dialect. `nvvm.addf`
performs a floating-point addition between two operands. `nvvm.subf`
performs a floating-point subtraction between two operands and is
equivalent to an `llvm.fneg` followed by an `nvvm.addf` operation.
PTX ISA Reference:
1.
https://docs.nvidia.com/cuda/parallel-thread-execution/#floating-point-instructions-add
2.
https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-add
Commit: 95685ca52ee89ab6df9872f1ade1bb9bfa5ce9ba
https://github.com/llvm/llvm-project/commit/95685ca52ee89ab6df9872f1ade1bb9bfa5ce9ba
Author: YongKang Zhu <yongzhu at fb.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M bolt/include/bolt/Core/BinaryContext.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/test/AArch64/compare-and-branch-inversion.S
M bolt/test/AArch64/compare-and-branch-reorder-blocks.S
A bolt/test/AArch64/retain-local-symbols.s
M bolt/test/X86/avx512-trap.test
M bolt/test/X86/dynamic-relocs-on-entry.s
Log Message:
-----------
[BOLT] Retain certain local symbols (#184074)
BOLT currently strips all STT_NOTYPE STB_LOCAL zero-sized symbols
that fall inside function bodies. Certain such symbols are named
labels (loop markers and subroutine entry points) or local function
symbols in hand-written assembly. We now keep them in local symbol
table in BOLT processed binaries for better symbolication.
Commit: 0418700f047950e71b5c94a31f2ed76f976e6090
https://github.com/llvm/llvm-project/commit/0418700f047950e71b5c94a31f2ed76f976e6090
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/test/CodeGen/AArch64/arm64-fmax-safe.ll
M llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll
M llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
M llvm/test/CodeGen/ARM/vminmaxnm-safe.ll
M llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll
M llvm/test/CodeGen/X86/sse-minmax.ll
Log Message:
-----------
[SDAGBuilder] Fix incorrect fcmp+select to minnum/maxnum transform (#184590)
minnum/maxnum don't have the correct sNaN semantics, we must convert to
minimumnum/maximumnum instead.
To avoid an NVPTX regression, make it handle fmaximmumnum in one
TableGen pattern.
This is intended as a targeted fix for the miscompile, as the complete
removal of this transform (#93575) appears to be blocked.
Fixes https://github.com/llvm/llvm-project/issues/176624.
Commit: 1f53da098f7c6a1257b8f02a139c0d26ce99aa7c
https://github.com/llvm/llvm-project/commit/1f53da098f7c6a1257b8f02a139c0d26ce99aa7c
Author: Fangrui Song <i at maskray.me>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/docs/CommandGuide/llvm-objdump.rst
M llvm/test/CodeGen/BPF/objdump_cond_op.ll
M llvm/test/CodeGen/BPF/objdump_cond_op_2.ll
M llvm/test/tools/llvm-objdump/BPF/disassemble-symbolize-operands.s
M llvm/tools/llvm-objdump/ObjdumpOpts.td
M llvm/tools/llvm-objdump/llvm-objdump.cpp
Log Message:
-----------
[llvm-objdump] Default --symbolize-operands for BPF (#184043)
BPF users expect to see basic block labels (e.g. <L0>, <L1>) in
disassembly output
(https://github.com/llvm/llvm-project/pull/95103#issuecomment-3771234810).
Default --symbolize-operands to on for BPF targets when neither
--symbolize-operands nor --no-symbolize-operands is explicitly
specified.
Add --no-symbolize-operands to allow users to opt out.
Commit: 6778c11f5cf26718c0fd057d24d416018932204b
https://github.com/llvm/llvm-project/commit/6778c11f5cf26718c0fd057d24d416018932204b
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/Analysis/CostModel/AArch64/sve-math.ll
M llvm/test/Analysis/CostModel/AArch64/sve-min-max.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-intrinsic-calls.ll
Log Message:
-----------
[AArch64] Fix SVE cost model for various math intrinsics (#184358)
The implementation of getIntrinsicInstrCost in BasicTTIImpl
assumes that for some intrinsics if we're using custom
lowering for the equivalent DAG node that the cost needs to
be 2, instead of 1 for legal ops. However, even though we
use custom lowering for these scalable vector operations
when SVE is available, we still end up generating the same
efficient codegen as fixed-width. This patch deals with a
few obvious intrinsics that we know get lowered to something
sensible and return the same cost as NEON, i.e. 1.
Commit: 9c35a7bfbc832fe357d03cc801ec25a811e52dc9
https://github.com/llvm/llvm-project/commit/9c35a7bfbc832fe357d03cc801ec25a811e52dc9
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/popcount_vmask.ll
Log Message:
-----------
[AArch64] Refine reduction VT selection in CTPOP -> VECREDUCE combine (#183025)
Use the same VT as the SETcc source, or fall back to using the VT of the
unextended operand of the CTPOP if the element size of the SETcc is too
small to fit the negative popcount.
Commit: 3cf97d8d48ccb309a5add656e7b94e27561a7dfa
https://github.com/llvm/llvm-project/commit/3cf97d8d48ccb309a5add656e7b94e27561a7dfa
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] Make ISD::ROTL/ROTR vector rotates legal on XOP+AVX512 targets (#184587)
Similar to what we did for funnel shifts on #166949 - set vector rotates
as legal on XOP (128-bit ROTL) and AVX512 (vXi32/vXi64 ROTL/ROTR)
targets, and custom fold to X86ISD::VROTLI/VROTRI as a later fixup.
128/256-bit vector widening to 512-bit instructions is already fully
supported + tested on AVX512F-only targets
First part of #184002
Commit: 8c206a26e408bcbf98b1cc6b0770b17c1e8d0320
https://github.com/llvm/llvm-project/commit/8c206a26e408bcbf98b1cc6b0770b17c1e8d0320
Author: Mariya Podchishchaeva <mariya.podchishchaeva at intel.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M clang/lib/CodeGen/CGExprCXX.cpp
A clang/test/CodeGenCXX/ms-vdtors-devirtualization.cpp
Log Message:
-----------
[win][clang] Fix devirtualization of vector deleting destructor call (#183741)
Since vector deleting destructor performs a loop over array elements and
calls delete[], simply devirtualizing call to it produces wrong code
with memory leaks.
Before emitting virtual call to vector deleting destructor, check if it
can be devirtualized, if yes, emit normal loop over array elements
instead of a virtual call.
No release note since this is a relatively recent regression.
This aims to fix https://github.com/llvm/llvm-project/issues/183621
Commit: 768182dff6ec12a91beae27fb2f5c2f20f6d4993
https://github.com/llvm/llvm-project/commit/768182dff6ec12a91beae27fb2f5c2f20f6d4993
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
Log Message:
-----------
[X86] Declare 128/256-bit funnel shifts legal on VBMI2 + NOVLX targets (#184634)
Add tablegen patterns to widen 128/256-bit funnel shift to 512-bit
Similar to what we do for 128/256-bit AVX512F rotates (and a lot of
other instructions) already - and I've take the opportunity to create
similar macros to reduce duplication in the rotate patterns
Another step towards #184002
Commit: 2e93eb71b63f25b36a991f603d7ccbb3963cb154
https://github.com/llvm/llvm-project/commit/2e93eb71b63f25b36a991f603d7ccbb3963cb154
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUFeatures.td
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
Log Message:
-----------
[AMDGPU] Use subtarget feature for flat offset bit width instead of arch checks (#183742)
Commit: c9ac1c036a45467ea3c30a14d17ce74b3c03d2f6
https://github.com/llvm/llvm-project/commit/c9ac1c036a45467ea3c30a14d17ce74b3c03d2f6
Author: Lang Hames <lhames at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/unittests/ExecutionEngine/Orc/WaitingOnGraphTest.cpp
Log Message:
-----------
[ORC] Fix typo in testcase comment. NFC.
Commit: 4a26b1f20ebb1477111064c6c686e81cf50ad7eb
https://github.com/llvm/llvm-project/commit/4a26b1f20ebb1477111064c6c686e81cf50ad7eb
Author: Zahira Ammarguellat <zahira.ammarguellat at intel.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M clang/lib/Sema/SemaOpenMP.cpp
M clang/test/OpenMP/for_non_rectangular_codegen.c
M clang/test/OpenMP/for_private_reduction_codegen.cpp
A clang/test/OpenMP/loop_collapse_codegen.cpp
Log Message:
-----------
[OpenMP] Enable collapse handling in triangular loops. (#184674)
These changes ensure that triangular loops are handled correctly when
calculating the number of iterations in OpenMP loops with `collapse`.
Commit: b6b19d140bd4f01c196ef45cb86651811f8a80ab
https://github.com/llvm/llvm-project/commit/b6b19d140bd4f01c196ef45cb86651811f8a80ab
Author: Amina Chabane <amina.chabane at arm.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/ctpop.ll
M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
M llvm/test/CodeGen/AArch64/neon-lowhalf128-optimisation.ll
M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
Log Message:
-----------
[AArch64] Fold zero-high vector inserts in MI peephole optimisation (#182835)
Summary
This patch follows on from #178227.
The previous ISel fold lowers the 64-bit case to:
```
fmov d0, x0
fmov d0, d0
```
which is not ideal and could be fmov d0, x0.
A redundant copy comes from the INSERT_SUBREG/INSvi64lane.
This peephole detects <2 x i64> vectors made of a zeroed upper and low
lane produced by FMOVXDr/FMOVDr, then removes the redundant copy.
Further updated tests and added MIR tests.
Commit: 7a624590d0d6a8f4b3b3aa4b2ee5d060e7c80a50
https://github.com/llvm/llvm-project/commit/7a624590d0d6a8f4b3b3aa4b2ee5d060e7c80a50
Author: Colin He <50345320+CPlusMinus2000 at users.noreply.github.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M mlir/lib/Dialect/Bufferization/Transforms/OneShotModuleBufferize.cpp
Log Message:
-----------
[mlir] Deterministic containers in OneShotModuleBufferize (#184722)
Iteration over funcOps in `getFuncOpsOrderedByCalls` is
non-deterministic as a result of using Dense containers. Replacing with
Vector-backed containers restores deterministic behaviour.
Commit: 774f740e0b5ff01fe8ad713300ba233f0a42262a
https://github.com/llvm/llvm-project/commit/774f740e0b5ff01fe8ad713300ba233f0a42262a
Author: Ayush Kumar Gaur <132849148+Ayush3941 at users.noreply.github.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M mlir/tools/mlir-src-sharder/CMakeLists.txt
Log Message:
-----------
[mlir] Avoid ASan ODR violation in mlir-src-sharder with LLVM dylib (#181045)
Build mlir-src-sharder via add_llvm_executable instead of add_tablegen
to avoid embedding a second copy of LLVM Support when linking against
libLLVM.so. Fixes ASan ODR violation for DisableABIBreakingChecks
Tested with ASan + LLVM dylib configuration; tool runs without abort.
Fixes #180911
Commit: e3c94d5a3640592f731d0603c7c4fbc73ff157ec
https://github.com/llvm/llvm-project/commit/e3c94d5a3640592f731d0603c7c4fbc73ff157ec
Author: Davide Grohmann <davide.grohmann at arm.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td
M mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops.mlir
M mlir/test/Target/SPIRV/tosa-ops.mlir
Log Message:
-----------
[mlir][spirv] Add last 6 Element Binary operators to TOSA Ext Inst Set (#184121)
This patch introduces the following element binary operators:
* spirv.Tosa.Maximum
* spirv.Tosa.Minimum
* spirv.Tosa.Mul
* spirv.Tosa.Pow
* spirv.Tosa.Sub
* spirv.Tosa.Table
Also dialect and serialization round-trip tests have been added.
Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
Commit: 2f90df0399b759525fcbd13283e37e2cdfb9bd4e
https://github.com/llvm/llvm-project/commit/2f90df0399b759525fcbd13283e37e2cdfb9bd4e
Author: laoshd <shandong.lao at hpe.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M flang/lib/Parser/io-parsers.cpp
A flang/test/Semantics/io17.f90
Log Message:
-----------
[Flang] Fix wrong compile-time error message, issue #178494. (#183878)
Fix the problem described in issue #178494. It will cover the failures
with S, SP, SS, BN, BZ, LZ, LZP, LZS, etc. It will resolve the test
failures in PR #183500.
Commit: fcf6bb8f3ce692c84b8cea6d55696c8576151abd
https://github.com/llvm/llvm-project/commit/fcf6bb8f3ce692c84b8cea6d55696c8576151abd
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/bitset/TestDataFormatterGenericBitset.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/coroutine_handle/TestCoroutineHandle.py
Log Message:
-----------
[lldb][test] Clean up USE_LIBSTDCPP/USE_LIBCPP usage
This patch makes the two tests consistent with the rest of the formatter API tests (and is in my opionion easier to follow).
Commit: 72e68fa73c5d09ab98d79d5f56a08a44e3ea1326
https://github.com/llvm/llvm-project/commit/72e68fa73c5d09ab98d79d5f56a08a44e3ea1326
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/optional/TestDataFormatterGenericOptional.py
Log Message:
-----------
[lldb][test] TestDataFormatterGenericOptional.py: remove obsolete skipIfs
Clang 7 and GCC 5 are pretty ancient. There's unlikely to be any bot configurations running this anymore. Lets remove it to reduce test noise.
Commit: 1bddfed92ae7de03edf4791d3e8b43c64aa921c3
https://github.com/llvm/llvm-project/commit/1bddfed92ae7de03edf4791d3e8b43c64aa921c3
Author: Tim Corringham <timothy.corringham at amd.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M clang/test/CodeGenHLSL/builtins/f16tof32-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/f16tof32.hlsl
M clang/test/CodeGenHLSL/builtins/f32tof16-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/f32tof16.hlsl
Log Message:
-----------
[HLSL] Amend f32tof16() and f16tof32() tests (#179261)
Amend the codegen tests for f32tof16() and f16tof32() to include SPIRV
as a target in addition to DXIL.
Fixes #179257
Co-authored-by: Tim Corringham <tcorring at amd.com>
Commit: 4afd0cf5534e19dc850ca6305a46f45894e23849
https://github.com/llvm/llvm-project/commit/4afd0cf5534e19dc850ca6305a46f45894e23849
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M mlir/lib/Dialect/SparseTensor/Transforms/SparseAssembler.cpp
A mlir/test/Dialect/SparseTensor/external_after_codegen.mlir
Log Message:
-----------
[mlir][sparse] Fix crash in SparseAssembler when run after SparseTensorCodegen (#183896)
After --sparse-tensor-codegen, sparse tensor arguments are replaced by
memrefs and \!sparse_tensor.storage_specifier types. The subsequent
--sparse-assembler pass calls getSparseTensorEncoding() to identify
sparse arguments to wrap/unwrap. However, getSparseTensorEncoding()
returns non-null for StorageSpecifierType as well as for sparse
RankedTensorType. Since StorageSpecifierType is not a RankedTensorType,
the subsequent cast<RankedTensorType> in convTypes() and convVals()
would crash with an assertion failure.
Fix by also checking isa<RankedTensorType>(type) in the passthrough
condition in both convTypes() and convVals(), so that
StorageSpecifierType arguments pass through unchanged.
Fixes #183776
Commit: e67360ec319a642e56abb0c3f0c3e627a98dd225
https://github.com/llvm/llvm-project/commit/e67360ec319a642e56abb0c3f0c3e627a98dd225
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
A libclc/clc/include/clc/address_space/qualifier.h
M libclc/clc/lib/amdgcn/SOURCES
A libclc/clc/lib/amdgcn/address_space/qualifier.cl
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/shared/clc_qualifier.cl
M libclc/opencl/lib/generic/SOURCES
A libclc/opencl/lib/generic/address_space/qualifier.cl
Log Message:
-----------
libclc: Implement address space qualifier functions for amdgpu (#184766)
Commit: 68c0afae262fad059bd524df9fc6d999fdb8eafd
https://github.com/llvm/llvm-project/commit/68c0afae262fad059bd524df9fc6d999fdb8eafd
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
Log Message:
-----------
AMDGPU: Add FlatSignedOffset feature and use it for flat offset printing (#183483)
Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>
Commit: e56b580d40a4fbb30a05f4d3e79ecbee731bc142
https://github.com/llvm/llvm-project/commit/e56b580d40a4fbb30a05f4d3e79ecbee731bc142
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/exec_mode3.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_NV_shader_atomic_fp16_vector/atomicrmw_faddfsub_vec_float16.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_NV_shader_atomic_fp16_vector/atomicrmw_fminfmax_vec_float16.ll
M llvm/test/CodeGen/SPIRV/pointers/fun-with-aggregate-arg-in-const-init.ll
Log Message:
-----------
Reapply "[SPIRV] Emit intrinsics for globals only in function that references them (#178143 (#179268)) (#182552)
This reverts commit 395858d9f172ff1c61c661aa7c2a18b449daffa6.
This PR had been reverted due to an unrelated address-sanitizer failure.
Commit: 001c049911e46c955aa9fc0137ca928408f9c489
https://github.com/llvm/llvm-project/commit/001c049911e46c955aa9fc0137ca928408f9c489
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/test/CodeGen/X86/known-pow2.ll
Log Message:
-----------
[X86] known-pow2.ll - add zext vector test for #182226 (#184772)
Commit: 0f59753a422d6dcbe28ab07b6f01efe131375fbe
https://github.com/llvm/llvm-project/commit/0f59753a422d6dcbe28ab07b6f01efe131375fbe
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
M mlir/test/Dialect/SparseTensor/spy_sddmm.mlir
Log Message:
-----------
[mlir][sparse] Fix crash in sparsification when unary/binary present block captures sparse tensor argument (#184597)
`relinkBranch` in Sparsification.cpp assumed that any block argument
from the outer `linalg.generic` op encountered inside an inlined
semi-ring branch must be a dense tensor, and asserted accordingly.
However, the `present` block of a `sparse_tensor.unary` (or similar
semi-ring ops) is permitted to capture sparse tensor operands directly
via `isAdmissibleBranchExp`, which accepts any `BlockArgument` as
admissible.
The fix removes the incorrect assertion and extends the load generation
to handle sparse tensors using `genSubscript`, which already knows how
to return the value buffer and current value position via the loop
emitter. The `kSparseIterator` strategy (where `genSubscript` returns a
`TensorType`) is also handled by emitting a
`sparse_tensor.extract_value` op.
Fixes #91183
Commit: 65d378d82d127915a5e58dbaaec70315b17d361e
https://github.com/llvm/llvm-project/commit/65d378d82d127915a5e58dbaaec70315b17d361e
Author: William Tran-Viet <wtranviet at proton.me>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M libcxx/docs/ReleaseNotes/23.rst
M libcxx/include/__iterator/wrap_iter.h
M libcxx/include/regex
Log Message:
-----------
[libc++] Remove `__wrap_iter::base()` (#179389)
Resolves #126442
- Converts all the relevant functions that used `.base()` into friends
- Fixed usage in `<regex>`
---------
Co-authored-by: A. Jiang <de34 at live.cn>
Commit: 9d1d80b2efcc2292a985a7cf8ad1124c2853f97e
https://github.com/llvm/llvm-project/commit/9d1d80b2efcc2292a985a7cf8ad1124c2853f97e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
Log Message:
-----------
DAG: Replace legal type check in EmitCopyFromReg (#177788)
It doesn't make sense that an illegal type would get here; a
CopyFromReg cannot be illegally typed. The only exception that
was hit here is in a handful of SystemZ inline assembly tests
for i128, which use untyped. They shouldn't; it should treat
v2i64 as legal instead. Just leave the untyped check for now.
Commit: 3ebb3ef542aa51307b12b748ad62567cbc0722cb
https://github.com/llvm/llvm-project/commit/3ebb3ef542aa51307b12b748ad62567cbc0722cb
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M mlir/lib/IR/BuiltinDialectBytecode.cpp
A mlir/test/Bytecode/invalid/invalid-dense-elem-type-interface.mlir
Log Message:
-----------
[mlir][bytecode] Fix crash when reading DenseIntOrFPElementsAttr with unsupported element type (#184773)
When a bytecode type callback substitutes a type that does not implement
DenseElementTypeInterface (e.g., \!test.i32 replacing i32), the bytecode
reader attempted to reconstruct a DenseIntOrFPElementsAttr with that
type. This unconditionally called getDenseElementBitWidth() which hit an
llvm_unreachable on unsupported types.
Fix this by validating the element type implements
DenseElementTypeInterface in readDenseIntOrFPElementsAttr before
proceeding. If the check fails, a proper diagnostic is emitted and
reading fails gracefully instead of crashing.
Fixes #128317
Commit: a631af32c01bae47ff3ddf4645df2da96984ff09
https://github.com/llvm/llvm-project/commit/a631af32c01bae47ff3ddf4645df2da96984ff09
Author: Chaitanya Koparkar <ckoparkar at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/include/llvm/CodeGen/ValueTypes.h
M llvm/include/llvm/CodeGenTypes/MachineValueType.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
Add EVT::changeVectorElementCount and MVT:changeVectorElementCount (#182266)
Fixes #174584.
Commit: a115e6bd096da9655df3541fb8161949d69cf562
https://github.com/llvm/llvm-project/commit/a115e6bd096da9655df3541fb8161949d69cf562
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M mlir/lib/Dialect/Shape/IR/Shape.cpp
M mlir/test/Dialect/Shape/canonicalize.mlir
Log Message:
-----------
[mlir][Shape] Fix crash in BroadcastOp::fold when operand is ub.poison (#183931)
BroadcastOp::fold used an unchecked llvm::cast<DenseIntElementsAttr> on
each operand's folded attribute. The existing null-check only guarded
against a missing (unset) attribute, not against a non-null attribute of
a different type such as PoisonAttr (produced when an operand is
ub.poison).
Replace the unchecked casts with dyn_cast_or_null, bailing out with
nullptr (i.e. no fold) when any operand does not provide a
DenseIntElementsAttr.
Add a regression test with a ub.poison operand.
Fixes #179679
Commit: 839dc4f7cfff5d240cc9274696efb056dd3847cd
https://github.com/llvm/llvm-project/commit/839dc4f7cfff5d240cc9274696efb056dd3847cd
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/IR/BufferDeallocationOpInterface.h
M mlir/lib/Dialect/Bufferization/IR/BufferDeallocationOpInterface.cpp
M mlir/lib/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation.cpp
M mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-branchop-interface.mlir
Log Message:
-----------
[mlir][bufferization] Fix use-after-free in ownership-based buffer deallocation (#184118)
When `handleInterface(RegionBranchOpInterface)` processes an op such as
`scf.for`, it calls `appendOpResults` to clone the op with extra
ownership result types and erase the original. The `Liveness` analysis
is computed once before the transformation begins and may still
reference the old (now-freed) result values.
If the same block contains a `BranchOpInterface` terminator (e.g.,
`cf.br`) after the structured loop, `handleInterface(BranchOpInterface)`
calls `getMemrefsToRetain`, which iterates `liveness.getLiveOut()`. That
set may contain stale `Value` objects pointing to the erased op's
results. Calling `isMemref()` on such a value dereferences freed memory,
triggering a crash.
Fix by adding a `valueMapping` map to `DeallocationState`. Before
erasing the old op in `handleInterface(RegionBranchOpInterface)`, record
the old-to-new result mapping via `state.mapValue`. The
`getLiveMemrefsIn` and `getMemrefsToRetain` helpers translate stale
liveness values through this map before calling `isMemref`, so they
always operate on live pointers.
Fixes #119863
Assisted-by: Claude Code
Commit: d316fb0797045d6f85b237aac18fabbed42e5d09
https://github.com/llvm/llvm-project/commit/d316fb0797045d6f85b237aac18fabbed42e5d09
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/fold-tail-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/gather-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/gather-do-not-vectorize-addressing.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave-allocsize-not-equal-typesize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll
M llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs-apple.ll
M llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-with-wide-ops.ll
M llvm/test/Transforms/LoopVectorize/AArch64/type-shrinkage-insertelt.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/predicated-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/VPlan/AArch64/widen-call-with-intrinsic-or-libfunc.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/X86/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/X86/fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/X86/gather-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/gather_scatter.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-ptradd-with-replicated-operand.ll
M llvm/test/Transforms/LoopVectorize/X86/interleaved-accesses-hoist-load-across-store.ll
M llvm/test/Transforms/LoopVectorize/X86/iv-live-outs.ll
M llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
M llvm/test/Transforms/LoopVectorize/X86/pr36524.ll
M llvm/test/Transforms/LoopVectorize/X86/pr51366-sunk-instruction-used-outside-of-loop.ll
M llvm/test/Transforms/LoopVectorize/X86/pr72969.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-udiv.ll
M llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
M llvm/test/Transforms/LoopVectorize/X86/uniform_mem_op.ll
M llvm/test/Transforms/LoopVectorize/X86/vplan-native-inner-loop-only.ll
M llvm/test/Transforms/LoopVectorize/X86/vplan-single-bit-ind-var-width-4.ll
M llvm/test/Transforms/LoopVectorize/X86/vplan-single-bit-ind-var.ll
M llvm/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll
M llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/cse-casts.ll
M llvm/test/Transforms/LoopVectorize/debugloc.ll
M llvm/test/Transforms/LoopVectorize/epilog-iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-any-of-reductions.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-interleave.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/float-induction.ll
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads-with-predicated-stores.ll
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads.ll
M llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
M llvm/test/Transforms/LoopVectorize/induction-multiple-uses-in-same-instruction.ll
M llvm/test/Transforms/LoopVectorize/induction-ptrcasts.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-neg-off.ll
M llvm/test/Transforms/LoopVectorize/loop-form.ll
M llvm/test/Transforms/LoopVectorize/loop-with-constant-exit-condition.ll
M llvm/test/Transforms/LoopVectorize/narrow-to-single-scalar.ll
M llvm/test/Transforms/LoopVectorize/operand-bundles.ll
M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction-index-width-smaller-than-iv-width.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-div.ll
M llvm/test/Transforms/LoopVectorize/uniform-blend.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_and.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_div_urem.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_lshr.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction2.ll
M llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll
M llvm/test/Transforms/LoopVectorize/vect-phiscev-sext-trunc.ll
M llvm/test/Transforms/LoopVectorize/version-mem-access.ll
M llvm/test/Transforms/LoopVectorize/version-stride-with-integer-casts.ll
Log Message:
-----------
[VPlan] Replicate VPScalarIVStepsRecipe by VF outside replicate regions. (#170053)
Extend replicateByVF to also handle VPScalarIVStepsRecipe. To do so, the
patch adds a new lane operand to VPScalarIVStepsRecipe, which is only
added when replicating. This enables removing a number of lane 0
computations. The lane operand will also be used to explicitly replicate
replicate regions in a follow-up.
Depends on https://github.com/llvm/llvm-project/pull/169796
Depends on https://github.com/llvm/llvm-project/pull/170906
PR: https://github.com/llvm/llvm-project/pull/170053
Commit: c7ddb30552d7281d74795f103d2b45af95fb1835
https://github.com/llvm/llvm-project/commit/c7ddb30552d7281d74795f103d2b45af95fb1835
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
Log Message:
-----------
[NVPTX] Remove `NoNaNsFPMath` uses (#183447)
Remove `NoNaNsFPMath` uses, use only `nnan`.
Commit: 0f5e9bee834adf5cef9e243103b023e20ae2b0f7
https://github.com/llvm/llvm-project/commit/0f5e9bee834adf5cef9e243103b023e20ae2b0f7
Author: Carlos Seo <carlos.seo at linaro.org>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M flang/lib/Optimizer/OpenMP/LowerWorkshare.cpp
A flang/test/Integration/OpenMP/workshare-forall-sliced-array.f90
A flang/test/Transforms/OpenMP/lower-workshare-thread-local.mlir
Log Message:
-----------
[flang][OpenMP] Fix crash when a sliced array is specified in a forall within a workshare construct (#170913)
This is a fix for two problems that caused a crash:
1. Thread-local variables sometimes are required to be parallelized.
Added a special case to handle this in
`LowerWorkshare.cpp:isSafeToParallelize`.
2. Race condition caused by a `nowait` added to the `omp.workshare` if
it is the last operation in a block. This allowed multiple threads to
execute the `omp.workshare` region concurrently. Since
_FortranAPushValue modifies a shared stack, this concurrent access
causes a crash. Disable the addition of `nowait` and rely on the
implicit barrier at the the of the `omp.workshare` region.
Fixes #143330
Commit: 209dca5fd3c1ebea7aa7b70ad48e979afc21bea9
https://github.com/llvm/llvm-project/commit/209dca5fd3c1ebea7aa7b70ad48e979afc21bea9
Author: Twice <twice at apache.org>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/WasmSSA/IR/WasmSSAOps.td
Log Message:
-----------
[MLIR][WasmSSA] Fix formatting of code blocks in WasmSSAOps.td (NFC) (#184169)
The documentation for the wasmssa dialect has some issues, such as
missing endings in some code blocks and misaligned code blocks, causing
rendering problems. This PR fixes those issues.
Commit: 1689d3c5371b53e619cdad98183680faca469f4a
https://github.com/llvm/llvm-project/commit/1689d3c5371b53e619cdad98183680faca469f4a
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/hazard-getreg-waitalu.mir
Log Message:
-----------
[AMDGPU] Test hazard-getreg-waitalu.mir on gfx13 (#183007)
Co-authored-by: Scott Egerton <9487234+ScottEgerton at users.noreply.github.com>
Commit: e3b62ffcd8592cf234174057b4581adb1eecbf9c
https://github.com/llvm/llvm-project/commit/e3b62ffcd8592cf234174057b4581adb1eecbf9c
Author: Shivam Kunwar <75530356+phyBrackets at users.noreply.github.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/Reassociate.cpp
A llvm/test/Transforms/Reassociate/reassociate-decrement-dbgvalue.ll
R llvm/test/Transforms/Reassociate/reassociate_dbgvalue_discard.ll
A llvm/test/Transforms/Reassociate/reassociate_dbgvalue_salvage.ll
Log Message:
-----------
[Reassociate][DebugInfo] Salvage debug info before rewriting expression (#182730)
When RewriteExprTree modifies instruction operands, call
`salvageDebugInfo()` before `setOperand()` so debug value expressions
are rewritten while original operands are still intact. This preserves
variable accessibility in debuggers instead of dropping values to
poison.
Fixes #60532
Fixes #61272
Commit: ee31f2d34cbee3afac4d6e598ec74113d75a462f
https://github.com/llvm/llvm-project/commit/ee31f2d34cbee3afac4d6e598ec74113d75a462f
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/FLATInstructions.td
A llvm/test/MC/AMDGPU/gfx13_asm_vflat.s
A llvm/test/MC/AMDGPU/gfx13_asm_vflat_alias.s
Log Message:
-----------
[AMDGPU] Add VFLAT, VGLOBAL, VSCRATCH to gfx13 (#182811)
Commit: 808674f7b20f7e2b6588d1f42061a154a6dcd4ed
https://github.com/llvm/llvm-project/commit/808674f7b20f7e2b6588d1f42061a154a6dcd4ed
Author: mitchell <mitchell.xu2 at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M clang-tools-extra/clang-tidy/misc/ThrowByValueCatchByReferenceCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/test/clang-tidy/checkers/misc/throw-by-value-catch-by-reference-options.cpp
Log Message:
-----------
[clang-tidy] Fix option serialization in misc-throw-by-value-catch-by-reference (#184750)
Correct the serialization of the `WarnOnLargeObject` and
`CheckThrowTemporaries` options in `storeOptions`.
Commit: c186db874b9037a77829bce4ebf89bed46efdbb8
https://github.com/llvm/llvm-project/commit/c186db874b9037a77829bce4ebf89bed46efdbb8
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenException.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/Dialect/Transforms/CXXABILowering.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRCXXABI.h
M clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerItaniumCXXABI.cpp
A clang/test/CIR/CodeGenCXX/Inputs/typeinfo
A clang/test/CIR/CodeGenCXX/typeid-cxx11.cpp
A clang/test/CIR/CodeGenCXX/typeid-should-throw.cpp
A clang/test/CIR/CodeGenCXX/typeid.cpp
Log Message:
-----------
[CIR] Implement 'typeid' operator lowering (#184449)
This patch adds typeid lowering, which uses a lot of the infrastructure
from dynamic_cast. However, this adds a `get_type_info` operation that
gets the type info out of a vtable pointer as well, which lets the
offset be handled by the ABI specific lowering code.
Commit: 03174c2b14629293da2959d44e9f82f7bc6b15b2
https://github.com/llvm/llvm-project/commit/03174c2b14629293da2959d44e9f82f7bc6b15b2
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M mlir/lib/Transforms/Utils/CFGToSCF.cpp
A mlir/test/Conversion/ControlFlowToSCF/unknown-cf-op.mlir
Log Message:
-----------
[mlir][CFGToSCF] Fix crash when encountering unknown control flow ops (#184103)
When transformToStructuredCFBranches encountered a control flow op not
handled by the CFGToSCFInterface (e.g., spirv.BranchConditional with
--lift-cf-to-scf), it correctly emitted an error and returned failure.
However, blocks had already been moved from the parent region into
temporary local Region objects before the failure was detected.
When those temporary Region objects went out of scope, their destructor
tried to destroy the contained blocks. But those blocks still had live
predecessor references from the parent region (the regionEntry's
terminator still pointed to them), causing an assertion failure:
use_empty() && "Cannot destroy a value that still has uses\!"
Fix: on failure from createStructuredBranchRegionOp, move the blocks
from the temporary conditionalRegions back into the parent region before
returning failure. This restores IR consistency and allows the Region
destructor to run safely.
Fixes #120883
Fixes #118454
Assisted-by: Claude Code
Commit: 743e4df2e24f77278aeb65a1776984b4b8fb247a
https://github.com/llvm/llvm-project/commit/743e4df2e24f77278aeb65a1776984b4b8fb247a
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/test/CIR/CodeGen/ternary.cpp
Log Message:
-----------
[CIR] Fix void ternary operators- (#184691)
I discovered this while working on something else, but we were doing a
'getTerminator' on a block that we didn't know whether it had a
terminator, and MLIR causes an assert in this case. This patch
re-factors the code to better check whether it might have a terminator
(to assuage the assert in mlir::Block), and get the correct value out.
The fixup later in the ternary setup correctly gets the 'void' yields
correct, so everything else gets fixed eventually.
Commit: 5634484b32df726270224814315253c8eb17fb62
https://github.com/llvm/llvm-project/commit/5634484b32df726270224814315253c8eb17fb62
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M libc/src/__support/GPU/allocator.cpp
Log Message:
-----------
[libc] Hoist GPU allocator loop invariants from find_slab (#184803)
Summary:
This improves performance as these variables were not eligible for LICM
apparently.
Commit: 5f1683ca1a4a582a73eabd79cad46a5294b35c33
https://github.com/llvm/llvm-project/commit/5f1683ca1a4a582a73eabd79cad46a5294b35c33
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M clang/lib/CodeGen/CGDebugInfo.cpp
R clang/test/DebugInfo/CXX/debug-info-constexpr-array.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
R llvm/test/DebugInfo/X86/debug-info-constexpr-array.ll
Log Message:
-----------
Revert "[DebugInfo] Emit DW_AT_const_value for constexpr array static members" (#184798)
Reverts llvm/llvm-project#182442.
The change does not handle endianness correctly.
Commit: 8ef122433149b10be71f01b9c5fafc8e269b1a63
https://github.com/llvm/llvm-project/commit/8ef122433149b10be71f01b9c5fafc8e269b1a63
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/hip-options.hip
A clang/test/Driver/linker-wrapper-canonical-prefixes.c
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td
Log Message:
-----------
[LinkerWrapper] Add support for --no-canonical-prefixes
This is necessary to support build environments where the
compiler/associated tools are actually just symlinks into a CAS. Without
this, we try and resolve binaries relative to the real path of
clang-linker-wrapper, which is usually in a directory prefixed with the
first couple characters of a SHA digest and named with a SHA digest. We
also need to ensure that we propagate --no-canonical-prefixes to sub
clang invocations so that clang is able to resolve lld in such
environments.
Reviewers: jhuber6, Artem-B, sarnex
Pull Request: https://github.com/llvm/llvm-project/pull/184160
Commit: 73e2988dd02ca470f81601fb0e6e2db88a23a3df
https://github.com/llvm/llvm-project/commit/73e2988dd02ca470f81601fb0e6e2db88a23a3df
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/include/llvm/CodeGen/ValueTypes.h
Log Message:
-----------
[CodeGen] Simplify EVT::operator!=. NFCI. (#184792)
This is based on the assumption that LLVMTy should be nullptr if and
only if the EVT is simple.
Commit: 02e9b08d0286a2aac18dadd9bfff34ba9d7bf869
https://github.com/llvm/llvm-project/commit/02e9b08d0286a2aac18dadd9bfff34ba9d7bf869
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M lldb/include/lldb/Target/Platform.h
M lldb/include/lldb/Utility/UnimplementedError.h
Log Message:
-----------
[lldb] Use UnimplementedError for GetSDKFromDebugInfo (#184199)
We can now differentiate unimplemented errors from actual errors that
may be useful to users.
Commit: c88ba88da52b963692ab30e75821b69dad2c1bbd
https://github.com/llvm/llvm-project/commit/c88ba88da52b963692ab30e75821b69dad2c1bbd
Author: Dmitrii Makarenko <dmitrii.makarenko at intel.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/include/llvm/ADT/ArrayRef.h
M llvm/unittests/ADT/ArrayRefTest.cpp
Log Message:
-----------
[ADT] Refine MutableArrayRef forwarding constructor constraints (#183806)
Keep MutableArrayRef on a single C&& constructor, with SFINAE on direct
check on `C::data()`. This keeps const std::span<int> supported and
rejects const vector/smallvector sources for MutableArrayRef<int>.
Commit: 1dc91cd6205f9e72be729dfdba7647b4ceaf8abd
https://github.com/llvm/llvm-project/commit/1dc91cd6205f9e72be729dfdba7647b4ceaf8abd
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/Target/X86/X86InstrSSE.td
M llvm/test/MC/Disassembler/X86/x86-64-avx.txt
M llvm/test/MC/X86/SSE42-32.s
M llvm/test/MC/X86/SSE42-64.s
M llvm/test/MC/X86/avx-32-att.s
M llvm/test/MC/X86/avx-64-att.s
M llvm/test/TableGen/x86-fold-tables.inc
M llvm/test/TableGen/x86-instr-mapping.inc
Log Message:
-----------
[X86] Add (v)pcmpestr(m/i)q to set the W bit. (#184746)
These instructions don't ignore the W bit as we had previously marked.
Also support (v)pcmpestr(m/i)l as an alias for the W0 form to match
binutils.
Fixes part of #183635
Commit: 18f228810eb2bcb5ea2620396624b5b1f4d4a7af
https://github.com/llvm/llvm-project/commit/18f228810eb2bcb5ea2620396624b5b1f4d4a7af
Author: agozillon <Andrew.Gozillon at amd.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
A flang/test/Lower/OpenMP/allocatable-dtype-intermediate-map-gen.f90
Log Message:
-----------
[Flang][OpenMP] Skip intermediate map generation for motion modifier map directives (#177737)
Currently if we create the following map:
!$omp target update from/to(derived_type%allocatable)
We'll generate an extra map for the derived type (and any other
allocatable maps that may be in-between the final mapped allocatable
member). However, for cases like this, and other motion modifier related
map directives we don't need to do so. All the user cares about is the
specified member. Removing the intermediate member will minimize extra
performance overhead. It also maintains correctness, as currently, the
MLIR diagnostics for the motion modifiers restricts possible map types
for updates to to and from, and applying this map type to an
intermediate map will result in unintended side affects, e.g. mapping
back data the user didn't want to or over-writing data they didn't
intend to on device. This minor modification addresses that.
Commit: 88b62b03c671b476ff1389fcd4288a695684a122
https://github.com/llvm/llvm-project/commit/88b62b03c671b476ff1389fcd4288a695684a122
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M clang-tools-extra/include-cleaner/lib/CMakeLists.txt
Log Message:
-----------
[ClangIncludeCleaner] Disable PCH (#184809)
Workaround a Clang bug w.r.t. instantiation of inline functions.
See: https://github.com/llvm/llvm-project/issues/184559.
Commit: 38a8bccdce3b7298761a22618ae406ff55a745df
https://github.com/llvm/llvm-project/commit/38a8bccdce3b7298761a22618ae406ff55a745df
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M flang/test/Lower/Intrinsics/bessel_yn.f90
M flang/test/Lower/Intrinsics/bge.f90
M flang/test/Lower/Intrinsics/bgt.f90
M flang/test/Lower/Intrinsics/ble.f90
M flang/test/Lower/Intrinsics/blt.f90
Log Message:
-----------
[flang][NFC] Converted five tests from old lowering to new lowering (part 25) (#184720)
Tests converted from test/Lower/Intrinsics: bessel_yn.f90, bge.f90,
bgt.f90, ble.f90, blt.f90
Commit: e9657a12b2e85bec018633df7604b6328e717ec7
https://github.com/llvm/llvm-project/commit/e9657a12b2e85bec018633df7604b6328e717ec7
Author: Will <will at mon.im>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M lld/test/COFF/base.test
M lld/test/COFF/heap.test
M lld/test/COFF/stack.test
M llvm/lib/Object/COFFModuleDefinition.cpp
Log Message:
-----------
COFF: Allow hex literals in .def files: BASE/HEAPSIZE/STACKSIZE (#184764)
For a Win32 DLL, a .def file can have a custom executable base:
```
LIBRARY "stub.dll" BASE=0x10000000
```
Currently the parser enforces Base 10, but [Microsoft's
documentation](https://learn.microsoft.com/en-us/cpp/build/reference/rules-for-module-definition-statements?view=msvc-170)
states "Numeric arguments are specified in base 10 or hexadecimal".
This fixes that, and also HEAPSIZE and STACKSIZE (which use the same
function).
There are a few more instances of `getAsInteger` that expect base10 -
for ordinals and the VERSION directive. Since I don't have an
in-the-wild example of a .def file using hexadecimal for these, I am
wary about changing those too.
Commit: 2580ddfe4e198b148f7e8a6931d29a6fbcc9a234
https://github.com/llvm/llvm-project/commit/2580ddfe4e198b148f7e8a6931d29a6fbcc9a234
Author: Daniel Chen <cdchen at ca.ibm.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M flang/CMakeLists.txt
Log Message:
-----------
[flang] Fix distribution build of `ISO_Fortran_binding.h` to also install it in `CMAKE_INSTALL_INCLUDEDIR`. (#184284)
Currently with `-DLLVM_DISTRIBUTION_COMPONENTS="flang-fortran-binding"`,
header file `ISO_Fortran_binding.h` is only installed at
`./lib/clang/23/include/ISO_Fortran_binding.h`, but not in the user
include.
This PR is to fix that so that the `ISO_Fortran_binding.h` is also
installed at `./include/flang/ISO_Fortran_binding.h`, which is the same
as the "normal" (non-distribution) build.
Commit: 5c3d0dd7a482b38e5a68f462d7ea874f55bc67f6
https://github.com/llvm/llvm-project/commit/5c3d0dd7a482b38e5a68f462d7ea874f55bc67f6
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/test/Dialect/MemRef/canonicalize.mlir
Log Message:
-----------
[mlir][memref] Fix crash in DimOp::fold for subview with ambiguous dropped dims (#183995)
When a rank-reducing subview has multiple size-1 source dimensions and
all strides are dynamic, `computeMemRefRankReductionMask` cannot
unambiguously determine which dimension is dropped. It would fall back
to an arbitrary choice that could be wrong.
In `DimOp::fold`, the code then maps a result dimension to that
(possibly incorrect) source dimension and asserts
`isDynamicSize(sourceIndex)`. If `getDroppedDims()` picked the wrong
dropped dim, the source dim at `sourceIndex` may be statically sized,
causing the assertion to fire.
Fix this by replacing the assert with a guard that returns `{}` (no
fold) when the resolved source dimension is not dynamic. This is safe
because the fold already handles the statically-sized result case
earlier.
Fixes #111244
Assisted-by: Claude Code
Commit: efb6f542c389755b22fe45a797fe9ea658292a05
https://github.com/llvm/llvm-project/commit/efb6f542c389755b22fe45a797fe9ea658292a05
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
Log Message:
-----------
[RISCV] Don't make ISD::ABDS/ABDU legal for v2i32 with P extension. (#184753)
We don't have the instructions for this so it causes a cannot select
error.
Commit: 3925d112c44413f858bcb50c00125e039cef170e
https://github.com/llvm/llvm-project/commit/3925d112c44413f858bcb50c00125e039cef170e
Author: Dmitry Chigarev <dmitry.chigarev at intel.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
M mlir/test/Conversion/VectorToXeGPU/transfer-read-to-xegpu.mlir
Log Message:
-----------
[MLIR][XeGPU] Decompose unsupported 'vector.transfer_read'-transpose-permutations (#182875)
The PR adds a pattern to `vector-to-xegpu` pass that decomposes
`vector.transfer_read` with unsupported transpose-permutations
(unsupported element-type) into `vector.transfer_read +
vector.transpose`:
Example:
```mlir
// input-ir:
%0 = vector.transfer_read %source[%offset, %offset], %c0
{permutation_map = affine_map<(d0, d1) -> (d1, d0)>,
in_bounds = [true, true]} : memref<32x64xf16>, vector<8x16xf16>
// mlir-opt %s --convert-vector-to-xegpu
// before PR (no conversion because of unsupported type):
%0 = vector.transfer_read %source[%offset, %offset], %c0
{permutation_map = affine_map<(d0, d1) -> (d1, d0)>,
in_bounds = [true, true]} : memref<32x64xf16>, vector<8x16xf16>
// mlir-opt %s --convert-vector-to-xegpu
// after PR (decomposed + converted):
%0 = xegpu.load_nd %source[%offset, %offset]
%1 = vector.transpose %0
```
---------
Signed-off-by: dchigarev <dmitry.chigarev at intel.com>
Commit: a9fb8b06224aec404a2ec9bf101c40e36f46426c
https://github.com/llvm/llvm-project/commit/a9fb8b06224aec404a2ec9bf101c40e36f46426c
Author: Dmitry Chigarev <dmitry.chigarev at intel.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
M mlir/test/Conversion/VectorToXeGPU/contract-to-xegpu.mlir
Log Message:
-----------
[MLIR][XeGPU] Support vector.contract transpose_a/transpose_b via 'vector-to-gpu' patterns (#182885)
The PR adds [`vector.contract(transpose_a/transpose_b)` decomposition
patterns](https://github.com/llvm/llvm-project/blob/3215645b8d81bbef7db1d16b88de7ed0288f2274/mlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp#L1263)
from `vector-to-gpu` to `vector-to-xegpu` pass.
The `populatePrepareVectorToMMAPatterns` adds two patterns:
1. `PrepareContractToGPUMMA` that splits `vector.contract(transpose)`
into `vector.transpose + vector.contract`
2. `CombineTransferReadOpTranspose` that fuses `vector.transpose` into
the permutation map of `vector.transfer_read`
The second pattern doesn't always bring us to the desired result
(`xegpu.load_nd + vector.transpose + xegpu.dpas`) since [not all data
types are supported
](https://github.com/llvm/llvm-project/blob/1237bd6df05a4777f444677186e4814388916ea9/mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp#L570-L575)
for the transposed-read case. There's a second PR (#182875) on this
matter that adds a decomposition-pattern for unsupported types (it might
seem strange that we first fuse and then decompose
transfer_read+transpose but this way we don't have code duplication
between vector-to-gpu&to-xegpu passes and cover all functional cases)
---------
Signed-off-by: dchigarev <dmitry.chigarev at intel.com>
Commit: 6b3f57de0af21788f27f6172b8dff933a0bfdf91
https://github.com/llvm/llvm-project/commit/6b3f57de0af21788f27f6172b8dff933a0bfdf91
Author: John Harrison <harjohn at google.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M lldb/test/API/python_api/block/TestFrameBlocks.py
Log Message:
-----------
[lldb] Skip SBBlock test on Windows. (#184818)
Skipping this test to unblock CI.
Commit: f14a8aa8887dc3e2ca7537551ea59ce6db5fd5b0
https://github.com/llvm/llvm-project/commit/f14a8aa8887dc3e2ca7537551ea59ce6db5fd5b0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
A llvm/test/CodeGen/X86/bit-manip-i256.ll
A llvm/test/CodeGen/X86/bit-manip-i512.ll
Log Message:
-----------
[X86] add i256/i512 bit manipulation tests suggested by #132601 (#184813)
Commit: 97572c1860efeeb97b5940927cee72081b61810a
https://github.com/llvm/llvm-project/commit/97572c1860efeeb97b5940927cee72081b61810a
Author: jimingham <jingham at apple.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M lldb/include/lldb/Host/ProcessRunLock.h
M lldb/include/lldb/Target/Process.h
M lldb/source/Target/Process.cpp
M lldb/source/Target/StopInfo.cpp
M lldb/test/API/python_api/run_locker/TestRunLocker.py
Log Message:
-----------
Add the ability to "allow another thread to see the private state" mode. (#184272)
When lldb stops to run a breakpoint condition or other callback that has
to happen between the private stop and returning control to the user, it
will run in the state where the public state is still "running". But if
the callback needs to run lldb commands or python code, it needs to see
the correct "stop" state.
We used to handle that by switching the public state to stopped before
running the callbacks. However, that opened a window where we are still
handling the stop event and another thread would be allowed to continue
the target or do other actions that can interfere with that orderly
process.
This patch adds the ability to designate a particular thread as "seeing
the private state" while all other threads see the "public state". Then
when we run a breakpoint callback, no threads but the one that is
actually running the callback will see the state change until the event
has been delivered to the primary state listener.
It also adds a test that while a long-running breakpoint callback runs,
another thread continues to see the state as running.
Commit: 21a1b4c1d748dc5e9742bfae2b35c4d9fc9e0b19
https://github.com/llvm/llvm-project/commit/21a1b4c1d748dc5e9742bfae2b35c4d9fc9e0b19
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/include/llvm/Transforms/Utils/UnrollLoop.h
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/Transforms/Scalar/LoopUnrollAndJamPass.cpp
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
Log Message:
-----------
[LoopUnroll] Remove `UseUpperBound` output parameter from `computeUnrollCount` (NFC) (#184526)
`UseUpperBound` is only ever read by `UnrollAndJamPass.cpp`'s
`computeUnrollAndJamCount()`. However, `computeUnrollAndJamCount()` also
sets `MaxTripCount` to `0` which
[disables](https://github.com/llvm/llvm-project/blob/928505c98345e0494f2d260788adb291efc9ee38/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp#L1017)
the only case that could set `UseUpperBound`.
Since there are no callers that need the result of `UseUpperBound`,
remove it.
Commit: f0265ccb60746e3c34254bb2e06ca62bd51b6ba2
https://github.com/llvm/llvm-project/commit/f0265ccb60746e3c34254bb2e06ca62bd51b6ba2
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
A llvm/test/Transforms/LoopUnroll/full-and-enable.ll
Log Message:
-----------
[LoopUnroll] Ensure we can accept both `llvm.loop.unroll.full` and `llvm.loop.unroll.enable` metadata on the same loop (NFC) (#182381)
Ensure that frontends can request both `PragmaEnable` and `PragmaFull`
semantics on a loop.
FYI: to the best of my knowledge, it's not possible to toggle both
`PragmaEnable` and `PragmaFull` via `clang`.
Commit: 43fc0f32c04cdc14f0608fddf8bbc235923d987b
https://github.com/llvm/llvm-project/commit/43fc0f32c04cdc14f0608fddf8bbc235923d987b
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/shll1-add-sub-combined.ll
Log Message:
-----------
[SLP][NFC]Add a case with a missing matching between shl/add/sub, NFC
Commit: 4c5ff239ea40145ab860e299f89c2718e39b5ee9
https://github.com/llvm/llvm-project/commit/4c5ff239ea40145ab860e299f89c2718e39b5ee9
Author: Chi-Chun, Chen <chichun.chen at hpe.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Semantics/OpenMP/depend01.f90
M flang/test/Semantics/OpenMP/reduction05.f90
Log Message:
-----------
[Flang][OpenMP] Avoid division-by-zero when checking array section stride (#184726)
Commit: 6d003f5033b324aa0319cd3ee8912bde80a915d6
https://github.com/llvm/llvm-project/commit/6d003f5033b324aa0319cd3ee8912bde80a915d6
Author: Jonathan Thackray <jonathan.thackray at arm.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsAArch64.def
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/Headers/arm_acle.h
M clang/lib/Sema/SemaARM.cpp
A clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
M clang/test/CodeGen/arm_acle.c
M clang/test/CodeGen/builtins-arm64.c
A clang/test/Sema/AArch64/pcdphint-atomic-store.c
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
A llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
M llvm/test/Verifier/AArch64/intrinsic-immarg.ll
Log Message:
-----------
[AArch64][clang][llvm] Add ACLE `stshh` atomic store builtin (#181386)
Add `__arm_atomic_store_with_stshh` implementation as defined in the
ACLE. Validate arguments passed are correct, and lower to the `stshh`
intrinsic plus an atomic store using a pseudo-instruction with the
allowed orderings:
* memory orderings: relaxed, release, seq_cst
* retention policies: keep, strm
The `STSHH` instruction (Store with Store Hint for Hardware) is part
of the `FEAT_PCDPHINT` extension.
Commit: 673d725c3bcf5b551e42ff96d00b77b8f3b9adcb
https://github.com/llvm/llvm-project/commit/673d725c3bcf5b551e42ff96d00b77b8f3b9adcb
Author: Nishant Sachdeva <32475507+nishant-sachdeva at users.noreply.github.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/test/tools/llvm-ir2vec/bindings/ir2vec-bindings.py
M llvm/tools/llvm-ir2vec/Bindings/PyIR2Vec.cpp
M llvm/tools/llvm-ir2vec/lib/Utils.cpp
M llvm/tools/llvm-ir2vec/lib/Utils.h
Log Message:
-----------
Reland "[llvm-ir2vec] Adding Inst Embeddings Map API to ir2vec python bindings (#180140)" (#184196)
Relanding change from https://github.com/llvm/llvm-project/pull/180140
- Returns a Inst Embedding Map based on the input function name
`getInstEmbMap(funcName) -> Map<Inst string, Embedding>`
- Refactors IR2VecTool methods to have a separate call to create the
embedder object
Commit: e5e709adeec3c5c063fc756d077a9b53dc469eb2
https://github.com/llvm/llvm-project/commit/e5e709adeec3c5c063fc756d077a9b53dc469eb2
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M mlir/lib/Conversion/VectorToXeGPU/CMakeLists.txt
Log Message:
-----------
Fix build break with BUILD_SHARED_LIBS=ON
/usr/bin/ld: tools/mlir/lib/Conversion/VectorToXeGPU/CMakeFiles/obj.MLIR
VectorToXeGPU.dir/VectorToXeGPU.cpp.o: in function `(anonymous namespace
)::ConvertVectorToXeGPUPass::runOnOperation()':
VectorToXeGPU.cpp:(.text._ZN12_GLOBAL__N_124ConvertVectorToXeGPUPass14ru
nOnOperationEv+0xbc): undefined reference to `mlir::populatePrepareVecto
rToMMAPatterns(mlir::RewritePatternSet&, bool)'
clang++: error: linker command failed with exit code 1 (use -v to see in
vocation)
Commit: 56cdd60a2f94d715c188ce17507796996d880f0d
https://github.com/llvm/llvm-project/commit/56cdd60a2f94d715c188ce17507796996d880f0d
Author: Fangrui Song <i at maskray.me>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/include/llvm/MC/MCAsmBackend.h
M llvm/lib/MC/MCAsmBackend.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h
M llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp
Log Message:
-----------
[MC] Merge fixupNeedsRelaxation and fixupNeedsRelaxationAdvanced. NFC (#184832)
The two-tier relaxation hook design (fixupNeedsRelaxationAdvanced
delegating to fixupNeedsRelaxation) is confusing and unnecessary.
Only M68k and AMDGPU used fixupNeedsRelaxation (via the default
fixupNeedsRelaxationAdvanced). AArch64 and CSKY had dead overrides:
they don't override mayNeedRelaxation to ever return true.
Merge the two hooks: convert M68k and AMDGPU to override
fixupNeedsRelaxationAdvanced directly, remove dead overrides from
AArch64 and CSKY, and simplify the default implementation to
`return !Resolved`.
Commit: 30060dc681f70a2e9071d380f01312d097a98c0c
https://github.com/llvm/llvm-project/commit/30060dc681f70a2e9071d380f01312d097a98c0c
Author: Lily Gorsheneva <bgorshenev at google.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Update Bazel build files for a9fb8b0 (#184823)
Deps for
https://github.com/llvm/llvm-project/commit/a9fb8b06224aec404a2ec9bf101c40e36f46426c
Commit: 14d586a46df3460be775676982e4ef478554e3c4
https://github.com/llvm/llvm-project/commit/14d586a46df3460be775676982e4ef478554e3c4
Author: Peter Rong <peterrong96 at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
A llvm/test/CodeGen/AArch64/Issue57251.ll
Log Message:
-----------
[SelectionDAG] Fix cycle in ReplacedValues during type legalization (#184697)
During type legalization, `ReplaceValueWith` handles morphed nodes by
computing `OldValId` and `NewValId`, calling `ReplaceAllUsesOfValueWith`
(RAUW), then adding `ReplacedValues[OldValId] = NewValId`.
However, the RAUW call can trigger `CSE`, which fires NoteDeletion
callbacks that add new entries to `ReplacedValues`. If NoteDeletion adds
`ReplacedValues[A] = B`, and the subsequent assignment adds
`ReplacedValues[B] = A`, a cycle is created. RemapId then recurses
infinitely following the cycle during path compression, causing a stack
overflow crash.
On AArch64, i16 is not a legal type and requires promotion to i32. When
IR uses i16 values as `extractelement` indices that feed into other
`extractelement` operations, the interplay between result promotion and
operand promotion creates the specific CSE pattern that produces the
cycle.
Fix by calling RemapId on both OldValId and NewValId after the RAUW call
to account for new ReplacedValues entries added during the RAUW cascade.
In the reproducer, this causes both ids to resolve to the same value,
skipping the assignment and preventing the cycle.
Fixes https://github.com/llvm/llvm-project/issues/57251
[Assisted-by](https://t.ly/Dkjjk): [Claude Opus
4.6](https://www.anthropic.com/news/claude-opus-4-6)
Commit: f8f0f93236b2aee6b63a454c05cc2876568f8972
https://github.com/llvm/llvm-project/commit/f8f0f93236b2aee6b63a454c05cc2876568f8972
Author: Deric C. <cheung.deric at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M clang/include/clang/AST/APValue.h
M clang/include/clang/AST/PropertiesBase.td
M clang/include/clang/AST/TypeBase.h
M clang/lib/AST/APValue.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/MicrosoftMangle.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/AST/Type.cpp
M clang/lib/CodeGen/CGExprConstant.cpp
M clang/lib/Sema/SemaTemplate.cpp
A clang/test/AST/HLSL/ast-dump-APValue-matrix.hlsl
M clang/test/CodeGenHLSL/BoolMatrix.hlsl
A clang/test/SemaHLSL/Types/BuiltinMatrix/MatrixConstantExpr.hlsl
Log Message:
-----------
[HLSL][Matrix] Add APValue and ConstExpr evaluator support for matrices (#178762)
Fixes #168935
This PR adds basic support for matrix APValues and a ConstExpr evaluator
for matrices.
- ConstExpr evaluation changes:
- Matrix initializer list
- Matrix HLSL elementwise cast
- Matrix HLSL aggregate splat
- Vector HLSL matrix truncation
- Int HLSL matrix truncation
- Float HLSL matrix truncation
- Matrix APValue:
- AST dumper and serialization
- Value flattening
Note that APValue matrices hold its elements in row-major order
irrespective of the `-fmatrix-memory-layout` flag.
The `-fmatrix-memory-layout` is for codegen, not semantics, so the
decision of which memory layout to use for the matrix APValue can be
independent of the memory layout for codegen.
There are also a number of places expecting switch case coverage over
all APValues but which do not currently support matrix APValues. I have
added placeholder llvm_unreachables to these places for the matrix
APValue, as these places can not currently be exercised in clang tests
(AFAIK).
Assisted-by: claude-opus-4.5
Commit: c5c6588c115347cdd000cb8a650b19dca0381196
https://github.com/llvm/llvm-project/commit/c5c6588c115347cdd000cb8a650b19dca0381196
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToWiDistributeExperimental.cpp
M mlir/test/Dialect/XeGPU/sg-to-wi-experimental-unit.mlir
Log Message:
-----------
[MLIR][XeGPU] Add distribution pattern for xegpu load & store matrix from sg to wi (#183179)
This PR adds distribution pattern for xegpu.load_matrix &
xegpu.store_matrix ops for the new sg-to-wi pass
Commit: 42d07c38e22768360a66548407a28332340efb20
https://github.com/llvm/llvm-project/commit/42d07c38e22768360a66548407a28332340efb20
Author: Chi-Chun, Chen <chichun.chen at hpe.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
A flang/test/Semantics/OpenMP/affinity-invalid.f90
Log Message:
-----------
[Flang][OpenMP] Reject substring and invalid use of array section in affinity (#184424)
Add semantic checks for OpenMP AFFINITY clauses to reject substring and
invalid use of array section
Commit: 894408ded44151e4e34a3402210f671355d66310
https://github.com/llvm/llvm-project/commit/894408ded44151e4e34a3402210f671355d66310
Author: Jim Ingham <jingham at apple.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M lldb/test/API/python_api/run_locker/TestRunLocker.py
Log Message:
-----------
Skip some tests on Windows. They were already expected fail and
I needed to use "sleep" so now the test file won't compile. So
switching to skip...
Commit: ce47e259bcd40abab7890a4651d4ddce775dee15
https://github.com/llvm/llvm-project/commit/ce47e259bcd40abab7890a4651d4ddce775dee15
Author: Amr Hesham <amr96 at programmer.net>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
A clang/test/CIR/CodeGen/openmp_default_simd_align.c
Log Message:
-----------
[CIR] Implement OpenMPRequiredSimdAlign UnaryExpr (#184214)
Implement the OpenMPRequiredSimdAlign kind of UnaryExprOrTypeTraitExpr
Commit: c54bc306c38b695e6e713002ef9608c36c63ce9a
https://github.com/llvm/llvm-project/commit/c54bc306c38b695e6e713002ef9608c36c63ce9a
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
Log Message:
-----------
[NFC][SPIRV] Remove `MachineInstr` from `DeadMIs` set after erasing it (#184795)
Commit: 5b064a2c168c2f8a08e86c4540c0adb838db030a
https://github.com/llvm/llvm-project/commit/5b064a2c168c2f8a08e86c4540c0adb838db030a
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M clang/include/clang/DependencyScanning/DependencyScannerImpl.h
M clang/include/clang/DependencyScanning/DependencyScanningWorker.h
M clang/include/clang/Tooling/DependencyScanningTool.h
M clang/lib/DependencyScanning/DependencyScannerImpl.cpp
M clang/lib/DependencyScanning/DependencyScanningWorker.cpp
M clang/lib/Tooling/DependencyScanningTool.cpp
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
Log Message:
-----------
[clang][deps] Simplify by-module-name scan API (#184376)
The by-module-name scanning APIs are fairly spread out. There's the main
`CompilerInstanceWithContext` class that provides a constructor,
`initialize()` and `computeDependencies()`. Then there's the
`DependencyScanningWorker` that optionally owns
`CompilerInstanceWithContext` and re-exposes two `initialize()` and one
`computeDependencies()` functions. Lastly, there's
`DependencyScanningTool` that again re-exposes two variants of
`initialize()` and one `computeDependencies()`.
The current setup makes it unnecessarily difficult to make changes to
these APIs (as observed in
https://github.com/swiftlang/llvm-project/pull/12453).
This PR makes `CompilerInstanceWithContext` standalone, and hides the
construct + initialize pattern behind a static factory function. This
makes it harder to misuse the API (forgetting to call `initialize()`,
calling it twice, etc.) and means changes now need to only touch single
class instead of three classes spread over multiple files.
Commit: 10ade366508d3fac4a769e3ca93e657edf491e94
https://github.com/llvm/llvm-project/commit/10ade366508d3fac4a769e3ca93e657edf491e94
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M libc/src/__support/GPU/CMakeLists.txt
M libc/src/__support/GPU/allocator.cpp
A libc/src/__support/GPU/fixedbuffer.h
R libc/src/__support/GPU/fixedstack.h
M libc/test/integration/src/__support/GPU/CMakeLists.txt
A libc/test/integration/src/__support/GPU/fixedbuffer_test.cpp
R libc/test/integration/src/__support/GPU/fixedstack_test.cpp
Log Message:
-----------
[libc] Rework slab cache data structure for GPU allocator
Summary:
This was previously a Trieber stack, which is a perfectly fine generic
and lock-free data structure. However, this used some expensive CAS
operations and had issues with ABA. Because the only user of this was
the slab cache mechanism, we can pretty safely specialize it. Instead,
we simply search a fixed size buffer for some sentinal values and CAS
into it.
For allocations that only ever hit the cache, this improves performance
from ~9000 cycles to ~6000 cycles and similar improvements for workloads
that feel the pain of small thread counts hitting the cache.
Commit: 454863b4404ce1470a40a93bb6442c3fe6628bc7
https://github.com/llvm/llvm-project/commit/454863b4404ce1470a40a93bb6442c3fe6628bc7
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M clang/lib/Headers/gpuintrin.h
Log Message:
-----------
[Clang] Fix 'gpuintrin.h' implementation of 'match_all'
Summary:
This implementation only worked if the lane mask passed in was uniform,
but this is against the expected usage where the user may be wishing to
check if a value is uniform *within* a mask subset. Also remove
redundant sync_lanes, the ballots and shuffles already have
synchronizing behavior.
Commit: b0091732025bc1173feebeb078fb0296c9d2ef86
https://github.com/llvm/llvm-project/commit/b0091732025bc1173feebeb078fb0296c9d2ef86
Author: Deric C. <cheung.deric at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Program.cpp
M clang/test/SemaHLSL/Types/BuiltinMatrix/MatrixConstantExpr.hlsl
Log Message:
-----------
[clang][bytecode][HLSL][Matrix] Support `ConstantMatrixType` and more HLSL casts in the new constant interpreter for basic matrix constexpr evaluation in HLSL (#184840)
Forgot to change the target branch before merging. This PR is a
cherry-pick of the squashed-and-merged PR commit
b16aa4b7ec665911c74300cd7442659b70973d13 from 183424
This PR fixes #182963
This PR is an extension of #178762 which has already been merged.
This PR adds support for `ConstantMatrixType` and the HLSL casts
`CK_HLSLArrayRValue`, `CK_HLSLMatrixTruncation`,
`CK_HLSLAggregateSplatCast`, and `CK_HLSLElementwiseCast` to the
bytecode constexpr evaluator.
The implementations of CK_HLSLAggregateSplatCast and
CK_HLSLElementwiseCast are incomplete, as they still need to support
struct and array types to enable use of the experimental new constant
interpreter on other existing HLSL constexpr tests. The completion of
the implementations of these casts will be tracked in a separate issue
(#183426) and implemented in a separate PR.
Assisted-by: claude-opus-4.6
Commit: cdea74824c776571ba0716e9c925ece7b014a9c8
https://github.com/llvm/llvm-project/commit/cdea74824c776571ba0716e9c925ece7b014a9c8
Author: Justice Adams <jadams23 at apple.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M .ci/green-dragon/clang-stage1-RA.groovy
Log Message:
-----------
[green dragon] skip trigger on release branch stage1 RA jobs (#184653)
* This will allow us to setup clang-stage1-RA jobs as multi branch
pipelines for release branches without setting up all the downstream
jobs.
I will need to cherry-pick the jenkinsfile to the release/22.x branch
which I will do after this lands
Commit: ea65e8593e21b055dfb1f5f74ea7a5618a6fa275
https://github.com/llvm/llvm-project/commit/ea65e8593e21b055dfb1f5f74ea7a5618a6fa275
Author: Sadaf Ebrahimi <sadafebrahimi at google.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M compiler-rt/lib/scudo/standalone/common.h
M compiler-rt/lib/scudo/standalone/fuchsia.cpp
M compiler-rt/lib/scudo/standalone/linux.cpp
M compiler-rt/lib/scudo/standalone/mem_map.cpp
M compiler-rt/lib/scudo/standalone/mem_map.h
M compiler-rt/lib/scudo/standalone/mem_map_base.h
M compiler-rt/lib/scudo/standalone/mem_map_fuchsia.cpp
M compiler-rt/lib/scudo/standalone/mem_map_fuchsia.h
M compiler-rt/lib/scudo/standalone/mem_map_linux.cpp
M compiler-rt/lib/scudo/standalone/mem_map_linux.h
M compiler-rt/lib/scudo/standalone/primary64.h
M compiler-rt/lib/scudo/standalone/secondary.h
M compiler-rt/lib/scudo/standalone/tests/common_test.cpp
M compiler-rt/lib/scudo/standalone/tests/map_test.cpp
M compiler-rt/lib/scudo/standalone/trusty.cpp
Log Message:
-----------
[scudo] Move getResidentPages function (#183138)
Moving getResidentPages out of linux.cpp and adding it to MemMapBase
Commit: 64d618785aa457d8fc70ae66407973ab7afa27a2
https://github.com/llvm/llvm-project/commit/64d618785aa457d8fc70ae66407973ab7afa27a2
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
Log Message:
-----------
[SPIRV] Replace `removeFromParent` with `eraseFromParent` for `ASSING_TYPE` (#184793)
The `ASSIGN_TYPE` instruction should not be referenced anymore at this
point. So we can free its memory.
Follow up of https://github.com/llvm/llvm-project/pull/182330
Commit: 1ef472f8360dbfa3b31dac085f1c02e1487bc7d2
https://github.com/llvm/llvm-project/commit/1ef472f8360dbfa3b31dac085f1c02e1487bc7d2
Author: Leandro Lupori <leandro.lupori at linaro.org>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/test/Lower/OpenMP/composite_simd_linear.f90
M flang/test/Lower/OpenMP/distribute-parallel-do-simd.f90
M flang/test/Lower/OpenMP/distribute-simd.f90
M flang/test/Lower/OpenMP/loop-pointer-variable.f90
M flang/test/Lower/OpenMP/ordered-simd.f90
M flang/test/Lower/OpenMP/wsloop-simd.f90
Log Message:
-----------
Revert "[flang][OpenMP] Fix lowering of LINEAR iteration variables" (#184843)
Reverts llvm/llvm-project#183794
It broke a couple of tests from Fujitsu testsuite.
Commit: 6807b61f4acbbe79daa00c9854de5d4a1e50e0cd
https://github.com/llvm/llvm-project/commit/6807b61f4acbbe79daa00c9854de5d4a1e50e0cd
Author: Jim Ingham <jingham at apple.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M lldb/test/API/commands/watchpoints/watchpoint_commands/command/watchpoint_command.py
Log Message:
-----------
Fix a bug in the watchpoint callback - in one case we weren't
returning anything from the callback. Fixing this on the off
chance that is what is causing the linux-only failure in this test
after PR:
https://github.com/llvm/llvm-project/pull/184272
Commit: b989713cd2980037c90dfba4bcf233c984284085
https://github.com/llvm/llvm-project/commit/b989713cd2980037c90dfba4bcf233c984284085
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M lldb/source/Host/windows/PseudoConsole.cpp
Log Message:
-----------
[lldb][windows] remove sleep before closing ConPTY (#183539)
Commit: 6811a83c81500ee373adfc0d9978ff9625a4cf1c
https://github.com/llvm/llvm-project/commit/6811a83c81500ee373adfc0d9978ff9625a4cf1c
Author: Chinmay Deshpande <chdeshpa at amd.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/AST/ASTContext.cpp
M clang/lib/CodeGen/ModuleBuilder.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
A clang/test/CodeGenCXX/dllexport-inherited-ctor.cpp
M clang/test/SemaCXX/dllexport.cpp
Log Message:
-----------
[Clang] Ensure child classes export inherited constructors from base classes (#182706)
Inherited constructors in `dllexport` classes are now exported for ABI-compatible cases,
matching MSVC behavior. Constructors with variadic arguments or callee-cleanup
parameters are not yet supported and produce a warning.
This aims to partially resolve https://github.com/llvm/llvm-project/issues/162640.
Assisted by : Cursor // Claude Opus 4.6
Commit: b7ed29df5dd53b96fbef359fdfdba5ba75867516
https://github.com/llvm/llvm-project/commit/b7ed29df5dd53b96fbef359fdfdba5ba75867516
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/expected-prof-consecutive-access.ll
Log Message:
-----------
[SLP][NFC]Add a test with a loop with profiling info, NFC
Commit: f7560e1795799fe30d595a348cb34f103077a81b
https://github.com/llvm/llvm-project/commit/f7560e1795799fe30d595a348cb34f103077a81b
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/multiple-argmin-argmax.ll
Log Message:
-----------
[LV] Add tests with loops with multiple argmin/argmax.
Add additional tests with multiple argmin/argmax reductions for
https://github.com/llvm/llvm-project/issues/184729.
Commit: 3ed12eb3ff5abf563fc0aa7f5f2d1c892eadd05a
https://github.com/llvm/llvm-project/commit/3ed12eb3ff5abf563fc0aa7f5f2d1c892eadd05a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
Log Message:
-----------
[RISCV][P-ext] Fix cannot select error for shlsat with i8 vector argument. (#184839)
We don't have instructions for an i8 sshlat.
Commit: 0bca18db8d67f9b622117546f441611688a1e5ae
https://github.com/llvm/llvm-project/commit/0bca18db8d67f9b622117546f441611688a1e5ae
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
Log Message:
-----------
[CIR][NFC] Add 'matrix' type to CIRGenExprConstant.cpp switch (#184852)
This just adds this as an NYI, but this will suppress the Wswitch
warning.
Commit: 9145a7484eb7ba42fbb5fc773800a591a3fe5914
https://github.com/llvm/llvm-project/commit/9145a7484eb7ba42fbb5fc773800a591a3fe5914
Author: Dave Lee <davelee.com at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M lldb/examples/python/formatter_bytecode.py
Log Message:
-----------
[lldb] Use "assemble" instead of "compile" in formatter_bytecode.py (#184714)
Replace "compile" with "assemble" in formatter_bytecode. This is in
preparation for the addition of a Python to formatter bytecode compiler.
It will be more clear to have one meaning for "compile".
Commit: 0a76568db07ec7f5469aa189e10283980e609ef6
https://github.com/llvm/llvm-project/commit/0a76568db07ec7f5469aa189e10283980e609ef6
Author: Demetrius Kanios <demetrius at kanios.net>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
A llvm/test/CodeGen/WebAssembly/pr184441.ll
Log Message:
-----------
[WebAssembly] Reapply "[WebAssembly] Incorporate SCCs into WebAssemblyFixIrreducibleControlFlow" (#181755) (#184441)
Re-application of #181755.
Includes fixes to issues found after the original's merge.
Commit: 7187a1d9d2ea2746616ab6ad97649d39f0e410f0
https://github.com/llvm/llvm-project/commit/7187a1d9d2ea2746616ab6ad97649d39f0e410f0
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M flang/include/flang/Parser/openmp-utils.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Parser/openmp-utils.cpp
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/resolve-directives.cpp
Log Message:
-----------
[flang][OpenMP] Utilities to get uppercase directive/clause names (#184853)
It is a convention to use uppercase names of directives and clauses in
diagnostic messages, but getting such names is somewhat cumbersome:
```
parser::ToUpperCaseLetters(llvm::omp::getOpenMPDirectiveName(dirId));
parser::ToUpperCaseLetters(llvm::omp::getOpenMPClauseName(clauseId));
```
Implement `GetUpperName` (overloaded for clauses and directives) to
shorten it to
```
GetUpperName(dirId, version);
GetUpperName(clauseId, version);
```
This patch replaces existing instances of this pattern, adding the use
of OpenMP version where it was previously missing.
Commit: eb6fb77731b31b536b415bbf486172310ccaf4c9
https://github.com/llvm/llvm-project/commit/eb6fb77731b31b536b415bbf486172310ccaf4c9
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M clang/lib/Tooling/DependencyScanningTool.cpp
Log Message:
-----------
[clang][deps] Move-construct optional to fix a bot (#184861)
This is a speculative fix for the openmp-offload-sles-build-only build
bot that fails after #184376 with:
```
clang/lib/Tooling/DependencyScanningTool.cpp:336:12: error: could not convert ‘CIWithContext’ from ‘clang::tooling::CompilerInstanceWithContext’ to ‘std::optional<clang::tooling::CompilerInstanceWithContext>’
return CIWithContext;
^~~~~~~~~~~~~
```
Commit: e4ad8a6e38f8f4c7704cfefb1891deb13a8ba64b
https://github.com/llvm/llvm-project/commit/e4ad8a6e38f8f4c7704cfefb1891deb13a8ba64b
Author: Deric C. <cheung.deric at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M clang/lib/Sema/SemaChecking.cpp
M clang/test/SemaHLSL/MatrixElementOverloadResolution.hlsl
A clang/test/SemaHLSL/Types/BuiltinMatrix/MatrixFloatPrecisionWarnings.hlsl
Log Message:
-----------
[HLSL][Matrix] Add implicit matrix floating-point conversion checks (#179568)
Fixes #168944
Depends on #178762 being merged first.
The commit adds implicit conversion warnings for HLSL matrix types in
Clang's semantic checker by extending SemaChecking.cpp to detect
precision loss when converting between matrix types (specifically,
ConstantMatrixType).
A new test validates float precision warnings, and an existing test was
updated to expect the new diagnostics.
Assisted-by: claude-opus-4.5
Commit: a8af467fad7e5fff71643a3d6f2d06ac4f637e66
https://github.com/llvm/llvm-project/commit/a8af467fad7e5fff71643a3d6f2d06ac4f637e66
Author: Jim Ingham <jingham at apple.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M lldb/include/lldb/Target/Process.h
Log Message:
-----------
When hijacking events, don't let the user thread that was allowed
to see the private state to do so until we are done hijacking.
Commit: 520319e3e0d2c22fd462a72583f88977bb882ca3
https://github.com/llvm/llvm-project/commit/520319e3e0d2c22fd462a72583f88977bb882ca3
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/CUDA/CUFDeviceGlobal.cpp
M flang/test/Fir/CUDA/cuda-device-global.f90
Log Message:
-----------
[flang][cuda] Copy type descriptor used in fir.alloca op (#184859)
Avoid error like:
```
error: runtime derived type info descriptor was not generated
```
Commit: 5e88b806e8281d0a329f36768ec157e17ce30f76
https://github.com/llvm/llvm-project/commit/5e88b806e8281d0a329f36768ec157e17ce30f76
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Use pragma pack(1) for VPIRFlags on AIX. (#184687)
Some compilers (e.g. on AIX) do not pack by default. Use LLVM_PACKED to
ensure the VPIRFlags struct is packed as expected on all platforms.
This matches what we already do in other places for AIX, e.g. in
llvm/include/llvm/CodeGen/SelectionDAGNodes.h (added in
844a02e509a4cc03f76ef5dd1c358c57ee164b71), although it uses the more
general LLVM_PACKED unconditionally
PR: https://github.com/llvm/llvm-project/pull/184687
Commit: 90fdad2001b756b8c6fdef5262cb76a67fc6420c
https://github.com/llvm/llvm-project/commit/90fdad2001b756b8c6fdef5262cb76a67fc6420c
Author: Michael Spencer <bigcheesegs at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M clang-tools-extra/modularize/ModularizeUtilities.cpp
M clang/docs/Modules.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/include/clang/Lex/HeaderSearch.h
M clang/include/clang/Lex/ModuleMap.h
M clang/include/clang/Lex/ModuleMapFile.h
M clang/lib/Frontend/FrontendAction.cpp
M clang/lib/Lex/HeaderSearch.cpp
M clang/lib/Lex/ModuleMap.cpp
M clang/lib/Lex/ModuleMapFile.cpp
A clang/test/Modules/deprecated-upwards-relative-path.m
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
Log Message:
-----------
[clang][modules] Add warning for module maps with ".." paths (#184279)
Implicitly discovered module maps that reference files outside their
module directory cause order dependent behavior when using implicitly
discovered module maps. This adds an off by default diagnostic about
these cases with the long term goal of removing import order dependent
behavior.
Module maps found via `-fmodule-map-file=` are not a problem because
they are all loaded at the start of translation.
Assisted-by: claude-opus-4.6
Commit: 5d2560c1a9fe5e824e23aeec77ba309a02b9bf38
https://github.com/llvm/llvm-project/commit/5d2560c1a9fe5e824e23aeec77ba309a02b9bf38
Author: Jim Ingham <jingham at apple.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M lldb/include/lldb/Target/Process.h
Log Message:
-----------
Revert "When hijacking events, don't let the user thread that was allowed"
This reverts commit a8af467fad7e5fff71643a3d6f2d06ac4f637e66.
This was a follow-on to 97572c1860efeeb97b5940927cee72081b61810a which was me
trying to guess why the ubuntu bots were failing with an entirely unhelpful
failure mode. I'll have to figure out how I can reproduce this somewhere so
I can look at it for real.
Commit: c969b5fe76d97ac269578816f7d21f536ac5e159
https://github.com/llvm/llvm-project/commit/c969b5fe76d97ac269578816f7d21f536ac5e159
Author: Jim Ingham <jingham at apple.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M lldb/test/API/python_api/run_locker/TestRunLocker.py
Log Message:
-----------
Revert "Skip some tests on Windows. They were already expected fail and"
This reverts commit 894408ded44151e4e34a3402210f671355d66310.
These tests were added by 97572c1860efeeb97b5940927cee72081b61810a
and I am reverting that as well.
Commit: ecd6f8c22bc477369d229b95b90820d87ebcdac7
https://github.com/llvm/llvm-project/commit/ecd6f8c22bc477369d229b95b90820d87ebcdac7
Author: Jim Ingham <jingham at apple.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M lldb/include/lldb/Host/ProcessRunLock.h
M lldb/include/lldb/Target/Process.h
M lldb/source/Target/Process.cpp
M lldb/source/Target/StopInfo.cpp
M lldb/test/API/python_api/run_locker/TestRunLocker.py
Log Message:
-----------
Revert "Add the ability to "allow another thread to see the private state" mode. (#184272)"
This reverts commit 97572c1860efeeb97b5940927cee72081b61810a.
This patch seems to cause TestWatchpointCommandPython.py to time out
on the ubuntu buildbots (but nowhere else that I can find so far.) The
timeout is weird too, the TEST FILE is timing out but the individual
tests aren't being shown and there's no other output. Grrr...
Anyway I'll revert this and then see if I can do some guessing about
how this change might cause the test to fail.
Commit: cc2c0f929f986fc1c05f8186a6ff174c39033a4b
https://github.com/llvm/llvm-project/commit/cc2c0f929f986fc1c05f8186a6ff174c39033a4b
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M .ci/green-dragon/clang-stage1-RA.groovy
M .ci/monolithic-linux.sh
M bolt/include/bolt/Core/BinaryContext.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/test/AArch64/compare-and-branch-inversion.S
M bolt/test/AArch64/compare-and-branch-reorder-blocks.S
A bolt/test/AArch64/retain-local-symbols.s
M bolt/test/X86/avx512-trap.test
M bolt/test/X86/dynamic-relocs-on-entry.s
M clang-tools-extra/clang-tidy/misc/ThrowByValueCatchByReferenceCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/include-cleaner/lib/CMakeLists.txt
M clang-tools-extra/modularize/ModularizeUtilities.cpp
A clang-tools-extra/test/clang-tidy/checkers/misc/throw-by-value-catch-by-reference-options.cpp
M clang/docs/Modules.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/APValue.h
M clang/include/clang/AST/PropertiesBase.td
M clang/include/clang/AST/TypeBase.h
M clang/include/clang/Basic/BuiltinsAArch64.def
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/DependencyScanning/DependencyScannerImpl.h
M clang/include/clang/DependencyScanning/DependencyScanningWorker.h
M clang/include/clang/Lex/HeaderSearch.h
M clang/include/clang/Lex/ModuleMap.h
M clang/include/clang/Lex/ModuleMapFile.h
M clang/include/clang/Tooling/DependencyScanningTool.h
M clang/lib/AST/APValue.cpp
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Program.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/MicrosoftMangle.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/AST/Type.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenException.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/Transforms/CXXABILowering.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRCXXABI.h
M clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerItaniumCXXABI.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGExprCXX.cpp
M clang/lib/CodeGen/CGExprConstant.cpp
M clang/lib/CodeGen/ModuleBuilder.cpp
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/DependencyScanning/DependencyScannerImpl.cpp
M clang/lib/DependencyScanning/DependencyScanningWorker.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Frontend/FrontendAction.cpp
M clang/lib/Headers/arm_acle.h
M clang/lib/Headers/gpuintrin.h
M clang/lib/Lex/HeaderSearch.cpp
M clang/lib/Lex/ModuleMap.cpp
M clang/lib/Lex/ModuleMapFile.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Tooling/DependencyScanningTool.cpp
A clang/test/AST/HLSL/ast-dump-APValue-matrix.hlsl
A clang/test/CIR/CodeGen/openmp_default_simd_align.c
M clang/test/CIR/CodeGen/ternary.cpp
A clang/test/CIR/CodeGenCXX/Inputs/typeinfo
A clang/test/CIR/CodeGenCXX/typeid-cxx11.cpp
A clang/test/CIR/CodeGenCXX/typeid-should-throw.cpp
A clang/test/CIR/CodeGenCXX/typeid.cpp
A clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
M clang/test/CodeGen/arm_acle.c
M clang/test/CodeGen/builtins-arm64.c
A clang/test/CodeGenCXX/dllexport-inherited-ctor.cpp
A clang/test/CodeGenCXX/ms-vdtors-devirtualization.cpp
M clang/test/CodeGenHLSL/BoolMatrix.hlsl
M clang/test/CodeGenHLSL/builtins/f16tof32-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/f16tof32.hlsl
M clang/test/CodeGenHLSL/builtins/f32tof16-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/f32tof16.hlsl
R clang/test/DebugInfo/CXX/debug-info-constexpr-array.cpp
M clang/test/Driver/hip-options.hip
A clang/test/Driver/linker-wrapper-canonical-prefixes.c
A clang/test/Modules/deprecated-upwards-relative-path.m
M clang/test/OpenMP/for_non_rectangular_codegen.c
M clang/test/OpenMP/for_private_reduction_codegen.cpp
A clang/test/OpenMP/loop_collapse_codegen.cpp
A clang/test/Sema/AArch64/pcdphint-atomic-store.c
M clang/test/SemaCXX/dllexport.cpp
M clang/test/SemaHLSL/MatrixElementOverloadResolution.hlsl
A clang/test/SemaHLSL/Types/BuiltinMatrix/MatrixConstantExpr.hlsl
A clang/test/SemaHLSL/Types/BuiltinMatrix/MatrixFloatPrecisionWarnings.hlsl
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M compiler-rt/lib/scudo/standalone/common.h
M compiler-rt/lib/scudo/standalone/fuchsia.cpp
M compiler-rt/lib/scudo/standalone/linux.cpp
M compiler-rt/lib/scudo/standalone/mem_map.cpp
M compiler-rt/lib/scudo/standalone/mem_map.h
M compiler-rt/lib/scudo/standalone/mem_map_base.h
M compiler-rt/lib/scudo/standalone/mem_map_fuchsia.cpp
M compiler-rt/lib/scudo/standalone/mem_map_fuchsia.h
M compiler-rt/lib/scudo/standalone/mem_map_linux.cpp
M compiler-rt/lib/scudo/standalone/mem_map_linux.h
M compiler-rt/lib/scudo/standalone/primary64.h
M compiler-rt/lib/scudo/standalone/secondary.h
M compiler-rt/lib/scudo/standalone/tests/common_test.cpp
M compiler-rt/lib/scudo/standalone/tests/map_test.cpp
M compiler-rt/lib/scudo/standalone/trusty.cpp
M flang/CMakeLists.txt
M flang/include/flang/Parser/openmp-utils.h
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/OpenMP/LowerWorkshare.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFDeviceGlobal.cpp
M flang/lib/Parser/io-parsers.cpp
M flang/lib/Parser/openmp-utils.cpp
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Fir/CUDA/cuda-device-global.f90
A flang/test/Integration/OpenMP/workshare-forall-sliced-array.f90
M flang/test/Lower/Intrinsics/bessel_yn.f90
M flang/test/Lower/Intrinsics/bge.f90
M flang/test/Lower/Intrinsics/bgt.f90
M flang/test/Lower/Intrinsics/ble.f90
M flang/test/Lower/Intrinsics/blt.f90
A flang/test/Lower/OpenMP/allocatable-dtype-intermediate-map-gen.f90
M flang/test/Lower/OpenMP/composite_simd_linear.f90
M flang/test/Lower/OpenMP/distribute-parallel-do-simd.f90
M flang/test/Lower/OpenMP/distribute-simd.f90
M flang/test/Lower/OpenMP/loop-pointer-variable.f90
M flang/test/Lower/OpenMP/ordered-simd.f90
M flang/test/Lower/OpenMP/wsloop-simd.f90
A flang/test/Semantics/OpenMP/affinity-invalid.f90
M flang/test/Semantics/OpenMP/depend01.f90
M flang/test/Semantics/OpenMP/reduction05.f90
A flang/test/Semantics/io17.f90
A flang/test/Transforms/OpenMP/lower-workshare-thread-local.mlir
M libc/src/__support/GPU/CMakeLists.txt
M libc/src/__support/GPU/allocator.cpp
A libc/src/__support/GPU/fixedbuffer.h
R libc/src/__support/GPU/fixedstack.h
M libc/test/integration/src/__support/GPU/CMakeLists.txt
A libc/test/integration/src/__support/GPU/fixedbuffer_test.cpp
R libc/test/integration/src/__support/GPU/fixedstack_test.cpp
M libclc/CMakeLists.txt
A libclc/clc/include/clc/address_space/qualifier.h
M libclc/clc/lib/amdgcn/SOURCES
A libclc/clc/lib/amdgcn/address_space/qualifier.cl
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/shared/clc_qualifier.cl
M libclc/opencl/lib/generic/SOURCES
A libclc/opencl/lib/generic/address_space/qualifier.cl
M libcxx/docs/ReleaseNotes/23.rst
M libcxx/include/__iterator/wrap_iter.h
M libcxx/include/regex
A libcxx/test/libcxx/strings/basic.string/string.cons/constexpr_initialization_stress.pass.cpp
R libcxx/test/std/strings/basic.string/string.cons/constexpr_initialization_stress.pass.cpp
M lld/test/COFF/base.test
M lld/test/COFF/heap.test
M lld/test/COFF/stack.test
M lldb/examples/python/formatter_bytecode.py
M lldb/include/lldb/Target/Platform.h
M lldb/include/lldb/Utility/UnimplementedError.h
M lldb/source/Host/windows/PseudoConsole.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
M lldb/test/API/commands/watchpoints/watchpoint_commands/command/watchpoint_command.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/bitset/TestDataFormatterGenericBitset.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/coroutine_handle/TestCoroutineHandle.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/optional/TestDataFormatterGenericOptional.py
M lldb/test/API/python_api/block/TestFrameBlocks.py
M llvm/docs/CommandGuide/llvm-objdump.rst
M llvm/include/llvm/ADT/ArrayRef.h
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/include/llvm/CodeGen/ValueTypes.h
M llvm/include/llvm/CodeGenTypes/MachineValueType.h
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/MC/MCAsmBackend.h
M llvm/include/llvm/Transforms/Utils/UnrollLoop.h
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/MCAsmBackend.cpp
M llvm/lib/Object/COFFModuleDefinition.cpp
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUFeatures.td
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h
M llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZInstrVector.td
M llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrSSE.td
M llvm/lib/Transforms/Scalar/LoopUnrollAndJamPass.cpp
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/lib/Transforms/Scalar/Reassociate.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/Analysis/CostModel/AArch64/sve-math.ll
M llvm/test/Analysis/CostModel/AArch64/sve-min-max.ll
A llvm/test/CodeGen/AArch64/Issue57251.ll
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/arm64-fmax-safe.ll
M llvm/test/CodeGen/AArch64/clmul-fixed.ll
M llvm/test/CodeGen/AArch64/ctpop.ll
M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
M llvm/test/CodeGen/AArch64/neon-lowhalf128-optimisation.ll
A llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
M llvm/test/CodeGen/AArch64/popcount_vmask.ll
M llvm/test/CodeGen/AMDGPU/hazard-getreg-waitalu.mir
M llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll
M llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
M llvm/test/CodeGen/ARM/vminmaxnm-safe.ll
M llvm/test/CodeGen/BPF/objdump_cond_op.ll
M llvm/test/CodeGen/BPF/objdump_cond_op_2.ll
M llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/exec_mode3.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_NV_shader_atomic_fp16_vector/atomicrmw_faddfsub_vec_float16.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_NV_shader_atomic_fp16_vector/atomicrmw_fminfmax_vec_float16.ll
M llvm/test/CodeGen/SPIRV/pointers/fun-with-aggregate-arg-in-const-init.ll
A llvm/test/CodeGen/SystemZ/fminimumnum-fmaximumnum.ll
A llvm/test/CodeGen/WebAssembly/pr184441.ll
M llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll
A llvm/test/CodeGen/X86/bit-manip-i256.ll
A llvm/test/CodeGen/X86/bit-manip-i512.ll
M llvm/test/CodeGen/X86/known-pow2.ll
M llvm/test/CodeGen/X86/sse-minmax.ll
R llvm/test/DebugInfo/X86/debug-info-constexpr-array.ll
A llvm/test/MC/AMDGPU/gfx13_asm_vflat.s
A llvm/test/MC/AMDGPU/gfx13_asm_vflat_alias.s
M llvm/test/MC/Disassembler/X86/x86-64-avx.txt
M llvm/test/MC/X86/SSE42-32.s
M llvm/test/MC/X86/SSE42-64.s
M llvm/test/MC/X86/avx-32-att.s
M llvm/test/MC/X86/avx-64-att.s
M llvm/test/TableGen/x86-fold-tables.inc
M llvm/test/TableGen/x86-instr-mapping.inc
A llvm/test/Transforms/LoopUnroll/full-and-enable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fold-tail-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/gather-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/gather-do-not-vectorize-addressing.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave-allocsize-not-equal-typesize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll
M llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs-apple.ll
M llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-with-wide-ops.ll
M llvm/test/Transforms/LoopVectorize/AArch64/type-shrinkage-insertelt.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-intrinsic-calls.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/predicated-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/VPlan/AArch64/widen-call-with-intrinsic-or-libfunc.ll
A llvm/test/Transforms/LoopVectorize/VPlan/tail-folding.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-after-all.ll
M llvm/test/Transforms/LoopVectorize/X86/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/X86/fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/X86/gather-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/gather_scatter.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-ptradd-with-replicated-operand.ll
M llvm/test/Transforms/LoopVectorize/X86/interleaved-accesses-hoist-load-across-store.ll
M llvm/test/Transforms/LoopVectorize/X86/iv-live-outs.ll
M llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
M llvm/test/Transforms/LoopVectorize/X86/pr36524.ll
M llvm/test/Transforms/LoopVectorize/X86/pr51366-sunk-instruction-used-outside-of-loop.ll
M llvm/test/Transforms/LoopVectorize/X86/pr72969.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-udiv.ll
M llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
M llvm/test/Transforms/LoopVectorize/X86/uniform_mem_op.ll
M llvm/test/Transforms/LoopVectorize/X86/vplan-native-inner-loop-only.ll
M llvm/test/Transforms/LoopVectorize/X86/vplan-single-bit-ind-var-width-4.ll
M llvm/test/Transforms/LoopVectorize/X86/vplan-single-bit-ind-var.ll
M llvm/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll
M llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/cse-casts.ll
M llvm/test/Transforms/LoopVectorize/debugloc.ll
M llvm/test/Transforms/LoopVectorize/epilog-iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-any-of-reductions.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-interleave.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/float-induction.ll
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads-with-predicated-stores.ll
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads.ll
M llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
M llvm/test/Transforms/LoopVectorize/induction-multiple-uses-in-same-instruction.ll
M llvm/test/Transforms/LoopVectorize/induction-ptrcasts.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-neg-off.ll
M llvm/test/Transforms/LoopVectorize/loop-form.ll
M llvm/test/Transforms/LoopVectorize/loop-with-constant-exit-condition.ll
A llvm/test/Transforms/LoopVectorize/multiple-argmin-argmax.ll
M llvm/test/Transforms/LoopVectorize/narrow-to-single-scalar.ll
M llvm/test/Transforms/LoopVectorize/operand-bundles.ll
M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction-index-width-smaller-than-iv-width.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-div.ll
M llvm/test/Transforms/LoopVectorize/uniform-blend.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_and.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_div_urem.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_lshr.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction2.ll
M llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll
M llvm/test/Transforms/LoopVectorize/vect-phiscev-sext-trunc.ll
M llvm/test/Transforms/LoopVectorize/version-mem-access.ll
M llvm/test/Transforms/LoopVectorize/version-stride-with-integer-casts.ll
A llvm/test/Transforms/Reassociate/reassociate-decrement-dbgvalue.ll
R llvm/test/Transforms/Reassociate/reassociate_dbgvalue_discard.ll
A llvm/test/Transforms/Reassociate/reassociate_dbgvalue_salvage.ll
A llvm/test/Transforms/SLPVectorizer/X86/expected-prof-consecutive-access.ll
A llvm/test/Transforms/SLPVectorizer/X86/shll1-add-sub-combined.ll
M llvm/test/Verifier/AArch64/intrinsic-immarg.ll
M llvm/test/tools/llvm-ir2vec/bindings/ir2vec-bindings.py
M llvm/test/tools/llvm-objdump/BPF/disassemble-symbolize-operands.s
M llvm/tools/llvm-ir2vec/Bindings/PyIR2Vec.cpp
M llvm/tools/llvm-ir2vec/lib/Utils.cpp
M llvm/tools/llvm-ir2vec/lib/Utils.h
M llvm/tools/llvm-objdump/ObjdumpOpts.td
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/unittests/ADT/ArrayRefTest.cpp
M llvm/unittests/ExecutionEngine/Orc/WaitingOnGraphTest.cpp
M mlir/include/mlir/Dialect/Bufferization/IR/BufferDeallocationOpInterface.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td
M mlir/include/mlir/Dialect/WasmSSA/IR/WasmSSAOps.td
M mlir/lib/Conversion/VectorToXeGPU/CMakeLists.txt
M mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferDeallocationOpInterface.cpp
M mlir/lib/Dialect/Bufferization/Transforms/OneShotModuleBufferize.cpp
M mlir/lib/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/Shape/IR/Shape.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseAssembler.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToWiDistributeExperimental.cpp
M mlir/lib/IR/BuiltinDialectBytecode.cpp
M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
M mlir/lib/Transforms/Utils/CFGToSCF.cpp
A mlir/test/Bytecode/invalid/invalid-dense-elem-type-interface.mlir
A mlir/test/Conversion/ControlFlowToSCF/unknown-cf-op.mlir
M mlir/test/Conversion/VectorToXeGPU/contract-to-xegpu.mlir
M mlir/test/Conversion/VectorToXeGPU/transfer-read-to-xegpu.mlir
M mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-branchop-interface.mlir
A mlir/test/Dialect/LLVMIR/nvvm-canonicalize.mlir
M mlir/test/Dialect/MemRef/canonicalize.mlir
M mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops.mlir
M mlir/test/Dialect/Shape/canonicalize.mlir
A mlir/test/Dialect/SparseTensor/external_after_codegen.mlir
M mlir/test/Dialect/SparseTensor/spy_sddmm.mlir
M mlir/test/Dialect/XeGPU/sg-to-wi-experimental-unit.mlir
A mlir/test/Target/LLVMIR/nvvm/addf/addf.mlir
A mlir/test/Target/LLVMIR/nvvm/addf/addf_invalid.mlir
A mlir/test/Target/LLVMIR/nvvm/addf/addf_vector.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-block-scale-shared.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-block-scale-tensor.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-invalid.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-sp-block-scale-shared.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-sp-block-scale-tensor.mlir
M mlir/test/Target/SPIRV/tosa-ops.mlir
M mlir/tools/mlir-src-sharder/CMakeLists.txt
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.7
[skip ci]
Commit: 08f6fedf6f08be18ff4c64ef5d09ed68f526e891
https://github.com/llvm/llvm-project/commit/08f6fedf6f08be18ff4c64ef5d09ed68f526e891
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M .ci/green-dragon/clang-stage1-RA.groovy
M .ci/monolithic-linux.sh
M bolt/include/bolt/Core/BinaryContext.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/test/AArch64/compare-and-branch-inversion.S
M bolt/test/AArch64/compare-and-branch-reorder-blocks.S
A bolt/test/AArch64/retain-local-symbols.s
M bolt/test/X86/avx512-trap.test
M bolt/test/X86/dynamic-relocs-on-entry.s
M clang-tools-extra/clang-tidy/misc/ThrowByValueCatchByReferenceCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/include-cleaner/lib/CMakeLists.txt
M clang-tools-extra/modularize/ModularizeUtilities.cpp
A clang-tools-extra/test/clang-tidy/checkers/misc/throw-by-value-catch-by-reference-options.cpp
M clang/docs/Modules.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/APValue.h
M clang/include/clang/AST/PropertiesBase.td
M clang/include/clang/AST/TypeBase.h
M clang/include/clang/Basic/BuiltinsAArch64.def
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/DependencyScanning/DependencyScannerImpl.h
M clang/include/clang/DependencyScanning/DependencyScanningWorker.h
M clang/include/clang/Lex/HeaderSearch.h
M clang/include/clang/Lex/ModuleMap.h
M clang/include/clang/Lex/ModuleMapFile.h
M clang/include/clang/Tooling/DependencyScanningTool.h
M clang/lib/AST/APValue.cpp
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Compiler.h
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Program.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/MicrosoftMangle.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/AST/Type.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenException.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/Transforms/CXXABILowering.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRCXXABI.h
M clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerItaniumCXXABI.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGExprCXX.cpp
M clang/lib/CodeGen/CGExprConstant.cpp
M clang/lib/CodeGen/ModuleBuilder.cpp
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/DependencyScanning/DependencyScannerImpl.cpp
M clang/lib/DependencyScanning/DependencyScanningWorker.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Frontend/FrontendAction.cpp
M clang/lib/Headers/arm_acle.h
M clang/lib/Headers/gpuintrin.h
M clang/lib/Lex/HeaderSearch.cpp
M clang/lib/Lex/ModuleMap.cpp
M clang/lib/Lex/ModuleMapFile.cpp
M clang/lib/Sema/SemaARM.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Tooling/DependencyScanningTool.cpp
A clang/test/AST/HLSL/ast-dump-APValue-matrix.hlsl
A clang/test/CIR/CodeGen/openmp_default_simd_align.c
M clang/test/CIR/CodeGen/ternary.cpp
A clang/test/CIR/CodeGenCXX/Inputs/typeinfo
A clang/test/CIR/CodeGenCXX/typeid-cxx11.cpp
A clang/test/CIR/CodeGenCXX/typeid-should-throw.cpp
A clang/test/CIR/CodeGenCXX/typeid.cpp
A clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
M clang/test/CodeGen/arm_acle.c
M clang/test/CodeGen/builtins-arm64.c
A clang/test/CodeGenCXX/dllexport-inherited-ctor.cpp
A clang/test/CodeGenCXX/ms-vdtors-devirtualization.cpp
M clang/test/CodeGenHLSL/BoolMatrix.hlsl
M clang/test/CodeGenHLSL/builtins/f16tof32-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/f16tof32.hlsl
M clang/test/CodeGenHLSL/builtins/f32tof16-builtin.hlsl
M clang/test/CodeGenHLSL/builtins/f32tof16.hlsl
R clang/test/DebugInfo/CXX/debug-info-constexpr-array.cpp
M clang/test/Driver/hip-options.hip
A clang/test/Driver/linker-wrapper-canonical-prefixes.c
A clang/test/Modules/deprecated-upwards-relative-path.m
M clang/test/OpenMP/for_non_rectangular_codegen.c
M clang/test/OpenMP/for_private_reduction_codegen.cpp
A clang/test/OpenMP/loop_collapse_codegen.cpp
A clang/test/Sema/AArch64/pcdphint-atomic-store.c
M clang/test/SemaCXX/dllexport.cpp
M clang/test/SemaHLSL/MatrixElementOverloadResolution.hlsl
A clang/test/SemaHLSL/Types/BuiltinMatrix/MatrixConstantExpr.hlsl
A clang/test/SemaHLSL/Types/BuiltinMatrix/MatrixFloatPrecisionWarnings.hlsl
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td
M clang/tools/clang-scan-deps/ClangScanDeps.cpp
M compiler-rt/lib/scudo/standalone/common.h
M compiler-rt/lib/scudo/standalone/fuchsia.cpp
M compiler-rt/lib/scudo/standalone/linux.cpp
M compiler-rt/lib/scudo/standalone/mem_map.cpp
M compiler-rt/lib/scudo/standalone/mem_map.h
M compiler-rt/lib/scudo/standalone/mem_map_base.h
M compiler-rt/lib/scudo/standalone/mem_map_fuchsia.cpp
M compiler-rt/lib/scudo/standalone/mem_map_fuchsia.h
M compiler-rt/lib/scudo/standalone/mem_map_linux.cpp
M compiler-rt/lib/scudo/standalone/mem_map_linux.h
M compiler-rt/lib/scudo/standalone/primary64.h
M compiler-rt/lib/scudo/standalone/secondary.h
M compiler-rt/lib/scudo/standalone/tests/common_test.cpp
M compiler-rt/lib/scudo/standalone/tests/map_test.cpp
M compiler-rt/lib/scudo/standalone/trusty.cpp
M flang/CMakeLists.txt
M flang/include/flang/Parser/openmp-utils.h
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/ClauseProcessor.h
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/OpenMP/LowerWorkshare.cpp
M flang/lib/Optimizer/Transforms/CUDA/CUFDeviceGlobal.cpp
M flang/lib/Parser/io-parsers.cpp
M flang/lib/Parser/openmp-utils.cpp
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-structure.h
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Fir/CUDA/cuda-device-global.f90
A flang/test/Integration/OpenMP/workshare-forall-sliced-array.f90
M flang/test/Lower/Intrinsics/bessel_yn.f90
M flang/test/Lower/Intrinsics/bge.f90
M flang/test/Lower/Intrinsics/bgt.f90
M flang/test/Lower/Intrinsics/ble.f90
M flang/test/Lower/Intrinsics/blt.f90
A flang/test/Lower/OpenMP/allocatable-dtype-intermediate-map-gen.f90
M flang/test/Lower/OpenMP/composite_simd_linear.f90
M flang/test/Lower/OpenMP/distribute-parallel-do-simd.f90
M flang/test/Lower/OpenMP/distribute-simd.f90
M flang/test/Lower/OpenMP/loop-pointer-variable.f90
M flang/test/Lower/OpenMP/ordered-simd.f90
M flang/test/Lower/OpenMP/wsloop-simd.f90
A flang/test/Semantics/OpenMP/affinity-invalid.f90
M flang/test/Semantics/OpenMP/depend01.f90
M flang/test/Semantics/OpenMP/reduction05.f90
A flang/test/Semantics/io17.f90
A flang/test/Transforms/OpenMP/lower-workshare-thread-local.mlir
M libc/src/__support/GPU/CMakeLists.txt
M libc/src/__support/GPU/allocator.cpp
A libc/src/__support/GPU/fixedbuffer.h
R libc/src/__support/GPU/fixedstack.h
M libc/test/integration/src/__support/GPU/CMakeLists.txt
A libc/test/integration/src/__support/GPU/fixedbuffer_test.cpp
R libc/test/integration/src/__support/GPU/fixedstack_test.cpp
M libclc/CMakeLists.txt
A libclc/clc/include/clc/address_space/qualifier.h
M libclc/clc/lib/amdgcn/SOURCES
A libclc/clc/lib/amdgcn/address_space/qualifier.cl
M libclc/clc/lib/generic/SOURCES
A libclc/clc/lib/generic/shared/clc_qualifier.cl
M libclc/opencl/lib/generic/SOURCES
A libclc/opencl/lib/generic/address_space/qualifier.cl
M libcxx/docs/ReleaseNotes/23.rst
M libcxx/include/__iterator/wrap_iter.h
M libcxx/include/regex
M libcxx/include/string
A libcxx/test/libcxx/strings/basic.string/string.cons/constexpr_initialization_stress.pass.cpp
R libcxx/test/std/strings/basic.string/string.cons/constexpr_initialization_stress.pass.cpp
M lld/test/COFF/base.test
M lld/test/COFF/heap.test
M lld/test/COFF/stack.test
M lldb/examples/python/formatter_bytecode.py
M lldb/include/lldb/Target/Platform.h
M lldb/include/lldb/Utility/UnimplementedError.h
M lldb/source/Host/windows/PseudoConsole.cpp
M lldb/source/Plugins/ExpressionParser/Clang/ClangModulesDeclVendor.cpp
M lldb/test/API/commands/watchpoints/watchpoint_commands/command/watchpoint_command.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/bitset/TestDataFormatterGenericBitset.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/coroutine_handle/TestCoroutineHandle.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/optional/TestDataFormatterGenericOptional.py
M lldb/test/API/python_api/block/TestFrameBlocks.py
M llvm/docs/CommandGuide/llvm-objdump.rst
M llvm/include/llvm/ADT/ArrayRef.h
M llvm/include/llvm/CodeGen/SDPatternMatch.h
M llvm/include/llvm/CodeGen/ValueTypes.h
M llvm/include/llvm/CodeGenTypes/MachineValueType.h
M llvm/include/llvm/IR/IntrinsicsAArch64.td
M llvm/include/llvm/MC/MCAsmBackend.h
M llvm/include/llvm/Transforms/Utils/UnrollLoop.h
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/MCAsmBackend.cpp
M llvm/lib/Object/COFFModuleDefinition.cpp
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUFeatures.td
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
M llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h
M llvm/lib/Target/M68k/MCTargetDesc/M68kAsmBackend.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZInstrVector.td
M llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrSSE.td
M llvm/lib/Transforms/Scalar/LoopUnrollAndJamPass.cpp
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/lib/Transforms/Scalar/Reassociate.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
M llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll
M llvm/test/Analysis/CostModel/AArch64/sve-math.ll
M llvm/test/Analysis/CostModel/AArch64/sve-min-max.ll
A llvm/test/CodeGen/AArch64/Issue57251.ll
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/arm64-fmax-safe.ll
M llvm/test/CodeGen/AArch64/clmul-fixed.ll
M llvm/test/CodeGen/AArch64/ctpop.ll
M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
M llvm/test/CodeGen/AArch64/neon-lowhalf128-optimisation.ll
A llvm/test/CodeGen/AArch64/pcdphint-atomic-store.ll
M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
M llvm/test/CodeGen/AArch64/popcount_vmask.ll
M llvm/test/CodeGen/AMDGPU/hazard-getreg-waitalu.mir
M llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll
M llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
M llvm/test/CodeGen/ARM/vminmaxnm-safe.ll
M llvm/test/CodeGen/BPF/objdump_cond_op.ll
M llvm/test/CodeGen/BPF/objdump_cond_op_2.ll
M llvm/test/CodeGen/NVPTX/fma-relu-contract.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
M llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_float_controls2/exec_mode3.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_NV_shader_atomic_fp16_vector/atomicrmw_faddfsub_vec_float16.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_NV_shader_atomic_fp16_vector/atomicrmw_fminfmax_vec_float16.ll
M llvm/test/CodeGen/SPIRV/pointers/fun-with-aggregate-arg-in-const-init.ll
A llvm/test/CodeGen/SystemZ/fminimumnum-fmaximumnum.ll
A llvm/test/CodeGen/WebAssembly/pr184441.ll
M llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll
A llvm/test/CodeGen/X86/bit-manip-i256.ll
A llvm/test/CodeGen/X86/bit-manip-i512.ll
M llvm/test/CodeGen/X86/known-pow2.ll
M llvm/test/CodeGen/X86/sse-minmax.ll
R llvm/test/DebugInfo/X86/debug-info-constexpr-array.ll
A llvm/test/MC/AMDGPU/gfx13_asm_vflat.s
A llvm/test/MC/AMDGPU/gfx13_asm_vflat_alias.s
M llvm/test/MC/Disassembler/X86/x86-64-avx.txt
M llvm/test/MC/X86/SSE42-32.s
M llvm/test/MC/X86/SSE42-64.s
M llvm/test/MC/X86/avx-32-att.s
M llvm/test/MC/X86/avx-64-att.s
M llvm/test/TableGen/x86-fold-tables.inc
M llvm/test/TableGen/x86-instr-mapping.inc
A llvm/test/Transforms/LoopUnroll/full-and-enable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fold-tail-low-trip-count.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/gather-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/gather-do-not-vectorize-addressing.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave-allocsize-not-equal-typesize.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product-neon.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/AArch64/pr60831-sve-inv-store-crash.ll
M llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs-apple.ll
M llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-with-wide-ops.ll
M llvm/test/Transforms/LoopVectorize/AArch64/type-shrinkage-insertelt.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-intrinsic-calls.ll
M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/predicated-first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/VPlan/AArch64/widen-call-with-intrinsic-or-libfunc.ll
A llvm/test/Transforms/LoopVectorize/VPlan/tail-folding.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-print-after-all.ll
M llvm/test/Transforms/LoopVectorize/X86/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/X86/fixed-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/X86/gather-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/gather_scatter.ll
M llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave-ptradd-with-replicated-operand.ll
M llvm/test/Transforms/LoopVectorize/X86/interleaved-accesses-hoist-load-across-store.ll
M llvm/test/Transforms/LoopVectorize/X86/iv-live-outs.ll
M llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
M llvm/test/Transforms/LoopVectorize/X86/pr36524.ll
M llvm/test/Transforms/LoopVectorize/X86/pr51366-sunk-instruction-used-outside-of-loop.ll
M llvm/test/Transforms/LoopVectorize/X86/pr72969.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-udiv.ll
M llvm/test/Transforms/LoopVectorize/X86/replicating-load-store-costs.ll
M llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
M llvm/test/Transforms/LoopVectorize/X86/uniform_mem_op.ll
M llvm/test/Transforms/LoopVectorize/X86/vplan-native-inner-loop-only.ll
M llvm/test/Transforms/LoopVectorize/X86/vplan-single-bit-ind-var-width-4.ll
M llvm/test/Transforms/LoopVectorize/X86/vplan-single-bit-ind-var.ll
M llvm/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll
M llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/cse-casts.ll
M llvm/test/Transforms/LoopVectorize/debugloc.ll
M llvm/test/Transforms/LoopVectorize/epilog-iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-any-of-reductions.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-interleave.ll
M llvm/test/Transforms/LoopVectorize/find-last-iv-sinkable-expr.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence-tail-folding.ll
M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
M llvm/test/Transforms/LoopVectorize/float-induction.ll
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads-with-predicated-stores.ll
M llvm/test/Transforms/LoopVectorize/hoist-predicated-loads.ll
M llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
M llvm/test/Transforms/LoopVectorize/induction-multiple-uses-in-same-instruction.ll
M llvm/test/Transforms/LoopVectorize/induction-ptrcasts.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll
M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
M llvm/test/Transforms/LoopVectorize/load-deref-pred-neg-off.ll
M llvm/test/Transforms/LoopVectorize/loop-form.ll
M llvm/test/Transforms/LoopVectorize/loop-with-constant-exit-condition.ll
A llvm/test/Transforms/LoopVectorize/multiple-argmin-argmax.ll
M llvm/test/Transforms/LoopVectorize/narrow-to-single-scalar.ll
M llvm/test/Transforms/LoopVectorize/operand-bundles.ll
M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction-index-width-smaller-than-iv-width.ll
M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
M llvm/test/Transforms/LoopVectorize/predicate-switch.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
M llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-div.ll
M llvm/test/Transforms/LoopVectorize/uniform-blend.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_and.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_div_urem.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_lshr.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction2.ll
M llvm/test/Transforms/LoopVectorize/use-scalar-epilogue-if-tp-fails.ll
M llvm/test/Transforms/LoopVectorize/vect-phiscev-sext-trunc.ll
M llvm/test/Transforms/LoopVectorize/version-mem-access.ll
M llvm/test/Transforms/LoopVectorize/version-stride-with-integer-casts.ll
A llvm/test/Transforms/Reassociate/reassociate-decrement-dbgvalue.ll
R llvm/test/Transforms/Reassociate/reassociate_dbgvalue_discard.ll
A llvm/test/Transforms/Reassociate/reassociate_dbgvalue_salvage.ll
A llvm/test/Transforms/SLPVectorizer/X86/expected-prof-consecutive-access.ll
A llvm/test/Transforms/SLPVectorizer/X86/shll1-add-sub-combined.ll
M llvm/test/Verifier/AArch64/intrinsic-immarg.ll
M llvm/test/tools/llvm-ir2vec/bindings/ir2vec-bindings.py
M llvm/test/tools/llvm-objdump/BPF/disassemble-symbolize-operands.s
M llvm/tools/llvm-ir2vec/Bindings/PyIR2Vec.cpp
M llvm/tools/llvm-ir2vec/lib/Utils.cpp
M llvm/tools/llvm-ir2vec/lib/Utils.h
M llvm/tools/llvm-objdump/ObjdumpOpts.td
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/unittests/ADT/ArrayRefTest.cpp
M llvm/unittests/ExecutionEngine/Orc/WaitingOnGraphTest.cpp
M mlir/include/mlir/Dialect/Bufferization/IR/BufferDeallocationOpInterface.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td
M mlir/include/mlir/Dialect/WasmSSA/IR/WasmSSAOps.td
M mlir/lib/Conversion/VectorToXeGPU/CMakeLists.txt
M mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferDeallocationOpInterface.cpp
M mlir/lib/Dialect/Bufferization/Transforms/OneShotModuleBufferize.cpp
M mlir/lib/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/Shape/IR/Shape.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseAssembler.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToWiDistributeExperimental.cpp
M mlir/lib/IR/BuiltinDialectBytecode.cpp
M mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp
M mlir/lib/Transforms/Utils/CFGToSCF.cpp
A mlir/test/Bytecode/invalid/invalid-dense-elem-type-interface.mlir
A mlir/test/Conversion/ControlFlowToSCF/unknown-cf-op.mlir
M mlir/test/Conversion/VectorToXeGPU/contract-to-xegpu.mlir
M mlir/test/Conversion/VectorToXeGPU/transfer-read-to-xegpu.mlir
M mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-branchop-interface.mlir
A mlir/test/Dialect/LLVMIR/nvvm-canonicalize.mlir
M mlir/test/Dialect/MemRef/canonicalize.mlir
M mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops.mlir
M mlir/test/Dialect/Shape/canonicalize.mlir
A mlir/test/Dialect/SparseTensor/external_after_codegen.mlir
M mlir/test/Dialect/SparseTensor/spy_sddmm.mlir
M mlir/test/Dialect/XeGPU/sg-to-wi-experimental-unit.mlir
A mlir/test/Target/LLVMIR/nvvm/addf/addf.mlir
A mlir/test/Target/LLVMIR/nvvm/addf/addf_invalid.mlir
A mlir/test/Target/LLVMIR/nvvm/addf/addf_vector.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-block-scale-shared.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-block-scale-tensor.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-invalid.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-sp-block-scale-shared.mlir
M mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-sp-block-scale-tensor.mlir
M mlir/test/Target/SPIRV/tosa-ops.mlir
M mlir/tools/mlir-src-sharder/CMakeLists.txt
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
rebase
Created using spr 1.3.7
Compare: https://github.com/llvm/llvm-project/compare/6e2ffd5eabc3...08f6fedf6f08
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