[all-commits] [llvm/llvm-project] 30086b: [RISCV] Remove RISCVVectorPeephole::tryToReduceVL ...
Luke Lau via All-commits
all-commits at lists.llvm.org
Wed Mar 4 19:59:07 PST 2026
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 30086bc246ebf3402856805977ace06951a0f1f8
https://github.com/llvm/llvm-project/commit/30086bc246ebf3402856805977ace06951a0f1f8
Author: Luke Lau <luke at igalia.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll
R llvm/test/CodeGen/RISCV/rvv/reduce-vl-peephole.ll
R llvm/test/CodeGen/RISCV/rvv/reduce-vl-peephole.mir
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
Log Message:
-----------
[RISCV] Remove RISCVVectorPeephole::tryToReduceVL (#184297)
Now that RISCVVLOptimizer has been extended to handle the remaining
cases tryToReduceVL handles, we can remove tryToReduceVL to keep all the
reduction logic in one place.
Intended to be NFC but it looks like in
test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll we were
previously reducing the vl of a volatile load in
insert_subvector_dag_loop, which RISCVVLOptimizer knows to avoid.
On llvm-test-suite and SPEC CPU 2017 -march=rva23u64 -O3 there are no
changes with this patch.
To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications
More information about the All-commits
mailing list