[all-commits] [llvm/llvm-project] 03e2af: [CIR] Fix bitfield store locations for assignment ...
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Wed Mar 4 18:44:52 PST 2026
Branch: refs/heads/users/vitalybuka/spr/libcstring-add-constexpr-initialization-stress-test
Home: https://github.com/llvm/llvm-project
Commit: 03e2af7a65ea2db96c934f8a8faa26d631b242ee
https://github.com/llvm/llvm-project/commit/03e2af7a65ea2db96c934f8a8faa26d631b242ee
Author: Akimasa Watanuki <mencotton0410 at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
A clang/test/CIR/CodeGen/bitfield-assignment-loc.c
Log Message:
-----------
[CIR] Fix bitfield store locations for assignment codegen (#184005)
Update bitfield-assignment codegen to emit stores at
assignment-expression source locations.
Keep `cir.set_bitfield` aligned with other store-like operations.
Prevent regressions that reattach bitfield stores to declaration-site
locations.
Add a CIR test on `clang/test/CIR/CodeGen/bitfield-assignment-loc.c`.
Fix https://github.com/llvm/llvm-project/issues/183759
Commit: d4d18248fde64ab8867ca81ecb16f402db7a17e8
https://github.com/llvm/llvm-project/commit/d4d18248fde64ab8867ca81ecb16f402db7a17e8
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-03-02 (Mon, 02 Mar 2026)
Changed paths:
M lldb/include/lldb/Utility/LLDBLog.h
M lldb/source/Initialization/SystemInitializerCommon.cpp
M lldb/source/Utility/LLDBLog.cpp
Log Message:
-----------
[lldb] Terminate the LLDB Log in SystemInitializerCommon::Terminate (#184261)
Currently, when calling SBDebugger::Initialize after
SBDebugger::Terminate, you hit an assert in LLDBLog when trying to
register the LLDB log a second time. Also fix the awkward
capitalization.
Commit: 1d1c83ad73977a17b06e34243a9b74f41af6da78
https://github.com/llvm/llvm-project/commit/1d1c83ad73977a17b06e34243a9b74f41af6da78
Author: Abhinav Gaba <abhinav.gaba at intel.com>
Date: 2026-03-02 (Mon, 02 Mar 2026)
Changed paths:
M offload/include/OpenMP/Mapping.h
M offload/libomptarget/OpenMP/Mapping.cpp
M offload/libomptarget/interface.cpp
M offload/libomptarget/omptarget.cpp
A offload/test/mapping/map_ordering_ptee_tgt_alloc_mapper_alloc_from_to.c
A offload/test/mapping/map_ordering_ptee_tgt_data_alloc_tgt_mapper_present_delete_from_to.c
A offload/test/mapping/map_ordering_tgt_alloc_from_to.c
A offload/test/mapping/map_ordering_tgt_alloc_present_tofrom.c
A offload/test/mapping/map_ordering_tgt_alloc_tofrom.c
A offload/test/mapping/map_ordering_tgt_data_alloc_from.c
A offload/test/mapping/map_ordering_tgt_data_alloc_to_from.c
A offload/test/mapping/map_ordering_tgt_data_alloc_tofrom.c
A offload/test/mapping/map_ordering_tgt_exit_data_always_always.c
A offload/test/mapping/map_ordering_tgt_exit_data_delete_from.c
A offload/test/mapping/map_ordering_tgt_exit_data_delete_from_assumedsize.c
A offload/test/mapping/map_ordering_tgt_exit_data_from_delete_assumedsize.c
A offload/test/mapping/map_ordering_tgt_exit_data_from_mapper_overlap.c
Log Message:
-----------
Reland "[OpenMP][Offload] Handle `present/to/from` when a different entry did `alloc/delete`." (#184260)
Some tests that were checking for prints inside/outside `target` regions
needed to be updated to work on systems where the ordering wasn't
deterministic.
Reverts llvm/llvm-project#184240
Original description from #165494:
-----
OpenMP allows cases like the following:
```c
int *p1, *p2, x;
p1 = p2 = &x;
...
#pragma omp target_exit_data map(delete: p1[:]) from(p2[0])
```
Which means, when the runtime encounters the `from` entry, the ref-count
may
not be zero, but it will go down to zero at the end of the current
construct,
which should cause the "from" transfer to happen.
Similarly, a user may have:
```c
struct S {
int *p;
};
#pragma omp declare_mapper (id1: S s) map(s.p) map(present, alloc: s.p[0:10])
#pragma omp declare_mapper (id2: S s) map(s.p, s.p[0:10])
S s1;
// present-check should fail here
#pragma omp target_enter_data map(alloc: s.p[0:10]) map(mapper(id1), to: s)
// "to" should be honored here
#pragma omp target_enter_data map(alloc: s.p[0:10]) map(mapper(id2), to: s)
```
Where the allocation happens before the "to" entry is encountered by the
runtime. Or, an allocation happens before a "present" entry is
encountered.
To handle cases like this, we need to use the state information of
previously
seen new allocations, deletions, "from" entries, when honoring
`to`/`from`/`present` map entries.
-----
Commit: 0ced81f7eabca9c4c640f8a6ebb4089c371d2fb0
https://github.com/llvm/llvm-project/commit/0ced81f7eabca9c4c640f8a6ebb4089c371d2fb0
Author: Abhinav Gaba <abhinav.gaba at intel.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M offload/test/mapping/map_ordering_ptee_tgt_alloc_mapper_alloc_from_to.c
M offload/test/mapping/map_ordering_tgt_alloc_from_to.c
M offload/test/mapping/map_ordering_tgt_alloc_tofrom.c
M offload/test/mapping/map_ordering_tgt_data_alloc_to_from.c
M offload/test/mapping/map_ordering_tgt_data_alloc_tofrom.c
Log Message:
-----------
[NFC][OpenMP] Remove redundant prints in `target` regions from tests added in #184260. (#184266)
Some buildbots don't like them, and the correctness of the values in the
`target` region is ensured via prints after the region.
Commit: 4f91d0b322a85bdad4b7440b35ba270b5277ec8c
https://github.com/llvm/llvm-project/commit/4f91d0b322a85bdad4b7440b35ba270b5277ec8c
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-03-02 (Mon, 02 Mar 2026)
Changed paths:
M libcxx/test/benchmarks/numeric/gcd.bench.cpp
M libcxx/test/benchmarks/streams/getline.bench.cpp
M libcxx/test/benchmarks/streams/ofstream.bench.cpp
Log Message:
-----------
[libc++] Give proper names to a few benchmarks (#183333)
Commit: 82319d74aae41bc1bdd59eed0b1c27cfc7b8086f
https://github.com/llvm/llvm-project/commit/82319d74aae41bc1bdd59eed0b1c27cfc7b8086f
Author: Jim Lin <jim at andestech.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSchedAndes45.td
M llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-reduction.s
Log Message:
-----------
[RISCV] Update Andes45 vector reduction scheduling info (#182980)
This PR adds latency/throughput for all RVV reductions to the andes45
series scheduling model.
Commit: a6fa21c5aabb9e7d47c221aa8403d96cb154d549
https://github.com/llvm/llvm-project/commit/a6fa21c5aabb9e7d47c221aa8403d96cb154d549
Author: Srivarshitha M <mvarshitha17874 at gmail.com>
Date: 2026-03-02 (Mon, 02 Mar 2026)
Changed paths:
A clang/test/CIR/CodeGen/c89-implicit-int.c
A clang/test/CIR/CodeGen/expressions.cpp
Log Message:
-----------
[CIR] Upstream basic CodeGen tests from incubator (#183998)
This PR upstreams `expressions.cpp` and `c89-implicit-int.c` from the
ClangIR incubator to the mainline.
Following the incremental approach discussed in #156747 and the feedback
from the closed PR #157333, I have:
1. Copied the files directly from the incubator to preserve history.
2. Updated the `RUN` lines to use the `--check-prefix=CIR` flag.
3. Converted `CHECK:` lines to `CIR:`.
4. Standardized variable captures using the `%[[VAR:.*]]` regex syntax
(in `expressions.cpp`).
Verified locally with `llvm-lit`. This is a partial fix for #156747.
*Note: As suggested in previous reviews, I am focusing only on the `CIR`
checks for now to keep the upstreaming incremental. OGCG/LLVM
verification can be added in a follow-up PR once the base tests land.*
Commit: 2407564cbfa18961f465e40ca0fb18fb754151c7
https://github.com/llvm/llvm-project/commit/2407564cbfa18961f465e40ca0fb18fb754151c7
Author: Victor Mustya <victor.mustya at intel.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/include/clang/Basic/OpenCLExtensions.def
M clang/test/SemaOpenCL/extension-version.cl
Log Message:
-----------
[Clang] Add missing extension cl_intel_split_work_group_barrier declaration (#184269)
All the OpenCL extensions must be declared in OpenCLExtensions.def,
otherwise the frontend won't recognize them and won't be able to use
them in the code. This patch adds the missing declaration for the
`cl_intel_split_work_group_barrier` extension.
Commit: 8decfb8a90dfcec032d717c195c5636b1fee7260
https://github.com/llvm/llvm-project/commit/8decfb8a90dfcec032d717c195c5636b1fee7260
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/lib/Conversion/ArithToEmitC/ArithToEmitCPass.cpp
M mlir/lib/Conversion/FuncToEmitC/FuncToEmitCPass.cpp
M mlir/test/Conversion/ArithToEmitC/arith-to-emitc-failed.mlir
A mlir/test/Conversion/FuncToEmitC/func-to-emitc-failed.mlir
Log Message:
-----------
[mlir][emitc] Do not convert illegal types to emitc (#156222)
This PR adds fallbacks for other types instead of converting unsupported
types to emitc.
Commit: 52f32d780fa2da1f5e54e80c91a0e79379e141d0
https://github.com/llvm/llvm-project/commit/52f32d780fa2da1f5e54e80c91a0e79379e141d0
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M .github/workflows/containers/github-action-ci-windows/Dockerfile
M .github/workflows/containers/github-action-ci/Dockerfile
Log Message:
-----------
[Github] Bump Github Runner to v2.332.0 (#184230)
To stay ahead of the support horizon. There were no major feature
changes/bug fixes from a cursory glance at the release notes.
Commit: 92aa2d36f020952087068dee186568c33a77088d
https://github.com/llvm/llvm-project/commit/92aa2d36f020952087068dee186568c33a77088d
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-03-02 (Mon, 02 Mar 2026)
Changed paths:
M .github/workflows/containers/github-action-ci-windows/Dockerfile
Log Message:
-----------
[Github] Respect LLVM_VERSION when building windows container (#184231)
Otherwise setting LLVM_VERSION does not actually do anything. This
avoids needing to update ~8 different locations in the file when doing a
toolchain bump to just 1 place.
Commit: e63e55cae8ce29150f38a758555d9cc712a1cf4c
https://github.com/llvm/llvm-project/commit/e63e55cae8ce29150f38a758555d9cc712a1cf4c
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-03-02 (Mon, 02 Mar 2026)
Changed paths:
M flang/include/flang/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.h
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.cpp
M flang/lib/Optimizer/OpenACC/Support/RegisterOpenACCExtensions.cpp
A flang/test/Transforms/OpenACC/acc-recipe-materialization-firstprivate-derived.fir
A flang/test/Transforms/OpenACC/acc-recipe-materialization-firstprivate.fir
A flang/test/Transforms/OpenACC/acc-recipe-materialization-kernel-private.fir
A flang/test/Transforms/OpenACC/acc-recipe-materialization-parallel.fir
A flang/test/Transforms/OpenACC/acc-recipe-materialization-private.fir
A flang/test/Transforms/OpenACC/acc-recipe-materialization-reduction.fir
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsLoop.h
M mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
M mlir/lib/Dialect/OpenACC/IR/OpenACCCG.cpp
A mlir/lib/Dialect/OpenACC/Transforms/ACCRecipeMaterialization.cpp
M mlir/lib/Dialect/OpenACC/Transforms/CMakeLists.txt
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsLoop.cpp
A mlir/test/Dialect/OpenACC/acc-recipe-materialization-firstprivate.mlir
A mlir/test/Dialect/OpenACC/acc-recipe-materialization-kernel-private.mlir
A mlir/test/Dialect/OpenACC/acc-recipe-materialization-parallel.mlir
A mlir/test/Dialect/OpenACC/acc-recipe-materialization-private.mlir
A mlir/test/Dialect/OpenACC/acc-recipe-materialization-reduction.mlir
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsLoopTest.cpp
Log Message:
-----------
[mlir][acc] Add ACCRecipeMaterialization pass and reduction ops (#184252)
Pass
----
Add the `acc-recipe-materialization` pass, which materializes OpenACC
privatization, firstprivate and reduction recipes by inlining their
init, copy, combiner, and destroy regions into the operation for the
construct. The pass runs on acc.parallel, acc.serial, acc.kernels, and
acc.loop.
- Firstprivate: Inserts acc.firstprivate_map so the initial value is
available on the device, then clones the recipe init and copy regions
into the construct and replaces uses with the materialized alloca.
Optional destroy region is cloned before the region terminator.
- Private: Clones the recipe init region into the construct (at region
entry or at the loop op for acc.loop private). Replaces uses of the
recipe result with the materialized alloca. Optional destroy region is
cloned before the region terminator.
- Reduction: Creates acc.reduction_init (init region inlined) and
acc.reduction_combine_region (combiner region inlined). All uses of the
reduction in the region are updated to the reduction init result.
New operations
--------------
- acc.reduction_init: Allocates and initializes a private reduction
variable from a recipe. Takes the original reduction variable and
reduction_operator; has a single region that must yield one value (the
private storage) via acc.yield. Used by the pass to materialize
acc.reduction_recipe init regions inside the compute construct.
- acc.reduction_combine_region: Combines the private reduction value
with the shared reduction variable. Takes the shared and private
memrefs; has a single region (the recipe combiner) terminated by
acc.yield with no operands. Used by the pass to materialize the
reduction recipe combiner.
Both ops implement RegionBranchOpInterface. acc.yield is updated to
allow terminating ReductionInitOp and ReductionCombineRegionOp regions.
Supporting changes
------------------
- OpenACCUtilsLoop: Factor cloneACCRegionInto out of the existing
loop-conversion helper so the pass can clone recipe regions with
optional result replacement; loop conversion now calls the shared
helper.
- Flang: Add ReductionInitOpFortranObjectViewModel
(FortranObjectViewOpInterface) for acc.reduction_init and register it in
OpenACC extensions.
Tests
-----
- MLIR: acc-recipe-materialization-{firstprivate,private,reduction,
kernel-private,parallel}.mlir (memref dialect).
- Flang: acc-recipe-materialization-{firstprivate,firstprivate-derived,
private,reduction,kernel-private,parallel}.fir; firstprivate test has a
second RUN with -acc-optimize-firstprivate-map.
---------
Co-authored-by: Scott Manley <rscottmanley at gmail.com>
Commit: 768240d019523a7887a0032948620d42129fae98
https://github.com/llvm/llvm-project/commit/768240d019523a7887a0032948620d42129fae98
Author: Shoreshen <372660931 at qq.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/ARM/ARMCallLowering.cpp
M llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp
M llvm/lib/Target/M68k/GISel/M68kCallLowering.h
M llvm/lib/Target/Mips/MipsCallLowering.cpp
M llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
M llvm/lib/Target/PowerPC/GISel/PPCCallLowering.h
M llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
M llvm/lib/Target/X86/GISel/X86CallLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/ashr64_reduce.ll
R llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll
A llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/sdag-print-divergence.ll
M llvm/test/CodeGen/AMDGPU/shl64_reduce.ll
M llvm/test/CodeGen/AMDGPU/srl64_reduce.ll
Log Message:
-----------
[AMDGPU] Insert readfirstlane for uniform VGPR arguments (#178198)
Fix inreg argument, which is uniform, but using VGPR due to run out of
SGPR.
---------
Co-authored-by: Matt Arsenault <Matthew.Arsenault at amd.com>
Commit: 6d25af00ac475e0b1f7d2b7a9ca24a223930a8d2
https://github.com/llvm/llvm-project/commit/6d25af00ac475e0b1f7d2b7a9ca24a223930a8d2
Author: Henrik G. Olsson <hnrklssn at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/utils/lit/lit/TestRunner.py
M llvm/utils/lit/lit/display.py
Log Message:
-----------
[utils] use annotations from __future__ in lit (#184225)
Commit: 572a0e45c6375a34bef4cd43e30c226d5598fc5f
https://github.com/llvm/llvm-project/commit/572a0e45c6375a34bef4cd43e30c226d5598fc5f
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Log Message:
-----------
AMDGPU: Remove "MBUF" from "loadMBUFScalarOperandsFromVGPR" (#184282)
There is nothing MBUF-specific about this function.
Commit: b23438661c1056bae385daba1501afb762d1e336
https://github.com/llvm/llvm-project/commit/b23438661c1056bae385daba1501afb762d1e336
Author: Jason Van Beusekom <jason.van-beusekom at hpe.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/include/clang/AST/ASTMutationListener.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/lib/Frontend/MultiplexConsumer.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Serialization/ASTCommon.h
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/test/OpenMP/target_indirect_codegen.cpp
A clang/test/OpenMP/target_vtable_omp_indirect_call_lookup.cpp
M offload/test/api/omp_indirect_call_table_manual.c
A offload/test/api/omp_indirect_func_array.c
A offload/test/api/omp_indirect_func_basic.c
A offload/test/api/omp_indirect_func_struct.c
A offload/test/api/omp_virtual_func.cpp
A offload/test/api/omp_virtual_func_multiple_inheritance_01.cpp
A offload/test/api/omp_virtual_func_multiple_inheritance_02.cpp
A offload/test/api/omp_virtual_func_reference.cpp
Log Message:
-----------
[OpenMP][clang] Indirect and Virtual function call mapping from host to device (#159857)
This patch implements the CodeGen logic for calling __llvm_omp_indirect_call_lookup
on the device when an indirect function call or a virtual function call is made
within an OpenMP target region.
---------
Co-authored-by: Youngsuk Kim
Commit: 198f85ea7c17141f3cd46d0a69044aea52163677
https://github.com/llvm/llvm-project/commit/198f85ea7c17141f3cd46d0a69044aea52163677
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/test/CodeGenCXX/pfp-member-pointer-offsetof.cpp
Log Message:
-----------
[clang][bytecode] Fix newly added pfp test (#184137)
Do the same thing 370d7ce58011eccfab8105eddbc028cc09c4c5e5 did in
ExprConstant.cpp
Commit: 5a53fce8582b7d558d1e4406406ccc143b3a51ff
https://github.com/llvm/llvm-project/commit/5a53fce8582b7d558d1e4406406ccc143b3a51ff
Author: Kavin Gnanapandithan <kavin.balag at gmail.com>
Date: 2026-03-02 (Mon, 02 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVMoveMerger.cpp
M llvm/test/CodeGen/RISCV/copysign-casts.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-mem.ll
M llvm/test/CodeGen/RISCV/double-select-fcmp.ll
M llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
Log Message:
-----------
[RISCV] Extends RISCVMoveMerger to merge GPRPairs independent of even/odd pair instruction order. (#183657)
This PR addresses post-commit reviews in #182416
Previously, `RISCVMoveMerger` only identified and merged 32-bit moves
into a 64-bit GPRPair move if the even-indexed register most appeared
before the odd-index register move.
This patch extends the pass by disregarding the order of even/odd-index
pair.
Commit: a85dbcfe016d8cce9bfea0d9265f3f69c40572e7
https://github.com/llvm/llvm-project/commit/a85dbcfe016d8cce9bfea0d9265f3f69c40572e7
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
Log Message:
-----------
[clang][bytecode] Reject non-VarDecl DeclRefExprs (#184141)
I have no idea how to test this, but this is what the current
interpreter does.
Commit: da8929bd2404553954394d6b08ae2ad516aea650
https://github.com/llvm/llvm-project/commit/da8929bd2404553954394d6b08ae2ad516aea650
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel][mlir][acc] Port e63e55cae8ce29150f38a758555d9cc712a1cf4c (#184289)
Co-authored-by: Pranav Kant <prka at google.com>
Commit: eba4a76597dd1d655794cb5732ace534b58bd97d
https://github.com/llvm/llvm-project/commit/eba4a76597dd1d655794cb5732ace534b58bd97d
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-03-02 (Mon, 02 Mar 2026)
Changed paths:
M compiler-rt/test/cfi/icall/bad-signature.c
Log Message:
-----------
[CFI] Expand test to include minimal runtime (#183646)
`ubsan_minimal` contains some CFI tests, but it would be nice have one
on CFI side.
Commit: 30fc31aa71fa784c9b9e35452653003de93e1dbc
https://github.com/llvm/llvm-project/commit/30fc31aa71fa784c9b9e35452653003de93e1dbc
Author: Jaydeep Chauhan <chauhan.jaydeep.ashwinbhai at intel.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/include/llvm/TableGen/CodeGenHelpers.h
Log Message:
-----------
[NFC][TableGen] Add deleted copy operations for RAII guard classes (#184168)
Commit: 84d0f8766de29ee8e4b45f8cdd5278c503a0e20f
https://github.com/llvm/llvm-project/commit/84d0f8766de29ee8e4b45f8cdd5278c503a0e20f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-02 (Mon, 02 Mar 2026)
Changed paths:
M clang/lib/Headers/CMakeLists.txt
Log Message:
-----------
[RISCV] Alphabetize riscv_files in clang/lib/Headers/CMakeLists.txt. NFC (#184024)
Commit: 75b0cf39b2f85635b37b4be078f65c66e1c0e3d6
https://github.com/llvm/llvm-project/commit/75b0cf39b2f85635b37b4be078f65c66e1c0e3d6
Author: Qihan Cai <caiqihan021 at hotmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rv64p.ll
Log Message:
-----------
[RISCV] Add scalar saturating add/sub operations for i32 for RV64P (#184062)
Commit: 4ea39c43e1338a16cf165f234dd88b8ecb53dcd1
https://github.com/llvm/llvm-project/commit/4ea39c43e1338a16cf165f234dd88b8ecb53dcd1
Author: Junji Watanabe <watanabe0621 at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/utils/lit/lit/LitConfig.py
M llvm/utils/lit/lit/TestRunner.py
M llvm/utils/lit/lit/llvm/config.py
M llvm/utils/lit/tests/lit.cfg
M llvm/utils/lit/tests/shtest-readfile.py
M llvm/utils/llvm-lit/llvm-lit.in
Log Message:
-----------
[LIT] Use forward slashes in substitutions when LLVM_WINDOWS_PREFER_FORWARD_SLASH is set (#179865)
When building with `-DLLVM_WINDOWS_PREFER_FORWARD_SLASH=ON`, tools like
lld output paths with forward slashes on Windows. However, lit's default
substitutions (`%t`, `%p`) typically use backslashes on Windows, causing
FileCheck failures in tests that strictly match path separators.
This patch propagates the `LLVM_WINDOWS_PREFER_FORWARD_SLASH` build flag
to llvm-lit via `builtin_parameters`. It also updates lit's TestRunner
to respect the 'use_normalized_slashes' parameter. When enabled, lit
normalizes paths in substitutions to use forward slashes, ensuring that
test expectations align with the tool output.
With this fix, the number of failed tests with
`-DLLVM_WINDOWS_PREFER_FORWARD_SLASH=ON` changes as follow:
- The total number of failed tests: 303 -> 168
- Break down:
- `Builtins-i386-windows` tests: 99 -> 0
- `Clang` tests: 28 -> 5
- `Clang Tools` tests: 7 -> 1
- `LLVM` tests: 6 -> 4
- `lld` tests: 2 -> 0
- Other failed tests:
- `glang`: 1
- `Clang-Unit`: 5
- `Clangd`: 3
- `Clangd Unit Tests`: 150
- `LLVM-Unit`: 1
Commit: d20395cfa3bb5c4d3a7cc61f28dc4faa2dd57eba
https://github.com/llvm/llvm-project/commit/d20395cfa3bb5c4d3a7cc61f28dc4faa2dd57eba
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-02 (Mon, 02 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/test/CodeGen/AArch64/clmul-fixed.ll
M llvm/test/CodeGen/AArch64/clmul-scalable.ll
M llvm/test/CodeGen/PowerPC/clmul-vector.ll
M llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-clmul.ll
M llvm/test/CodeGen/X86/clmul-vector-256.ll
M llvm/test/CodeGen/X86/clmul-vector-512.ll
M llvm/test/CodeGen/X86/clmul-vector.ll
Log Message:
-----------
[LegalizeVectorOps][RISCV][PowerPC][AArch64][X86] Enable the clmul/clmulr/clmulh expansion code. (#184257)
These opcodes weren't added to the master switch statement that
determines if they should be considered vector ops.
Commit: e4def2d11fb5b482dd4614601fc8018c42a824b9
https://github.com/llvm/llvm-project/commit/e4def2d11fb5b482dd4614601fc8018c42a824b9
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
Log Message:
-----------
[AMDGPU] Make the options consistent across 3 RA pipelines(NFC) (#184190)
Adding the missing option for the wwm-regalloc in the test
attr-amdgpu-flat-work-group-size-vgpr-limit.ll. The existing
test already specifies -sgpr-regalloc=fast & -vgpr-regalloc=fast
to ensure that the fast register allocator is preferred over
the default greedy allocator. For consistency, the same
preference should also be applied to the wwm-regalloc pipeline.
Commit: 0504af9e3bf76deea13c8a83928de36b3b816355
https://github.com/llvm/llvm-project/commit/0504af9e3bf76deea13c8a83928de36b3b816355
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Analysis/CmpInstAnalysis.cpp
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Analysis/InlineCost.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CAS/OnDiskCommon.cpp
M llvm/lib/CodeGen/RegisterClassInfo.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/LibraryScanner.cpp
M llvm/lib/IR/ConstantRange.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/LTO/LTO.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/Support/APFixedPoint.cpp
M llvm/lib/Support/APFloat.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/NewGVN.cpp
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
M llvm/tools/llvm-dwarfdump/Coverage.cpp
M llvm/tools/llvm-readobj/ELFDumper.cpp
Log Message:
-----------
[llvm] Turn misc copy-assign to move-assign (#184143)
That's an automated patch generated from clang-tidy
performance-use-std-move as a follow-up to #184136
Commit: f67c2cd75e256af054919bee68886ebd51155b39
https://github.com/llvm/llvm-project/commit/f67c2cd75e256af054919bee68886ebd51155b39
Author: Luke Lau <luke at igalia.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
M llvm/test/CodeGen/RISCV/rvv/vabd.ll
M llvm/test/CodeGen/RISCV/rvv/vabdu.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
Log Message:
-----------
[RISCV] Handle Zvabd and XRivosVizip EEWs in RISCVVLOptimizer (#184117)
This allows the VL optimizer to handle more cases that
RISCVVectorPeephole currently catches.
The XRivosVizip instructions have ReadsPastVL=true, so only the vl of
the zip instruction itself is reduced, not its inputs.
Commit: 78ac964c47cbdbc64e84c3230ba76fe774e8dd1b
https://github.com/llvm/llvm-project/commit/78ac964c47cbdbc64e84c3230ba76fe774e8dd1b
Author: quic_hchandel <hchandel at qti.qualcomm.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/test/CodeGen/RISCV/opt-w-instrs.mir
Log Message:
-----------
[RISCV][NFC] Prepare for Short Forward Branch of branches with immediates (#182456)
This NFC patch introduces two key updates:
- It replaces the `gpr` operand type with `sfb_rhs` for the `rhs`
operand in the short forward branch optimization pseudos. The `sfb_rhs`
type supports both register and immediate operands.
- It updates the pseudos to use branch opcodes instead of condition
codes, which were used prior to this change.
Together, these changes prepare the existing codebase to support short
forward branches that compare a register with an immediate value.
Currently, short forward branch support is limited to
register-to-register comparisons
Commit: 0fff939c1aa9eacabd9019b822e399a426ea97fa
https://github.com/llvm/llvm-project/commit/0fff939c1aa9eacabd9019b822e399a426ea97fa
Author: Adam Siemieniuk <adam.siemieniuk at intel.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/test/Dialect/Linalg/transform-lower-pack.mlir
M mlir/test/Dialect/Linalg/transform-tile-and-fuse-pack-unpack.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/pack-unpack-mmt4d.mlir
Log Message:
-----------
[mlir][linalg] Lower unpack - capture handle to created copy op (#183744)
Adds missing copy op created to unpack lowering results. Corresponding
transform op is also updated with the new result value.
Commit: 7fb5a02dcda1018ccc462b114593eca400c3b528
https://github.com/llvm/llvm-project/commit/7fb5a02dcda1018ccc462b114593eca400c3b528
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
A clang/include/clang/AST/pch.h
M clang/lib/AST/CMakeLists.txt
Log Message:
-----------
[CMake][AST] Add PCH (#183358)
Add frequently used expensive headers from clang/AST to a PCH.
Results in a 13% stage2-clang build time improvement.
Commit: a631c3f4077cf84c90f9dfa98a9bdbc1e568f055
https://github.com/llvm/llvm-project/commit/a631c3f4077cf84c90f9dfa98a9bdbc1e568f055
Author: Davide Grohmann <davide.grohmann at arm.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
Log Message:
-----------
[mlir][spirv] Expand verifier testing for spirv.Tosa ops (#184112)
Also keep test order aligned with op definition order.
Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
Commit: ecb694de65e87a941f7a0cd658cef7016b0eaa77
https://github.com/llvm/llvm-project/commit/ecb694de65e87a941f7a0cd658cef7016b0eaa77
Author: Steffen Larsen <sholstla at amd.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/lib/Analysis/UnsafeBufferUsage.cpp
Log Message:
-----------
[Clang][NFCI] Initialize PredefinedNames immediately (#183295)
In isPredefinedUnsafeLibcFunc the set of predefined names is initialized
lazily. However, this pattern is redundant as function-scope static
variables are initialized on first pass through the control flow. This
commit makes the variable constant, makes it a non-heap object, and
initializes it immediately. This has the following benefits:
- The initialization pattern cleaner and potentially easier for the
compiler to optimize.
- Making the variable const avoids it being used as mutable global
state.
- Having immediate initialization removes a potential race condition.
Signed-off-by: Steffen Holst Larsen <sholstla at amd.com>
Commit: b67536954eb1ce439b203073ba297f557a153eaa
https://github.com/llvm/llvm-project/commit/b67536954eb1ce439b203073ba297f557a153eaa
Author: Steffen Larsen <sholstla at amd.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/include/clang/Basic/TargetCXXABI.h
M clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/RangedConstraintManager.h
M clang/lib/AST/TypePrinter.cpp
M clang/lib/Basic/Targets/AVR.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/ModuleBuilder.cpp
M clang/lib/Driver/Distro.cpp
M clang/lib/Options/DriverOptions.cpp
M clang/lib/Sema/SemaOpenACCClauseAppertainment.cpp
M clang/lib/StaticAnalyzer/Checkers/ErrnoModeling.cpp
M clang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp
Log Message:
-----------
[Clang][NFCI] Make unchanged global state const (#183478)
To avoid modifications to global state that does not currently need to
be modified, this patch makes a selection of trivial cases const. This
aims to help preserve the intention of these variables and reduce the
potential mutable global state surface of clang.
---------
Signed-off-by: Steffen Holst Larsen <sholstla at amd.com>
Commit: 9cda40735a17194fec9cac9689dd5acf1eb1a44f
https://github.com/llvm/llvm-project/commit/9cda40735a17194fec9cac9689dd5acf1eb1a44f
Author: Weibo He <NewSigma at 163.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaCoroutine.cpp
A clang/test/CodeGenCoroutines/coro-gro3.cpp
Log Message:
-----------
[clang][Sema] Fix initialization of GRO when GRO-return type mismatches (CWG2563) (#179156)
This patch implements one piece of proposed solution to
[CWG2563](https://cplusplus.github.io/CWG/issues/2563.html):
> get-return-object-invocation is as follows:
> ...
> otherwise, get-return-object-invocation initializes a variable with
the exposition-only name gro as if by
> decltype(auto) gro = promise.get_return_object();
Close #98744
Commit: eb1e808fdb44fee0cb8beea0ea8f162b82e8d92f
https://github.com/llvm/llvm-project/commit/eb1e808fdb44fee0cb8beea0ea8f162b82e8d92f
Author: Gergo Stomfai <stomfaig at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/include/llvm/IR/Intrinsics.td
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/CodeGen/X86/AMX/amx-low-intrinsics-no-amx-bitcast.ll
M llvm/test/CodeGen/X86/AMX/amx-low-intrinsics.ll
M llvm/test/Transforms/SLPVectorizer/X86/extracts-non-extendable.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-load-reduced-as-part-of-bv.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
M llvm/test/Transforms/SLPVectorizer/reduction-gather-non-scheduled-extracts.ll
M llvm/unittests/Analysis/ValueTrackingTest.cpp
Log Message:
-----------
[IR] Mark reduction intrinsics as nocreateundeforpoison (#184173)
In investigating #156233, it came up that select folds like here:
https://alive2.llvm.org/ce/z/Y6jzj6 cannot be carried out, or easily
fixed for now, because integer reductions do not propagate noundef, even
if their arguments are noundef. This patch adds this propagation.
Commit: 0933b634c6a272e5f5ed53da21118eecb15ee940
https://github.com/llvm/llvm-project/commit/0933b634c6a272e5f5ed53da21118eecb15ee940
Author: Frederik Harwath <frederik.harwath at amd.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
Log Message:
-----------
[AMDGPU] IGroupLP: Refactor SchedGroup::initSchedGroup (NFC) (#184122)
There are three overloaded SchedGroup::initSchedGroup functions, two of
which are only used for specific types of SchedGroups, namely
SCHED_BARRIER and SCHED_GROUP_BARRIER. This seems to have a led to some
confusion since the different functions perform checks which are not
needed for their intended restricted use cases. Furthermore, there are
several wrong comments surrounding those functions.
Simplify the functions and inline the actual initialization parts of the
SCHED_BARRIER and SCHED_GROUP_BARRIER variants at their only call sites.
Extract a function that finds the candidate SUnits for a given
SchedGroup and use this instead of initSchedGroup. Fix comments.
Commit: 92bd6eee4db36d931f5c0ca7c9614a22c9b08a63
https://github.com/llvm/llvm-project/commit/92bd6eee4db36d931f5c0ca7c9614a22c9b08a63
Author: Volodymyr Turanskyy <vturanskyy at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M libc/config/baremetal/aarch64/entrypoints.txt
M libc/config/baremetal/arm/entrypoints.txt
M libc/src/stdio/baremetal/CMakeLists.txt
A libc/src/stdio/baremetal/fflush.cpp
A libc/src/stdio/baremetal/file_internal.cpp
M libc/src/stdio/baremetal/file_internal.h
M libc/src/stdio/baremetal/getc.cpp
A libc/src/stdio/baremetal/ungetc.cpp
M libc/src/stdio/baremetal/vfscanf_internal.h
Log Message:
-----------
[libc] Reland add getc, ungetc, fflush to enable libc++ iostream on baremetal (#183556)
After https://github.com/llvm/llvm-project/pull/168931 landed getc,
ungetc and fflush are still missing at link time while trying to make
libc++ std::cout work with LLVM libc on baremetal.
ungetc implementation is very minimal only to cover the current standard
streams implementation from the patch above.
The original PR https://github.com/llvm/llvm-project/pull/175530 caused
build failure on Windows because of too long command line in the
generated *.bat file which was fixed by
https://github.com/llvm/llvm-project/issues/182374
Commit: c4e2f79c22d2e22564cba60a7f4c1b126d6dfad9
https://github.com/llvm/llvm-project/commit/c4e2f79c22d2e22564cba60a7f4c1b126d6dfad9
Author: David Green <david.green at arm.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AArch64/srem-vec-crash.ll
Log Message:
-----------
[AArch64][GlobalISel] Limit srem by const of small sizes. (#184066)
The code in SignedDivisionByConstantInfo::get can only handle bitwidths
>= 3. This adds a check for bitwidth==1 for urem too, although it will
already have been simplified.
Commit: 09217ba90459efe47c2309ab51b168a869f377d3
https://github.com/llvm/llvm-project/commit/09217ba90459efe47c2309ab51b168a869f377d3
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M lldb/test/API/lang/cpp/template/TestTemplateArgs.py
M lldb/test/API/python_api/event/TestEvents.py
M lldb/test/API/python_api/type/TestTypeList.py
Log Message:
-----------
[lldb] Disable shared build for TestTemplateArgs,TestEvents,TestTypeList (#184304)
See https://github.com/llvm/llvm-project/pull/181720
Commit: 39f2740faceafb5bb9fc2ad799eb17135faa1a38
https://github.com/llvm/llvm-project/commit/39f2740faceafb5bb9fc2ad799eb17135faa1a38
Author: Frederik Harwath <frederik.harwath at amd.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
Log Message:
-----------
[AMDGPU] IGroupLP: Avoid repeating reachability checks in greedy algorithm (#182463)
In the greedy pipeline solver, the group cost is found using the
addEdges function and the edges must be removed from the DAG after
processing each group. The best group edges are then reinserted using
the same function. This repeats the costly reachability checks inside
the function which become problematic for pipelines with many
SchedGroups.
The algorithm is changed to remember the best group edges instead of
recomputing them. Additionally, SchedGroup::tryAddEdge is refactored to
avoid a redundant cycle check which is already performed by DAG->addEdge.
Commit: b4743b2641b60fc0f577657be4ee884461e46e33
https://github.com/llvm/llvm-project/commit/b4743b2641b60fc0f577657be4ee884461e46e33
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Introduce VPlan::get(Zero|AllOnes) (NFC) (#184085)
Commit: 5d8c6c198ddefc6b63449fd66b99b83e929da15c
https://github.com/llvm/llvm-project/commit/5d8c6c198ddefc6b63449fd66b99b83e929da15c
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Mention allocation elision (#177592)
allockind / alloc-family enable allocation elision, but this was not
previously mentioned by LangRef.
Related discussion:
https://discourse.llvm.org/t/rfc-clarifying-semantic-assumptions-for-custom-allocators/89469
The semantics here are specified in terms of allowed transforms.
Making the semantics operational is tracked in #184102.
Commit: b4fffcd8e4157b72a19393ff2c2b5fcc5f51bae2
https://github.com/llvm/llvm-project/commit/b4fffcd8e4157b72a19393ff2c2b5fcc5f51bae2
Author: Srinivasa Ravi <srinivasar at nvidia.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/docs/NVPTXUsage.rst
Log Message:
-----------
[NFC][Docs] Add documentation for NVPTX conversion intrinsics (#175536)
This change adds documentation for the NVPTX narrow floating-point
conversion intrinsics.
PTX ISA Reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt
Commit: 8879ff136c73c201d48d5334a0729d7817a7c643
https://github.com/llvm/llvm-project/commit/8879ff136c73c201d48d5334a0729d7817a7c643
Author: Fuad Ismail <fuad1502 at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
A llvm/test/CodeGen/MIR/Generic/machine-function-empty-name-no-ir-section.mir
A llvm/test/CodeGen/MIR/Generic/machine-function-empty-name-no-matching-ir.mir
A llvm/test/CodeGen/MIR/Generic/machine-function-empty-name.mir
Log Message:
-----------
Support unnamed functions in MIR parser (#183018)
In this PR, unnamed machine functions in an MIR file are associated with
anonymous functions in the embedded LLVM IR according to the order in
which they are specified. If there are more unnamed machine functions
then there are LLVM IR functions, the parsing will fail by reporting the
original error message of `function ‘’ isn’t defined in the provided
LLVM IR`.
Closes #36511
Commit: 91e73b93e881c585b353afc43b8353dc6fda1fe6
https://github.com/llvm/llvm-project/commit/91e73b93e881c585b353afc43b8353dc6fda1fe6
Author: Artem Kroviakov <71938912+akroviakov at users.noreply.github.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/test/Dialect/XeGPU/resolve-layout-conflicts.mlir
Log Message:
-----------
[MLIR][XeGPU] Allow uniform vectors in layout conflict resolution (#183756)
Commit: 4d3bdc0f89475ad5064eb992494be2e3789ae851
https://github.com/llvm/llvm-project/commit/4d3bdc0f89475ad5064eb992494be2e3789ae851
Author: David Spickett <david.spickett at arm.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M lldb/source/Commands/CommandObjectWatchpoint.cpp
Log Message:
-----------
[lldb] Use AppendMessageWithFormatv in ComandObjectWatchpoint (#184128)
All of the AppendMessage... methods of CommandReturnObject automatically
add a newline, apart from AppendMessageWithFormat. This gets very
confusing when reviewing changes to commands.
While there are use cases for building a message as you go, controlling
when the newline is emitted, a lot of calls to AppendMessageWithFormat
include a newline at the end of the format string.
Such as in the watchpoint commands. So I've converted them to equivalent
AppendMessageWithFormatv calls so that:
* They have the less surprising behaviour re. newlines.
* They are in many cases more readable than the printf style notation.
Commit: d1c563beee794b3a967786fd07c437ffc66fb7f0
https://github.com/llvm/llvm-project/commit/d1c563beee794b3a967786fd07c437ffc66fb7f0
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M lldb/unittests/Target/CMakeLists.txt
Log Message:
-----------
[lldb] Don't link TestingSupport as a component (#184310)
This doesn't work with dylib builds, because TestingSupport is not part
of the dylib. Instead, we should link it via LINK_LIBS, like other tests
already do.
Commit: 5e814e26dd72d14ac1118a647210294d38c8d01e
https://github.com/llvm/llvm-project/commit/5e814e26dd72d14ac1118a647210294d38c8d01e
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/lib/Dialect/LLVMIR/Transforms/InlinerInterfaceImpl.cpp
M mlir/test/Dialect/LLVMIR/inlining.mlir
Log Message:
-----------
[mlir][llvm] Fix crash in LLVM inliner when callee has no recognized terminator (#183949)
When the callee of an llvm.call has a body block ending with an
unregistered op (rather than a recognized LLVM terminator like
llvm.return), the LLVM inliner's handleTerminator method was called with
that unregistered op and crashed via a cast<LLVM::ReturnOp>() assertion
or use-after-erase due to unresolved call result uses.
The root cause is that the generic MLIR verifier conservatively treats
unregistered ops as potential terminators (using mightHaveTrait), so
malformed IR of this shape passes verification. The inliner, however,
assumes that the callee's terminator is a recognized LLVM op.
Fix by adding a guard in LLVMInlinerInterface::isLegalToInline() that
refuses to inline a callee containing any block whose last operation
does not have the IsTerminator trait. This prevents the crash and leaves
the call site intact without any IR mutation.
Fixes #108363
Fixes #118766
Commit: 03a9ebc8974bb45d9a48c9016faaf3bb92a1f41b
https://github.com/llvm/llvm-project/commit/03a9ebc8974bb45d9a48c9016faaf3bb92a1f41b
Author: Shekhar <95859857+levi42x at users.noreply.github.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/X86/known-never-zero.ll
Log Message:
-----------
[DAG] isKnownNeverZero - add ISD::UADDSAT/UMAX/UMIN DemandedElts handling and tests (#183992)
Fixes #183038
Adds `isKnownNeverZero` support for `UADDSAT`, `UMAX`, and `UMIN`. This
allows the compiler to prove a vector result is _non-zero_ by analyzing
only the demanded lanes of its operands.
Commit: 0b36d4265e301699aef184e0405da35e4c2461e5
https://github.com/llvm/llvm-project/commit/0b36d4265e301699aef184e0405da35e4c2461e5
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/veclib-llvm.pow.ll
M llvm/test/CodeGen/ARM/pow.ll
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/armpl.ll
Log Message:
-----------
[AArch64] Add vector expansion support for ISD::FCBRT when using ArmPL (#183750)
This patch teaches the backend how to lower the FCBRT DAG node to the
vector math library function when using ArmPL. This is similar to what
we already do for llvm.pow/FPOW, however the only way to expose this is
via a DAG combine that converts
FPOW(<2 x double> %x, <2 x double> <double 1.0/3.0, double 1.0/3.0>)
into
FCBRT(<2 x double> %x)
when the appropriate fast math flags are present on the node. I've
updated the DAG combine to handle vector types and only perform the
transformation if there exists a vector library variant of cbrt.
Commit: 245887e343d37309f2ce7f728ebd4c71dc9ee4e6
https://github.com/llvm/llvm-project/commit/245887e343d37309f2ce7f728ebd4c71dc9ee4e6
Author: Aadarsh Keshri <120744385+Aadarsh-Keshri at users.noreply.github.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
A llvm/test/CodeGen/X86/veclib-llvm.sincos.ll
Log Message:
-----------
[X86] Added sincos vector lib codegen test coverage (#183702)
Added veclib-llvm.sincos.ll tests for amdlibm and libmvec
Fixes #182847
Commit: 36cced2b8244517778a9b097bd2b60f5b1e690e4
https://github.com/llvm/llvm-project/commit/36cced2b8244517778a9b097bd2b60f5b1e690e4
Author: Nashe Mncube <nashe.mncube at arm.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
R llvm/test/tools/llvm-mca/AArch64/Apple/Inputs/basic-instructions.s
R llvm/test/tools/llvm-mca/AArch64/Apple/Inputs/neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Apple/M1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Apple/M1-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A57-basic-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Inputs/basic-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Inputs/bf16-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Inputs/complxnum-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Inputs/fp16fml-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Inputs/fptoint-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Inputs/i8mm-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Inputs/mte-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Inputs/neon-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Inputs/rcpc-immo-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Inputs/sve-instructions.s
R llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/basic-instructions.s
R llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/bf16-instructions.s
R llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/complxnum-instructions.s
R llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/fp16fml-instructions.s
R llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/fptoint-instructions.s
R llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/i8mm-instructions.s
R llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/mte-instructions.s
R llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/neon-instructions.s
R llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/rcpc-immo-instructions.s
R llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/sve-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-bf16-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-complxnum-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-fp16fml-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-fptoint-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-i8mm-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-mte-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-rcpc-immo-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-bf16-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-complxnum-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-fp16fml-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-fptoint-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-i8mm-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-mte-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-rcpc-immo-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-bf16-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-complxnum-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-fp16fml-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-i8mm-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-rcpc-immo-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-bf16-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-complxnum-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-fp16fml-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-fptoint-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-i8mm-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-mte-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-rcpc-immo-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-sve-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-bf16-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-complxnum-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-fp16fml-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-fptoint-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-i8mm-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-mte-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-rcpc-immo-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-sve-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-bf16-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-complxnum-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-fp16fml-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-fptoint-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-i8mm-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-rcpc-immo-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-sve-instructions.s
Log Message:
-----------
[NFC][AArch64] Refactor Arm llvm-mca tests (#183294)
This patch refactors the llvm-mca tests for AArch64 targets
which make use of the shared "Neoverse/Inputs" directory. For the
sake of making scaling easier, the "Inputs" directory is now on the
toplevel at llvm-mca/AArch64 and all tests referencing this directory
are rewritten to use the new path.
Commit: 6ee48f2ce747c4c9a5371a5746176fd52373de96
https://github.com/llvm/llvm-project/commit/6ee48f2ce747c4c9a5371a5746176fd52373de96
Author: Luke Lau <luke at igalia.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
Log Message:
-----------
[RISCV] Remove VL != 1 restriction in RISCVVLOptimizer (#184298)
This was added way back in #112228 when the VLs were reduced in-situ,
and returning false in isSupportedInstr could trim the number of
instructions processed.
However after #124530 the demanded VLs are all computed beforehand as an
analysis so this is no longer an optimization.
This also removes the diff in rvv-peephole-vmerge-vops.ll in #184297
Commit: 263a22e8655664e8b05e212114887ad7d06c67e5
https://github.com/llvm/llvm-project/commit/263a22e8655664e8b05e212114887ad7d06c67e5
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
A mlir/test/Dialect/XeGPU/xegpu-propagate-layout-invalid.mlir
Log Message:
-----------
[mlir][xegpu] Fix crash in XeGPUPropagateLayout when module has llvm.func (#183899)
updateFunctionOpInterface() called
funcOp.setType(FunctionType::get(...)) on every FunctionOpInterface
operation, including llvm.func. However, llvm.func stores its type as
LLVMFunctionType, not the standard FunctionType. Calling
setType(FunctionType{}) on it corrupts the function_type attribute, and
the next call to getFunctionType() (which tries to
cast<LLVMFunctionType> the stored attribute) aborts.
Fix by skipping functions whose type is not a standard FunctionType.
XeGPU layout propagation only applies to functions using MLIR's
FunctionType; other function types (like LLVMFunctionType) are not
expected to carry XeGPU layouts.
Fixes #177846
Fixes #177777
Fixes #181970
Commit: ecec7920c636082708b80d6a603e8d5d7eb5b0a7
https://github.com/llvm/llvm-project/commit/ecec7920c636082708b80d6a603e8d5d7eb5b0a7
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/Func/IR/FuncOps.td
M mlir/lib/Dialect/Func/IR/FuncOps.cpp
M mlir/test/Conversion/FuncToLLVM/func-memref-return.mlir
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm-32b.mlir
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
M mlir/test/Dialect/EmitC/invalid_types.mlir
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/nvvm.mlir
M mlir/test/Dialect/Linalg/invalid.mlir
M mlir/test/Dialect/NVGPU/invalid.mlir
M mlir/test/Dialect/SparseTensor/invalid.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Vector/invalid.mlir
M mlir/test/Transforms/print-op-graph.mlir
M mlir/test/Transforms/test-dialect-conversion-pdll.mlir
M mlir/test/Transforms/test-legalizer.mlir
M mlir/test/Transforms/test-merge-blocks.mlir
M mlir/test/Transforms/test-pattern-selective-replacement.mlir
Log Message:
-----------
[mlir][func] Move return-type verification from ReturnOp to FuncOp (#184153)
Move the operand count and type checks for func.return from
ReturnOp::verify() into a new FuncOp::verify(). The verifier iterates
all blocks in the callable region, skipping terminators that are not
func.return (e.g. llvm.return or test.return that may appear during
dialect conversion).
Fix several invalid-IR tests that had func.func return types
inconsistent with the actual func.return operands. Previously these
mismatches were silent because block verification stopped at an earlier
expected error before reaching the func.return; now that
FuncOp::verify() runs before body verification, the return types must be
consistent.
Commit: 7856e98768087e0381b2f700bed544324ecd0984
https://github.com/llvm/llvm-project/commit/7856e98768087e0381b2f700bed544324ecd0984
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/uArch/IntelGpuXe2.h
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToWiDistributeExperimental.cpp
A mlir/test/Dialect/XeGPU/xegpu-subgroup-distribute-no-arch.mlir
Log Message:
-----------
[mlir][XeGPU] Fix crash in getUArch when no chip target attribute is set (#183912)
When running --xegpu-subgroup-distribute (or --xegpu-propagate-layout)
on a gpu.func that lacks a chip target attribute, getChipStr() returns
std::nullopt and the callers pass an empty string to getUArch(). This
function used llvm_unreachable for unrecognised architecture names,
causing an immediate abort instead of gracefully skipping the operation.
Fix by:
1. Changing getUArch() to return nullptr for unknown arch names instead
of calling llvm_unreachable.
2. Adding null-pointer guards to all callers in XeGPUPropagateLayout.cpp
that were missing them. The callers in XeGPUSubgroupDistribute.cpp
already had null checks but they were unreachable due to the unreachable
call.
Add a regression test that runs --xegpu-subgroup-distribute on a
gpu.func without any chip attribute and verifies it no longer crashes.
Fixes #181531
Fixes #179167
Commit: a8a5242bb2dc2949e148e7000230d479be321def
https://github.com/llvm/llvm-project/commit/a8a5242bb2dc2949e148e7000230d479be321def
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
Log Message:
-----------
[mlir][XeGPU] Fix crash in wg-to-sg type converter on non-XeGPU tensors (#183914)
The SCF structural type conversion in XeGPUWgToSgDistributePass
registered a RankedTensorType conversion callback that unconditionally
called VectorType::get() on the tensor's shape. If the tensor had
dynamic dimensions (e.g. tensor<?xi32>) and no XeGPU layout encoding,
getSgShapeAndCount() returned the original shape intact (including the
kDynamic sentinel value), causing VectorType::get() to abort because
VectorType does not support dynamic sizes.
Fix by checking whether the RankedTensorType carries an XeGPU LayoutAttr
encoding before attempting the conversion. Plain tensors without such an
encoding are left unchanged (std::nullopt causes the passthrough
converter to handle them).
Add a regression test for the no-encoding / dynamic-tensor case.
Fixes #182999
Commit: bbd5b1d3bd073c239b36359932c3049b0d5c83bd
https://github.com/llvm/llvm-project/commit/bbd5b1d3bd073c239b36359932c3049b0d5c83bd
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
M mlir/test/Conversion/VectorToXeGPU/store-to-xegpu.mlir
Log Message:
-----------
[mlir][VectorToXeGPU] Fix crash on memref with non-scalar element type (#183905)
The vector.store and vector.load lowering in --convert-vector-to-xegpu
would crash when the source memref had a non-integer/float element type
(e.g. memref<?xvector<4xf32>>).
The crash occurred inside createNdDescriptor() when computing the byte
offset for dynamic memrefs: srcTy.getElementTypeBitWidth() internally
calls getIntOrFloatBitWidth() which asserts on non-scalar types such as
vector<4xf32>.
Fix by adding a check for the memref's element type in
storeLoadPreconditions(). If the element type is not an integer or
float, the pattern returns notifyMatchFailure() instead of proceeding
and crashing.
The same guard is applied to TransferReadLowering and
TransferWriteLowering which share the same helper and can hit the same
path.
Fixes #181463
Commit: 8d082c7c3144c0a635031387bf7bf6d60960ab9e
https://github.com/llvm/llvm-project/commit/8d082c7c3144c0a635031387bf7bf6d60960ab9e
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenUtils.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenUtils.h
A mlir/test/Dialect/SparseTensor/conversion_invalid.mlir
Log Message:
-----------
[mlir][sparse] Fix crash in sparse_tensor.new with unsupported element type (#183898)
sparse_tensor.new with an element type not supported by the sparse
tensor runtime library (e.g. `index`) would call primaryTypeEncoding(),
which hits an llvm_unreachable("Unknown primary type"). The runtime
library only supports fixed-width types (f64/f32/f16/bf16,
i64/i32/i16/i8, and complex<f32/f64>); platform-dependent types such as
`index` have no corresponding PrimaryType encoding.
Fix by adding an isValidPrimaryType() helper and checking it in
SparseTensorNewConverter::matchAndRewrite() before calling genReader(),
so the conversion fails gracefully instead of crashing.
Fixes #180310
Commit: 6884ff014277bed5b09cd6fb794fed53b09dce37
https://github.com/llvm/llvm-project/commit/6884ff014277bed5b09cd6fb794fed53b09dce37
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp
A mlir/test/Dialect/SparseTensor/sparse_foreach_rank0.mlir
Log Message:
-----------
[mlir][sparse] Fix crash in ForeachRewriter for rank-0 dense tensors (#183903)
sparse_tensor.foreach over a rank-0 (scalar) dense tensor crashed
because ForeachRewriter delegated entirely to LoopEmitter, which builds
one loop level per tensor dimension. For rank-0 tensors no loops are
created, so getValPosits() called std::vector::back() on an empty
container.
Add a rank-0 early-return path in ForeachRewriter::matchAndRewrite that
handles dense scalar tensors directly: bufferize the input to a rank-0
memref, load the single element with empty indices, then inline the body
block exactly once. Reduction block-argument values in the yield are
remapped to their post-inline equivalents before the block is inlined to
avoid dangling references.
Sparse rank-0 tensors are left as a notifyMatchFailure (genuinely
unsupported, no crash).
Fixes #177856
Commit: f934db36aa2606054b3e73af7258df3fd8ccdb64
https://github.com/llvm/llvm-project/commit/f934db36aa2606054b3e73af7258df3fd8ccdb64
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
M mlir/test/Dialect/SparseTensor/invalid_encoding.mlir
Log Message:
-----------
[mlir][sparse] Reject dense level after non-unique level in encoding verifier (#184157)
The sparse tensor iteration model for dense levels requires exactly one
parent position to linearize into a contiguous range. However, when a
non-unique level (e.g. compressed(nonunique)) precedes a dense level,
the DedupIterator provides a two-element cursor {posLo, segHi}, causing
DenseLevel::peekRangeAt to assert and crash with:
Assertion `parentPos.size() == 1 && "Dense level can not be
non-unique."'
Fix this by adding a check in SparseTensorEncodingAttr::verify that
rejects any encoding where a dense level directly follows a non-unique
level, emitting a proper diagnostic instead of crashing during lowering.
Fixes #130008
Commit: ee8259dcca82849735225c8ea1b215ed7fef7648
https://github.com/llvm/llvm-project/commit/ee8259dcca82849735225c8ea1b215ed7fef7648
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/lib/Dialect/SparseTensor/Transforms/SparseSpaceCollapse.cpp
M mlir/test/Dialect/SparseTensor/sparse_space_collapse.mlir
Log Message:
-----------
[mlir][sparse] Fix use-after-free crash in SparseSpaceCollapsePass (#184001)
The `SparseSpaceCollapsePass::runOnOperation()` was calling
`collapseSparseSpace()` inside the `func->walk(...)` callback. The
collapse erases the outer `IterateOp` (and all its nested ops including
inner `ExtractIterSpaceOp`s), while the walk iterator still holds a
reference to one of those nested ops as its current position. The walk
then tries to advance to the next op, which has already been freed,
causing a segfault.
Fix this by collecting all collapsable groups during the walk without
mutating the IR, then processing them after the walk completes.
Fixes #130021
Commit: a368bd4049db226f093a688b15153a3a6bfb2ee9
https://github.com/llvm/llvm-project/commit/a368bd4049db226f093a688b15153a3a6bfb2ee9
Author: sweiglbosker <stefan at s00.xyz>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
A clang/test/CIR/CodeGenCUDA/kernel-args.cu
Log Message:
-----------
[CIR][CUDA]: Handle duplicate mangled names (#183976)
Replace the NYI for duplicate function defs with the proper diagnostic
logic from OG codegen.
Related: #175871, #179278
Commit: ec7f3503f8d0a927d166b1c608b94e9cae3b0a86
https://github.com/llvm/llvm-project/commit/ec7f3503f8d0a927d166b1c608b94e9cae3b0a86
Author: sweiglbosker <stefan at s00.xyz>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/test/Interfaces/LoopLikeInterface/test-block-loop.mlir
M mlir/test/lib/Interfaces/LoopLikeInterface/TestBlockInLoop.cpp
Log Message:
-----------
[MLIR] Make test-block-is-in-loop pass a module pass (#184036)
This pass can't run in parallel on function as it would trigger race conditions.
Fixes #183999
Commit: d908184487b9d99b249d4238453e91203492888a
https://github.com/llvm/llvm-project/commit/d908184487b9d99b249d4238453e91203492888a
Author: David Green <david.green at arm.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
Log Message:
-----------
[AArch64] Limit support to f32 and f64 in performSelectCombine (#184315)
This prevents a crash with fp128 types, other types (f16) were already
excluded.
Fixes #184300
Commit: 703649554da8f7b92873d21da7f3c51fbc7112ed
https://github.com/llvm/llvm-project/commit/703649554da8f7b92873d21da7f3c51fbc7112ed
Author: Shekhar <95859857+levi42x at users.noreply.github.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/X86/known-never-zero.ll
Log Message:
-----------
[DAG] isKnownNeverZero - add ISD::OR DemandedElts handling (#183228)
This patch updates `SelectionDAG::isKnownNeverZero` to support `ISD::OR`
by forwarding the `DemandedElts` mask to its operands.
Previously, `ISD::OR` dropped the mask, causing the compiler to be
overly conservative if any lane in the vector was zero, even if that
lane wasn't demanded. This change allows the compiler to prove a vector
result is non-zero even if ignored lanes are zero.
Fixes #183037
**Tests:**
- Moved tests from the C++ file to the IR assembly file
(`known-never-zero.ll`) as requested.
- Confirmed the code now correctly tracks which parts of a vector are
actually needed for `ISD::OR`.
- This allows the compiler to prove a result is "never zero" even if
some unused lanes contain zeros.
Commit: fa6eef837831ee6744e6baf0398104f374070470
https://github.com/llvm/llvm-project/commit/fa6eef837831ee6744e6baf0398104f374070470
Author: Lewis Crawford <lcrawford at nvidia.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll
M llvm/test/CodeGen/ARM/fminmax-folds.ll
M llvm/test/CodeGen/X86/fmaxnum.ll
M llvm/test/CodeGen/X86/fminnum.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
M llvm/test/Transforms/InstSimplify/ConstProp/min-max.ll
M llvm/test/Transforms/InstSimplify/fminmax-folds.ll
Log Message:
-----------
Revert "Avoid maxnum(sNaN, x) optimizations / folds (#170181)" (#184125)
This reverts commit ea3fdc5972db7f2d459e543307af05c357f2be26.
Re-enable const-folding for maxnum/minnum in the middle-end, GlobalISel,
and SelectionDAG.
Re-enable optimizations that depend on maxnum/minnum sNaN semantics in
InstCombine and DAGCombiner.
Now that maxnum(x, sNaN) is specified to non-deterministically produce
either NaN or x, these constant-foldings and optimizations are now valid
again according to the newly clarified semantics in #172012 .
Commit: de69348f80f5498c5a42e6fd347ba18239c498a5
https://github.com/llvm/llvm-project/commit/de69348f80f5498c5a42e6fd347ba18239c498a5
Author: Maria Fernanda Guimarães <66797940+mafeguimaraes at users.noreply.github.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/include/clang/APINotes/APINotesReader.h
M clang/lib/APINotes/APINotesManager.cpp
M clang/lib/APINotes/APINotesReader.cpp
Log Message:
-----------
[Reland] [APINotes] Refactor APINotesReader to propagate llvm::Error (#184212)
Reland of #183812 with the explicit `std::move` restored to fix buildbot
failures on older compilers.
Commit: 97043e50ad41c9da94a5cb48417f5139d6a84c8d
https://github.com/llvm/llvm-project/commit/97043e50ad41c9da94a5cb48417f5139d6a84c8d
Author: Artem Gindinson <gindinson at roofline.ai>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorDistribute.cpp
M mlir/test/Dialect/Vector/vector-warp-distribute.mlir
Log Message:
-----------
[mlir][Vector][GPU] Distribute expanding `shape_cast` ops (#183830)
The initial implementation of `shape_cast` distribution only focused on
scenarios with collapsing shape casts. Within downstream pipelines such
as IREE, commit 962a9a3 exposes an issue with this implementation, where
the rank-expanding cast ops (stemming from the new `vector.broadcast`
canonicalization) silently fall through to the "collapsing-or-no-op"
logic. This brings about bugs with rank mismatches and firing validation
assertions when distributing rather common reshaping sequences
encountered after CSE/ canonicalization, such as below:
```
// Example 1: gather op
%weight = arith.constant dense_resource<__elided__> : tensor<256xi8>
%c0 = arith.constant 0 : index
...
%expand = vector.shape_cast <...> : vector<1xindex> to vector<1x1xindex>
%gather = vector.gather %weight[%c0] [%expand], <...>, <...> : memref<256xi8>, vector<1x1xindex>, vector<1x1xi1>, vector<1x1xi8> into vector<1x1xi8>
%collapse_back = vector.shape_cast %gather : vector<1x1xi8> to vector<1xi8>
// Example 2: multi-reduction
%expand = vector.shape_cast <...>: vector<1x96xi32> to vector<1x2x48xi32>
%reduce = vector.multi_reduction <add>, %expand, <...> [1, 2]: vector<1x2x48xi32> to vector<1x1xi32>
%collapse = vector.shape_cast %reduce : vector<1x1xi32> to vector<1xi32>
```
This commit adds initial handling of expanding `shape_cast`s, going
through the three scenarios:
- if all "excess" dimensions in the front of the destination shape are
unit, it's clear that the work is not distributed across those, so we
strip the same number of unit dimensions from the per-lane yielded type;
- if the source type within the warp code is of rank 1, we still
determine the corresponding output type cleanly by multiplying the
dimensions of the per-lane yield type;
- if neither of the above are true, explicitly fail the pattern for such
expanding `shape_cast`'s. Dimension-specific distribution parameters are
deemed ambiguous, at least from within this pattern's context.
---------
Signed-off-by: Artem Gindinson <gindinson at roofline.ai>
Commit: 534d6e887ff815cdba5f9e2784b6b432faac25c1
https://github.com/llvm/llvm-project/commit/534d6e887ff815cdba5f9e2784b6b432faac25c1
Author: Alexis Engelke <engelke at in.tum.de>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h
Log Message:
-----------
[Analysis][NFC] Store CallbackVH in vector, not in map (#184323)
This avoid non-trivial move operations whenever the map grows.
Commit: 33864efe461e6c71545b009d1a394d2b756784f8
https://github.com/llvm/llvm-project/commit/33864efe461e6c71545b009d1a394d2b756784f8
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M lld/COFF/Driver.cpp
M lld/wasm/OutputSections.cpp
Log Message:
-----------
[lld] Turn misc copy-assign to move-assign (#184145)
That's an automated patch generated from clang-tidy
performance-use-std-move as a follow-up to #184136
Commit: 1eeb2eccf8b2397c49aaeefde61257c5be6fc905
https://github.com/llvm/llvm-project/commit/1eeb2eccf8b2397c49aaeefde61257c5be6fc905
Author: flovent <flbven at protonmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/StdNamespaceModificationCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/system-header-simulation.h
M clang-tools-extra/test/clang-tidy/checkers/bugprone/std-namespace-modification.cpp
Log Message:
-----------
[clang-tidy] Handle specialization of user-defined type in `bugprone-std-namespace-modification` (#183984)
Ignore `templateSpecializationType` based on user-define classes too.
Fixes #183752
Commit: bbde3e3b59c8f7d8eee940a5aeb4eb5a849c05f4
https://github.com/llvm/llvm-project/commit/bbde3e3b59c8f7d8eee940a5aeb4eb5a849c05f4
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
Log Message:
-----------
[VPlan] Preserve IsSingleScalar for sunken predicated stores. (#184329)
The predicated stores may be single scalar (e.g. for VF = 1). We should
preserve IsSingleScalar. As all stores access the same address,
IsSingleScalar must match across all stores in the group.
This fixes an assertion when interleaving-only with sunken stores.
Fixes https://github.com/llvm/llvm-project/issues/184317
PR: https://github.com/llvm/llvm-project/pull/184329
Commit: c782e2d40572ce4ff3a71562265bf6f01857c132
https://github.com/llvm/llvm-project/commit/c782e2d40572ce4ff3a71562265bf6f01857c132
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-service-func.ll
M llvm/test/CodeGen/SPIRV/pointers/fun-with-aggregate-arg-in-const-init.ll
Log Message:
-----------
[SPIRV] Don't emit service function basic block names (#184206)
Right now if a module has a service function we always emit `OpName
entry` for the service function's basic block.
The actual service function isn't emitted and no other instruction uses
the basic block `OpName` instruction, so don't emit it.
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: 5b976c930189e54eda134684ef4ea3682bf2ee18
https://github.com/llvm/llvm-project/commit/5b976c930189e54eda134684ef4ea3682bf2ee18
Author: Pengxiang Huang <71998072+Pengxiang-Huang at users.noreply.github.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/config/linux/x86_64/headers.txt
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/key_t.h
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-macros/CMakeLists.txt
M libc/include/llvm-libc-macros/linux/CMakeLists.txt
A libc/include/llvm-libc-macros/linux/sys-ipc-macros.h
A libc/include/llvm-libc-macros/sys-ipc-macros.h
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/key_t.h
A libc/include/llvm-libc-types/struct_ipc_perm.h
A libc/include/sys/ipc.yaml
M libc/include/sys/types.yaml
M libc/src/sys/CMakeLists.txt
A libc/src/sys/ipc/CMakeLists.txt
A libc/src/sys/ipc/ftok.h
A libc/src/sys/ipc/linux/CMakeLists.txt
A libc/src/sys/ipc/linux/ftok.cpp
A libc/src/sys/ipc/linux/kernel_statx.h
M libc/test/src/sys/CMakeLists.txt
A libc/test/src/sys/ipc/CMakeLists.txt
A libc/test/src/sys/ipc/linux/CMakeLists.txt
A libc/test/src/sys/ipc/linux/ftok_test.cpp
Log Message:
-----------
[libc][sys] add header and functions for sys ipc (#182700)
Split from a larger change. This PR contains the base impl for sys ipc,
sys sem will come after this. @SchrodingerZhu
this PR implements for:
https://github.com/llvm/llvm-project/issues/182161
see the last PR for more detail:
https://github.com/llvm/llvm-project/pull/182683
Commit: c9d065abc15846deb95a23fb0b3e1855d3d26314
https://github.com/llvm/llvm-project/commit/c9d065abc15846deb95a23fb0b3e1855d3d26314
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
A llvm/test/CodeGen/X86/funnel-shift-i256.ll
M llvm/test/CodeGen/X86/shift-i256.ll
Log Message:
-----------
[X86] Add i256 shift / funnel shift coverage to match i512 tests (#184346)
shift-i256.ll - added x86-64/x86-64-v2/x86-64-v3/x86-64-v4 coverage and retained the x86 test coverage
Commit: acb8a6df19919cf2fa9946b88f5b14c28aa4f7ef
https://github.com/llvm/llvm-project/commit/acb8a6df19919cf2fa9946b88f5b14c28aa4f7ef
Author: Lukacma <Marian.Lukac at arm.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
A llvm/test/CodeGen/AArch64/neon-extractbitcast-mir.ll
Log Message:
-----------
[AArch64] Fix type mismatch in bitconvert + vec_extract patterns (#183549)
This patch fixes mismatch in element width during isel of bitconvert +
vec_extract nodes. This resolves issue reported on
[this](https://github.com/llvm/llvm-project/pull/172837) PR.
Commit: e570faa87ed3afb21504d06d0c22d82686f3a8e3
https://github.com/llvm/llvm-project/commit/e570faa87ed3afb21504d06d0c22d82686f3a8e3
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/test/Driver/hip-toolchain-no-rdc.hip
M clang/test/Driver/spirv-amd-toolchain.c
Log Message:
-----------
[SPIR-V][HIP] Disable SPV_KHR_untyped_pointers (#183530)
SPV_KHR_untyped_pointers in SPIR-V to LLVM translator is incomplete with
few known issues. Therefore we better not to rely on this extension for SPIR-V
generation.
Commit: 81396ebc51c40214465111ede745147989c67e48
https://github.com/llvm/llvm-project/commit/81396ebc51c40214465111ede745147989c67e48
Author: LU-JOHN <John.Lu at amd.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
Log Message:
-----------
[AMDGPU] Generate more swaps (#184164)
Generate more swaps from:
```
mov T, X
...
mov X, Y
...
mov Y, X
```
by being more careful about what use/defs of X, Y, T are allowed in
intervening code and allowing flexibility where the swap is inserted.
---------
Signed-off-by: John Lu <John.Lu at amd.com>
Commit: 43503c44c8d0d9ec6948c21e5ff79e2ec7babad1
https://github.com/llvm/llvm-project/commit/43503c44c8d0d9ec6948c21e5ff79e2ec7babad1
Author: SiliconA-Z <gfunni234 at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
Log Message:
-----------
[NFC][AArch64] isPureCmp is a duplicate of canAdjustCmp, so remove the duplicate (#183568)
Just delete the duplicate function.
Commit: e10655eb1dfc5e40387b6389715100a62ba9f806
https://github.com/llvm/llvm-project/commit/e10655eb1dfc5e40387b6389715100a62ba9f806
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/test/CodeGen/X86/known-never-zero.ll
Log Message:
-----------
[X86] known-never-zero.ll - add sdiv/udiv vector test coverage for #183047 (#184350)
Commit: 358f4777202395e19c17f0c4c57a55234ffc37df
https://github.com/llvm/llvm-project/commit/358f4777202395e19c17f0c4c57a55234ffc37df
Author: Shivam Gupta <shivam98.tkg at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/lib/CodeGen/CGStmtOpenMP.cpp
A clang/test/OpenMP/for_range_loop_codegen.cpp
M clang/test/OpenMP/parallel_for_codegen.cpp
Log Message:
-----------
[Clang] Fix clang crash for fopenmp statement(for) inside lambda function (#146772)
C++ range-for statements introduce implicit variables such as `__range`,
`__begin`, and `__end`. When such a loop appears inside an OpenMP
loop-based directive (e.g. `#pragma omp for`) within a lambda, these
implicit variables were not emitted before OpenMP privatization logic
ran.
OMPLoopScope assumes that loop-related variables are already present in
LocalDeclMap and temporarily overrides their addresses. Since the
range-for implicit variables had not yet been emitted, they were treated
as newly introduced entries and later erased during restore(), leading
to missing mappings and a crash during codegen.
Fix this by emitting the range-for implicit variables before OpenMP
privatization (setVarAddr/apply), ensuring that existing mappings are
correctly overridden and restored.
This fixes #146335
Commit: 02b2a1e8fe7f553e49b6dff9ee9b2ba160eea9cb
https://github.com/llvm/llvm-project/commit/02b2a1e8fe7f553e49b6dff9ee9b2ba160eea9cb
Author: Shoreshen <372660931 at qq.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp
Log Message:
-----------
Fix `assignValueToReg` function's argument (#184354)
Because of [PR#178198](https://github.com/llvm/llvm-project/pull/178198)
the argument changes for `assignValueToReg`.
This PR aiming at fixing M86k experimental target
Commit: aef962708fe52372debf0ee3773462d5765a6069
https://github.com/llvm/llvm-project/commit/aef962708fe52372debf0ee3773462d5765a6069
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVBaseInfo.h
M llvm/lib/Target/SPIRV/SPIRVAPI.cpp
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVCommandLine.h
M llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
M llvm/lib/Target/SPIRV/SPIRVSubtarget.h
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
Log Message:
-----------
Reapply "[SPIRV][NFCI] Use unordered data structures for SPIR-V extensions (#184162)
Reapply https://github.com/llvm/llvm-project/pull/183567 with minor
changes.
Problem causing the revert was we couldn't use the enum in `DenseMap`
directly because of some `TableGen` limitations so I casted made the map
use the underlying type, but that caused some UB, so I
[fixed](https://github.com/llvm/llvm-project/pull/183769) the `TableGen`
limitation so now it just works.
Commit: d61b45cd409d6def96eae8977bab2b0393c96b7e
https://github.com/llvm/llvm-project/commit/d61b45cd409d6def96eae8977bab2b0393c96b7e
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/lib/CodeGen/CGAtomic.cpp
M clang/test/CodeGen/atomic-arm64.c
M clang/test/CodeGen/atomic-ops.c
M clang/test/CodeGen/big-atomic-ops.c
M clang/test/CodeGenOpenCL/atomic-ops.cl
Log Message:
-----------
[Clang] Generate ptr and float atomics without integer casts (#183853)
Summary:
LLVM IR should support these for all cases except for compare-exchange.
Currently the code goes through an integer indirection for these cases.
This PR changes the behavior to use atomics directly to the target
memory type.
Commit: 6cc42b39556d33a968a899fd3243bcb707ae7169
https://github.com/llvm/llvm-project/commit/6cc42b39556d33a968a899fd3243bcb707ae7169
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M libc/src/__support/GPU/allocator.cpp
Log Message:
-----------
[libc] Various GPU allocator tweaks and optimizations (#184368)
Summary:
Some low-hanging fruit tweaks. Mostly preventing redundant loads and
unnecessary widening. Some fixes as well, like nullptr handling,
incorrect rounding, and oversized bitfields.
Commit: e68f696fdae0ce2ae1a0260a7414fbba50430018
https://github.com/llvm/llvm-project/commit/e68f696fdae0ce2ae1a0260a7414fbba50430018
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M .github/workflows/spirv-tests.yml
Log Message:
-----------
[CI][SPIRV][NFC] Remove unneccessary mkdir from workflow (#184353)
The `CMake` command does the `mkdir` automatically.
Pointed out in https://github.com/llvm/llvm-project/pull/184174
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: 3f1d968db946e90c7e29bfa886566957f0e374f4
https://github.com/llvm/llvm-project/commit/3f1d968db946e90c7e29bfa886566957f0e374f4
Author: Matthias Springer <me at m-sp.org>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/include/mlir/IR/Operation.h
M mlir/include/mlir/IR/Region.h
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenACC/Transforms/LegalizeDataValues.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtils.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenUtils.cpp
Log Message:
-----------
[mlir][IR] Add variadic `getParentOfType` overloads (#184071)
Add `getParentOfType` overloads that work with multiple types.
Commit: f82f8cf8d498ea5dc0b20e2cead112d6d2b85894
https://github.com/llvm/llvm-project/commit/f82f8cf8d498ea5dc0b20e2cead112d6d2b85894
Author: Fangrui Song <i at maskray.me>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/PPC.cpp
M lld/ELF/Arch/PPC64.cpp
M lld/ELF/Arch/X86.cpp
M lld/ELF/Arch/X86_64.cpp
M lld/ELF/Config.h
M lld/ELF/SyntheticSections.cpp
M lld/ELF/Target.h
Log Message:
-----------
[ELF] Add TargetInfo::initTargetSpecificSections hook (#184292)
so that we can move target-specific synthetic section creation from
createSyntheticSections into per-target initTargetSpecificSections
overrides. This reduces target-specific code in the shared
SyntheticSections.cpp. The subsequent commits (split from
https://github.com/llvm/llvm-project/pull/184057) will move these
target-specific classes to Arch/ files.
Commit: 5f8f1e2afe991cd214bff9b3cb68612f594e8596
https://github.com/llvm/llvm-project/commit/5f8f1e2afe991cd214bff9b3cb68612f594e8596
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp
M clang/test/CIR/Transforms/flatten-try-op.cir
Log Message:
-----------
[CIR] Fix unreachable block generation in EH flattening (#184268)
The previous EH CFG flattening implementation would sometimes create
dispatch handlers in unreachable blocks. This seemed OK until I started
implementing the code to lower the flattened CIR to an ABI-specific form
and those weren't getting updated.
This change fixes the flattening code to avoid generating unreachable
blocks.
Commit: a232b5b96f67b395f52d44cf0e02c52ec658ff40
https://github.com/llvm/llvm-project/commit/a232b5b96f67b395f52d44cf0e02c52ec658ff40
Author: Frank Schlimbach <frank.schlimbach at intel.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/MPI/IR/MPIOps.td
M mlir/include/mlir/Dialect/Shard/IR/ShardOps.td
M mlir/include/mlir/Dialect/Shard/Transforms/Partition.h
M mlir/include/mlir/Dialect/Shard/Transforms/Passes.td
R mlir/include/mlir/Dialect/Shard/Transforms/Simplifications.h
A mlir/include/mlir/Dialect/Shard/Transforms/Simplify.h
M mlir/lib/Conversion/MPIToLLVM/MPIToLLVM.cpp
M mlir/lib/Conversion/ShardToMPI/ShardToMPI.cpp
M mlir/lib/Dialect/MPI/IR/MPIOps.cpp
M mlir/lib/Dialect/Shard/IR/ShardOps.cpp
M mlir/lib/Dialect/Shard/Transforms/CMakeLists.txt
R mlir/lib/Dialect/Shard/Transforms/Simplifications.cpp
A mlir/lib/Dialect/Shard/Transforms/Simplify.cpp
M mlir/test/Conversion/MPIToLLVM/mpitollvm.mlir
M mlir/test/Conversion/ShardToMPI/convert-shard-to-mpi.mlir
M mlir/test/Dialect/MPI/mpiops.mlir
M mlir/test/Dialect/Shard/all-scatter-op-lowering.mlir
M mlir/test/Dialect/Shard/canonicalization.mlir
M mlir/test/Dialect/Shard/folding.mlir
M mlir/test/Dialect/Shard/invalid.mlir
M mlir/test/Dialect/Shard/ops.mlir
R mlir/test/Dialect/Shard/simplifications.mlir
A mlir/test/Dialect/Shard/simplify.mlir
M mlir/test/lib/Dialect/Shard/CMakeLists.txt
M mlir/test/lib/Dialect/Shard/TestReshardingPartition.cpp
R mlir/test/lib/Dialect/Shard/TestSimplifications.cpp
M mlir/tools/mlir-opt/mlir-opt.cpp
Log Message:
-----------
[mlir][shard, mpi] Adding Shard/MPI reduce_scatter and simplification (#184189)
- introduces a simplify pass, which finds such patterns and replaces it
with the equivalent `reduce-scatter`
- promotes the test-pass `test-shard-optimizations` to a proper pass and adds
- folding allgather+allslice into reduce_scatter
- sanitizes the `shard.reduce_scatter` op
- adds a new `mpi.reduce_scatter_block` op
- lowers `shard.reduce_scatter` to MPI
- lowers `mpi-reduce_scatter_block` to llvm
---------
Co-authored-by: Copilot <175728472+Copilot at users.noreply.github.com>
Commit: 829da4927bf19c398c3685a8a75d4ccf57269877
https://github.com/llvm/llvm-project/commit/829da4927bf19c398c3685a8a75d4ccf57269877
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
Log Message:
-----------
[CIR][AArch64] Add lowering for vaba_* and vabd_* builtins (#183595)
Add CIR lowering for the following AdvSIMD (NEON) intrinsic groups:
* vabd_* – Absolute difference
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#absolute-difference
* vaba_* – Absolute difference and accumulate
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#absolute-difference-and-accumulate
Tests for these intrinsics were split out from:
* "test/CodeGen/AArch64/neon-intrinsics.c"
and moved to:
* "test/CodeGen/AArch64/neon/intrinsics.c".
The following helper hooks were adapted from the ClangIR project:
* `getNeonType`, `emitNeonCall`, `emitNeonCallToOp`.
Credit to the ClangIR contributors for the original implementation.
Commit: bb2b957c53b0d000d49f83e5cb95bcd8172bf860
https://github.com/llvm/llvm-project/commit/bb2b957c53b0d000d49f83e5cb95bcd8172bf860
Author: walkerkd <keith.walker at arm.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMInstrThumb2.td
A llvm/test/CodeGen/Thumb2/pacbti-m-bxaut.ll
Log Message:
-----------
[Thumb2] Use BXAUT instruction if available (#183056)
Generated a
bxaut r12, lr, sp
instruction rather than
aut r12, lr, sp
bx lr
The bxaut instruction is available when for thumb2 code with the
armv8.1m-main architecture and PACBTI is enabled
This change introduces a new pseudo instruction ARM::t2BXAUT_RET which
is similar to the existing pseudo instruction ARM::tBX_RET.
---------
Co-authored-by: Copilot <175728472+Copilot at users.noreply.github.com>
Commit: b44dba97d059b928f93eeccd7eac3f1e108a4082
https://github.com/llvm/llvm-project/commit/b44dba97d059b928f93eeccd7eac3f1e108a4082
Author: lanluo-nvidia <lanl at nvidia.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/CMakeLists.txt
Log Message:
-----------
[mlir] Install '.pdll' files along with the header files (#183855)
The CMake install configuration was not installing
'include/mlir/Transforms/DialectConversion.pdll`, which is required
by the installed PDLL compiler tools for interacting withthe dialect
conversion infrastructure.
Commit: 779d76c9effd22454a3af48c0a6e922af371eb66
https://github.com/llvm/llvm-project/commit/779d76c9effd22454a3af48c0a6e922af371eb66
Author: David Green <david.green at arm.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64.h
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
A llvm/lib/Target/AArch64/AArch64PassRegistry.def
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/test/CodeGen/AArch64/stp-opt-with-renaming-ld3.mir
Log Message:
-----------
[AArch64] Add basic NPM support for LoadStoreOptimizer. (#184090)
This adds what I can tell is the the basics for NPM support on LLVM, and
ports the AArch64LoadStoreOpt pass to have NPM support.
Commit: b33c7db8eb630384d40acbd753f5bfbc80d0d2f0
https://github.com/llvm/llvm-project/commit/b33c7db8eb630384d40acbd753f5bfbc80d0d2f0
Author: Paul Kirth <paulkirth at google.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang-tools-extra/clang-doc/CMakeLists.txt
A clang-tools-extra/clang-doc/benchmarks/CMakeLists.txt
A clang-tools-extra/clang-doc/benchmarks/ClangDocBenchmark.cpp
Log Message:
-----------
[clang-doc] Add basic benchmarks for library functionality (#182620)
clang-doc's performance is good, but we suspect it could be better. To
track this with more fidelity, we can add a set of GoogleBenchmarks that
exercise portions of the library. To start we try to track high level
items that we monitor via the TimeTrace functions, and give them their
own micro benchmarks. This should give us more confidence that switching
out data structures or updating algorthms will have a positive
performance impact.
Note that an LLM helped generate portions of the benchmarks and
parameterize them. Most of the internal logic was written by me, but
the LLM was used to handle boilerplate and adaptation to the harness.
Commit: 640ba7b05e753d527d238eb6592dca20dbcd4686
https://github.com/llvm/llvm-project/commit/640ba7b05e753d527d238eb6592dca20dbcd4686
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M .github/workflows/containers/github-action-ci-tooling/Dockerfile
Log Message:
-----------
[Github] Bump clang-format/clang-tidy to v22.1.0 (#184374)
Per the version policy for these tools to bump them at the beginning of
the release cycle and at the end of the release cycle.
Commit: 9081ac255a8b82c78c3a8c5a3db4f72ecca21cba
https://github.com/llvm/llvm-project/commit/9081ac255a8b82c78c3a8c5a3db4f72ecca21cba
Author: Finn Plummer <mail at inbelic.dev>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/DirectX/DXILResourceAccess.cpp
A llvm/test/CodeGen/DirectX/ResourceAccess/handle-cases.ll
A llvm/test/CodeGen/DirectX/ResourceAccess/handle-to-index.ll
A llvm/test/CodeGen/DirectX/ResourceAccess/non-unique.ll
Log Message:
-----------
[DirectX][ResourceAccess] Resolve resource handles at access (#182106)
This change resolves handles (or corresponding ptr) that all point into
a unique global resource by propagating an index into that global
resource through control flow.
If a unique global resource can't be resolved, an error is reported
instead.
This specifically resolves all handles that point into the same global
resource array.
Resolves: https://github.com/llvm/llvm-project/issues/165288
By reporting an error, this is part of resolving
https://github.com/llvm/llvm-project/issues/179303.
Commit: b6f389e005d7cf4bc0df0c594cd65d625a96ad01
https://github.com/llvm/llvm-project/commit/b6f389e005d7cf4bc0df0c594cd65d625a96ad01
Author: Paul Kirth <paulkirth at google.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang-tools-extra/clang-doc/Generators.cpp
M clang-tools-extra/clang-doc/JSONGenerator.cpp
M clang-tools-extra/clang-doc/MDGenerator.cpp
M clang-tools-extra/clang-doc/Representation.cpp
M clang-tools-extra/clang-doc/Representation.h
M clang-tools-extra/clang-doc/YAMLGenerator.cpp
M clang-tools-extra/unittests/clang-doc/ClangDocTest.cpp
M clang-tools-extra/unittests/clang-doc/GeneratorTest.cpp
Log Message:
-----------
[clang-doc] Improve complexity of Index construction (#182621)
The existing implementation ends up with an O(N^2) algorithm due to
repeated linear scans during index construction. Switching to a
StringMap allows us to reduce this to O(N), since we no longer need to
search the vector.
The `BM_Index_Insertion` benchmark measures the time taken to insert N
unique records into the index.
| Scale (N Items) | Baseline (ns) | Patched (ns) | Speedup | Change |
|----------------:|--------------:|-------------:|--------:|-------:|
| 10 | 9,977 | 11,004 | 0.91x | +10.3% |
| 64 | 69,249 | 69,166 | 1.00x | -0.1% |
| 512 | 1,932,714 | 525,877 | 3.68x | -72.8% |
| 4,096 | 92,411,535 | 4,589,030 | 20.1x | -95.0% |
| 10,000 | 577,384,945 | 12,998,039 | 44.4x | -97.7% |
The patch delivers significant improvements to scalability. At 10,000
items, index construction is **~44 times faster**, confirming the
complexity reduction from O(N^2) to O(N). The crossover point where the
new map-based approach beats the vector-based approach appears to be
around N=64.
Since the index is typically larger than 64 for files of non trivial
complexity, and users will typically be building documentation for an
entire project with many files, all normal usage should benefit from
this change.
Other benchmarks show minor regressions, though in a typical build of
LLVM documentation index construction takes up a larger amount of
runtime than any of these other components.
Commit: f95662d159dcf40d4cabce028b5913d8a7330ff6
https://github.com/llvm/llvm-project/commit/f95662d159dcf40d4cabce028b5913d8a7330ff6
Author: Jason Van Beusekom <jason.van-beusekom at hpe.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/include/clang/AST/ASTMutationListener.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/lib/Frontend/MultiplexConsumer.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Serialization/ASTCommon.h
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/test/OpenMP/target_indirect_codegen.cpp
R clang/test/OpenMP/target_vtable_omp_indirect_call_lookup.cpp
M offload/test/api/omp_indirect_call_table_manual.c
R offload/test/api/omp_indirect_func_array.c
R offload/test/api/omp_indirect_func_basic.c
R offload/test/api/omp_indirect_func_struct.c
R offload/test/api/omp_virtual_func.cpp
R offload/test/api/omp_virtual_func_multiple_inheritance_01.cpp
R offload/test/api/omp_virtual_func_multiple_inheritance_02.cpp
R offload/test/api/omp_virtual_func_reference.cpp
Log Message:
-----------
Revert "[OpenMP][clang] Indirect and Virtual function call mapping from host to device" (#184378)
Reverts llvm/llvm-project#159857
Commit: a8a2f2fe997692ec67e3874c7c23e6d4dc0324ff
https://github.com/llvm/llvm-project/commit/a8a2f2fe997692ec67e3874c7c23e6d4dc0324ff
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/Transforms/Passes.td
M mlir/include/mlir/Dialect/XeGPU/Transforms/Transforms.h
M mlir/lib/Dialect/XeGPU/Transforms/CMakeLists.txt
R mlir/lib/Dialect/XeGPU/Transforms/XeGPUFoldAliasOps.cpp
R mlir/test/Dialect/XeGPU/xegpu-fold-alias-ops.mlir
Log Message:
-----------
[MLIR][XeGPU] Remove fold alias pass in xegpu (#182802)
Commit: 616656bc5e1ae78625f751d55817e7408526f1dd
https://github.com/llvm/llvm-project/commit/616656bc5e1ae78625f751d55817e7408526f1dd
Author: Fangrui Song <i at maskray.me>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M lld/ELF/Arch/Mips.cpp
M lld/ELF/Config.h
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
Log Message:
-----------
[ELF] Move MIPS synthetic sections into Arch/Mips.cpp (#184384)
Move MipsAbiFlagsSection, MipsOptionsSection, MipsReginfoSection, and
MipsRldMapSection from SyntheticSections.h/cpp into Arch/Mips.cpp.
The MIPS-specific section creation in createSyntheticSections is
replaced
by the initTargetSpecificSections hook.
Commit: 200600a06c20501a8380ab6c60d2158956e6214c
https://github.com/llvm/llvm-project/commit/200600a06c20501a8380ab6c60d2158956e6214c
Author: Fangrui Song <i at maskray.me>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M lld/ELF/Arch/PPC.cpp
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
Log Message:
-----------
[ELF] Move PPC32Got2Section into Arch/PPC.cpp (#184383)
Move PPC32Got2Section from SyntheticSections.h/cpp into the anonymous
namespace in Arch/PPC.cpp, renaming it to Got2Section.
Extracted from #184292. Moved initTargetSpecificSections after ctor and
before other hooks to match the linker's pass order.
Commit: 7b7c8b2eb3f1b7f12ea42a9d3ece4cb17bbf969b
https://github.com/llvm/llvm-project/commit/7b7c8b2eb3f1b7f12ea42a9d3ece4cb17bbf969b
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M libc/test/include/CMakeLists.txt
M libc/test/integration/CMakeLists.txt
M libc/utils/libctest/format.py
Log Message:
-----------
[libc] Extend check-libc-lit to cover include, integration, and all src tests (#184366)
The lit-based test runner introduced in c776a52f only discovered
libc.test.src tests with a strict __unit__.__build__ or
__hermetic__.__build__ suffix. This missed four categories of tests:
1. libc.test.include.* tests (e.g. isnan_test, signbit_test)
2. libc.test.integration.* tests (e.g. pthread, unistd, startup)
3. libc.test.src.* tests that have no __unit__/__hermetic__ marker (e.g.
errno_test, dirent_test, htonl)
4. libc.test.src.* tests with extra option suffixes between the type
marker and .__build__ (e.g. __unit__.__NO_FMA_OPT.__build__)
Wire up the two missing build dependencies so that check-libc-lit builds
include and integration tests before running them, and update
_isTestExecutable() to recognise all four patterns.
The pattern documentation was consolidated into the _isTestExecutable()
docstring, where it is next to the code it describes, to avoid the two
diverging in future.
Tested:
Compared the test count from a full `ninja check-libc` run (2765 tests)
against `llvm-lit --show-tests libc/test` after this change and
confirmed the counts match exactly.
Commit: bf680bdf13499860a552f991bb9d11b2b52b8ea8
https://github.com/llvm/llvm-project/commit/bf680bdf13499860a552f991bb9d11b2b52b8ea8
Author: Victor Chernyakin <chernyakin.victor.j at outlook.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang-tools-extra/clang-tidy/readability/RedundantTypenameCheck.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/redundant-typename.cpp
Log Message:
-----------
[clang-tidy] Fix yet another false positive in `readability-redundant-typename` (#184301)
Fixes #184083.
Commit: 7a310b4c5a069141110fda5f9beb4905482ce621
https://github.com/llvm/llvm-project/commit/7a310b4c5a069141110fda5f9beb4905482ce621
Author: Han-Chung Wang <hanhan0912 at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/TilingInterfaceImpl.cpp
M mlir/test/Interfaces/TilingInterface/lower-to-loops-using-interface.mlir
Log Message:
-----------
[mlir][linalg] Upstream PackOp/UnPackOp's generateScalarImplementation. (#182838)
The revision upstreams the implementation from IREE. The ops were
upstreamed some time ago, and they are the remaining implementation. The
core implementation is mirrored from IREE and some cleanups and style
nits are fixed.
The mirror is not a pure copy-paste because the op accessors are
different:
| IREE | llvm-project |
|------|--------------|
| `getInputRank()` | `packOp.getSourceRank()` |
| `getOutputRank()` | `packOp.getDestRank()` |
| `getInput()` | `packOp.getSource()` |
| `getOutput()` | `packOp.getDest()` |
And it uses `linalg::createOrFoldDimOp` and `createFoldedDimOp` from
upstream to create DimOp ops.
Closes https://github.com/llvm/llvm-project/pull/128816
Closes https://github.com/llvm/llvm-project/pull/178222
Co-authored-by: lorenzo chelini <l.chelini at icloud.com>
---------
Signed-off-by: hanhanW <hanhan0912 at gmail.com>
Commit: c1bba5ba023aaa1ac76f2eac76961a8b12e4e1b0
https://github.com/llvm/llvm-project/commit/c1bba5ba023aaa1ac76f2eac76961a8b12e4e1b0
Author: calebwat <107081575+calebwat at users.noreply.github.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanCFG.h
Log Message:
-----------
[VPlan][NFC] Remove unnecessary explicit copy constructors (#183863)
VPHierarchicalChildrenIterator has explicitly defined copy and copy
assignment constructors which perform the same operation as the implicit
versions would. As a result, it does not follow the rule of three style,
but also does not need a destructor. This patch avoids that by simply
removing the explicit definitions, since their functionality is the same
as the implicit ones.
Commit: b926acfb341b75fa041b84523b5286644ea0482a
https://github.com/llvm/llvm-project/commit/b926acfb341b75fa041b84523b5286644ea0482a
Author: Kelvin Li <kli at ca.ibm.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
Log Message:
-----------
[flang] remove unused variable (NFC) (#184293)
Commit: 56b5af76cf3c0d369b734c3f51011aec1c918bef
https://github.com/llvm/llvm-project/commit/56b5af76cf3c0d369b734c3f51011aec1c918bef
Author: Emmanuel Antonio <38330347+EmmanuelAC1 at users.noreply.github.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel][mlir] Fix Bazel build for a232b5b (#184394)
Co-authored-by: Pranav Kant <prka at google.com>
Commit: 7161bd94fded2d85e4af5057c4a8b9fbc4d28683
https://github.com/llvm/llvm-project/commit/7161bd94fded2d85e4af5057c4a8b9fbc4d28683
Author: Frank Schlimbach <frank.schlimbach at intel.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/lib/Conversion/MPIToLLVM/CMakeLists.txt
Log Message:
-----------
[mlir][mpi] fixing 184189 build failures (#184399)
Commit: 6b040b0dee9cb8b38e56dbcb7e51182a62703e05
https://github.com/llvm/llvm-project/commit/6b040b0dee9cb8b38e56dbcb7e51182a62703e05
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/lib/Driver/Driver.cpp
M clang/test/Driver/hip-save-temps.hip
M clang/test/Driver/hip-spirv-backend-bindings.c
M clang/test/Driver/hip-spirv-backend-phases.c
Log Message:
-----------
[HIP] Fix -save-temps with the new offload driver (#184385)
Summary:
The new offloading driver passes LLVM-IR to the linker phase. This
caused a problem with `-save-temps` passing unoptimized bitcode. We were
supposed to have dedicated handling for this, but it was not firing in
the HIP case like it is supposed to. OpenMP already supports this so
simply identify the cases that skip this support and fix it.
Commit: d0dd371249795ef17fac95dd77444baef1fdf578
https://github.com/llvm/llvm-project/commit/d0dd371249795ef17fac95dd77444baef1fdf578
Author: Alexandra Sidorova <asidorov at amd.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/canonicalize.mlir
A mlir/test/Dialect/Vector/canonicalize/vector-to-elements.mlir
Log Message:
-----------
[MLIR][Canonicalization] Add shape_cast folding patterns (#183061)
### Summary
This PR adds two shape_cast-related canonicalization patterns for
`vector.to_elements` and `vector.from_elements`.
### Details
- Added` ToElements(ShapeCast(X)) -> ToElements(X)` as an in-place fold
in `ToElementsOp::fold`.
- Added `ShapeCast(FromElements(X)) -> FromElements(X)` as an
`OpRewritePattern` — it must be a pattern (not a `fold`) because we have
to create new op `FromElementsOp` with updated result type. This cannot
be done with a `fold`, because `fold` cannot create new ops and the
existing `FromElementsOp` result type differs from the `ShapeCastOp`
result type. Mutating the `FromElementsOp` (not root op) would violate
the `fold` contract and break other users.
- Added lit tests for the both ops (new `vector-to-elements.mlir`,
`vector-from-elements.mlir`)
---------
Signed-off-by: Alexandra Sidorova <asidorov at amd.com>
Commit: ea79bcfcc579f940e05ae81d898ef19594dea402
https://github.com/llvm/llvm-project/commit/ea79bcfcc579f940e05ae81d898ef19594dea402
Author: Leandro Lupori <leandro.lupori at linaro.org>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/test/Lower/OpenMP/composite_simd_linear.f90
M flang/test/Lower/OpenMP/distribute-parallel-do-simd.f90
M flang/test/Lower/OpenMP/distribute-simd.f90
M flang/test/Lower/OpenMP/loop-pointer-variable.f90
M flang/test/Lower/OpenMP/ordered-simd.f90
M flang/test/Lower/OpenMP/wsloop-simd.f90
Log Message:
-----------
[flang][OpenMP] Fix lowering of LINEAR iteration variables (#183794)
Linear iteration variables were being treated as private. This fixes
one of the issues reported in #170784.
Commit: a34d56dee94ba3ce31f3b03bc8bb9f38012a7c89
https://github.com/llvm/llvm-project/commit/a34d56dee94ba3ce31f3b03bc8bb9f38012a7c89
Author: Fangrui Song <i at maskray.me>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
A llvm/test/CodeGen/AArch64/dso_local_equivalent.ll
M llvm/test/MC/ELF/rtti-proxy-gotpcrel.ll
Log Message:
-----------
[AArch64] Fix relative vtable PLT/GOTPCREL specifiers to use MCSpecifierExpr (#184393)
PR #155776 changed S_PLT/S_GOTPCREL printing to
%pltpcrel(x)/%gotpcrel(x)
syntax via MCSpecifierExpr, but lowerSymbolDifference and
getIndirectSymViaGOTPCRel still created MCSymbolRefExpr with these
specifiers, which prints via the @-specifier table as @PLT/@GOTPCREL,
leading to incorrect relocation types.
Fixes: bed89970c3df5e755820708580e405f65ddaa1ba
(AArch64: Replace @plt/%gotpcrel in data directives with %pltpcrel
%gotpcrel (#155776))
Add llvm/test/CodeGen/AArch64/dso_local_equivalent.ll
Commit: 90febba9c4ec8cb7fed9b8b0dafab2458583c0ca
https://github.com/llvm/llvm-project/commit/90febba9c4ec8cb7fed9b8b0dafab2458583c0ca
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll
Log Message:
-----------
[X86] vector-shuffle-combining-xop.ll - tests showing failure to combine shuffles with non-uniform rotates (#184397)
We only handle this for VROTLI/VROTRI nodes
Noticed while working on #184002
Commit: 637bb0e37747001eaac08bca4312177f57735f5e
https://github.com/llvm/llvm-project/commit/637bb0e37747001eaac08bca4312177f57735f5e
Author: hanbeom <kese111 at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
M llvm/test/CodeGen/WebAssembly/load-ext.ll
Log Message:
-----------
[WebAssembly][FastISel] Call materializeLoadStoreOperands in load fold (#184203)
The `tryToFoldLoadIntoMI` function omitted materializing base registers
for addresses before folding sign-extend instructions into loads. This
left `$noreg` as the base register, crashing subsequent passes.
WebAssembly memory instructions structurally require a valid base
register. Calling the existing `materializeLoadStoreOperands` function
ensures that a `CONST 0` virtual register is generated when addressing
global variables directly without a pre-existing base register.
(before) %1:i32 = LOAD8_S_I32_A32 0, @ch, $noreg ... -> CRASH (after)
%3:i32 = CONST_I32 0
%1:i32 = LOAD8_S_I32_A32 0, @ch, %3:i32 ... -> Folded safely
Commit: f42b8a18d9043f36f173184d1bf1c28dc6a5be2f
https://github.com/llvm/llvm-project/commit/f42b8a18d9043f36f173184d1bf1c28dc6a5be2f
Author: PiJoules <leonardchan at google.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
Log Message:
-----------
[sanitizer][Fuchsia] Define interceptor for reallocarray on Fuchsia (#184410)
Commit: 80acaccbe644ea6c87ca54d4426b4dbdb53e5671
https://github.com/llvm/llvm-project/commit/80acaccbe644ea6c87ca54d4426b4dbdb53e5671
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
Log Message:
-----------
[RISCV] Promote i8/i16/i32 scalable vector CLMUL to i64 CLMUL with Zvbc. (#184265)
This handles the simple case where we can widen to i64 vector
without splitting. More work will be done in follow ups.
Commit: e379ad78203b32bb444c1ceab2869767a0de728c
https://github.com/llvm/llvm-project/commit/e379ad78203b32bb444c1ceab2869767a0de728c
Author: Zhijie Wang <yesterda9 at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeAnnotations.h
M clang/lib/Analysis/LifetimeSafety/LifetimeAnnotations.cpp
M clang/test/Sema/Inputs/lifetime-analysis.h
M clang/test/Sema/warn-lifetime-analysis-nocfg.cpp
M clang/test/Sema/warn-lifetime-safety-invalidations.cpp
Log Message:
-----------
[LifetimeSafety] Use per-container invalidation rules to fix false positives (#183000)
- Refactor `isContainerInvalidationMethod()` to per-container
invalidation sets, based on
https://en.cppreference.com/w/cpp/container#Iterator_invalidation.
- Follow reference invalidation rules instead of iterator invalidation
rules. Specifically:
- Methods that only invalidate iterators but not references are excluded
(e.g. `deque::push_back`, `unordered_map::emplace`).
- Methods that only invalidate references to the removed element itself
are excluded (e.g. `vector::pop_back`, `deque::pop_*`, and
`erase`/`extract` on all node-based containers).
- Fix false positives for `insert`/`emplace` etc on ordered associative
containers (`set`, `map`, `multiset`, `multimap`), which never
invalidate iterators per the standard.
- Add previously missing methods: `emplace_hint`, `insert_or_assign`,
`push_range`, `replace_with_range`, `resize_and_overwrite`, `merge`.
- `operator[]` now only invalidates for `flat_map`. `map::operator[]`
and `unordered_map::operator[]` may insert but don't invalidate
references.
Fixes #181912
Commit: c5039c18482765b1499d94231c8b4c5e1a4be485
https://github.com/llvm/llvm-project/commit/c5039c18482765b1499d94231c8b4c5e1a4be485
Author: zhijian lin <zhijian at ca.ibm.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[NFC] Refactor the SelectionDAG::getMemcmp etc with a existing helper function getRuntimeCallSDValueHelper (#184200)
Refactor the SelectionDAG::getMemcmp,
SelectionDAG::getStrcpy,SelectionDAG::getStrlen with a existing helper
function SelectionDAG::getRuntimeCallSDValueHelper.
Commit: 6893d277575df9779184cb1b2a1efea31dc0a65c
https://github.com/llvm/llvm-project/commit/6893d277575df9779184cb1b2a1efea31dc0a65c
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M flang/lib/Semantics/canonicalize-acc.cpp
M flang/test/Semantics/OpenACC/acc-canonicalization-validity.f90
Log Message:
-----------
[flang][acc] Improve clause validity check around do concurrent (#184389)
The current validity message prints out both "TILE" and "COLLAPSE" even
if just one of them is used. This makes it confusing if the user only
used one of them. This improves the messages to be precise which clause
is not allowed (and separate messages are issued when both clauses are
used).
Commit: 03bd4ef4ecf9b6e5003a78af34438e978d064cb4
https://github.com/llvm/llvm-project/commit/03bd4ef4ecf9b6e5003a78af34438e978d064cb4
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.h
A clang/test/CIR/CodeGenCXX/vtable-pure-deleted-funcs.cpp
Log Message:
-----------
[CIR] Handle vtable pure and deleted virtual functions (#183862)
Finding reproducers for these that don't use the deferred vtable (which
we haven't yet implemented) was a bit of a challenge, but I found
this setup to get these to be emitted. Fortunately it is a quite easy
implementation that doesn't do awfully much.
This patch implements both, plus the name through the itanium ABI.
Commit: 2d4c8e0d0fa2279a3d76365c29c63ec03433351c
https://github.com/llvm/llvm-project/commit/2d4c8e0d0fa2279a3d76365c29c63ec03433351c
Author: Jason Van Beusekom <jason.van-beusekom at hpe.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/include/clang/AST/ASTMutationListener.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Serialization/ASTWriter.h
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/lib/Frontend/MultiplexConsumer.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Serialization/ASTCommon.h
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/test/OpenMP/target_indirect_codegen.cpp
A clang/test/OpenMP/target_vtable_omp_indirect_call_lookup.cpp
M offload/test/api/omp_indirect_call_table_manual.c
A offload/test/api/omp_indirect_func_array.c
A offload/test/api/omp_indirect_func_basic.c
A offload/test/api/omp_indirect_func_struct.c
A offload/test/api/omp_virtual_func.cpp
A offload/test/api/omp_virtual_func_multiple_inheritance_01.cpp
A offload/test/api/omp_virtual_func_multiple_inheritance_02.cpp
A offload/test/api/omp_virtual_func_reference.cpp
Log Message:
-----------
[OpenMP][clang] Indirect and Virtual function call mapping from host to device (#184412)
This patch implements the CodeGen logic for calling __llvm_omp_indirect_call_lookup
on the device when an indirect function call or a virtual function call is made
within an OpenMP target region.
---------
Co-authored-by: Youngsuk Kim
Commit: a5ca0ec16bdd8143bd3d0dd04845a2297b035e5a
https://github.com/llvm/llvm-project/commit/a5ca0ec16bdd8143bd3d0dd04845a2297b035e5a
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M libcxx/utils/libcxx/test/dsl.py
Log Message:
-----------
[libc++] Update documentation for _executeWithFakeConfig (#184420)
Commit: c7c16573b8f3c1842791fadcd916d2eb96347c58
https://github.com/llvm/llvm-project/commit/c7c16573b8f3c1842791fadcd916d2eb96347c58
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/test/CIR/CodeGen/atomic-thread-fence.c
Log Message:
-----------
[CIR] Synchronize CIR with recent changes to atomic ops (#184416)
This synchronizes the CIR atomic expression handling with changes that
were made in https://github.com/llvm/llvm-project/pull/183853
Commit: b5baf5e062b24d0f240aae09fd771aacca891f2d
https://github.com/llvm/llvm-project/commit/b5baf5e062b24d0f240aae09fd771aacca891f2d
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
A clang/test/CIR/CodeGen/gnu-ptr-math.c
Log Message:
-----------
[CIR] Implement func-ptr/void-ptr addition/subtraction/inc/dec. (#184254)
As a GNU extension, clang supports math on void* and function pointers
in C mode only. From a CIR perspective, it makes sense to leave these
types in the IR, since it might be useful to do analysis.
During lowering, we already properly lower these to a size-1 element, so
there is no changes that need to happen besides letting this get through
CIR generation. This patch does that, plus adds some tests.
Commit: 899080a87ad96d5f590ad8bb469b9a33e6de6795
https://github.com/llvm/llvm-project/commit/899080a87ad96d5f590ad8bb469b9a33e6de6795
Author: Finn Plummer <mail at inbelic.dev>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/docs/DirectX/DXILResources.rst
M llvm/lib/Analysis/DXILResource.cpp
A llvm/test/Analysis/DXILResource/buffer-frombinding-unbounded.ll
Log Message:
-----------
[Analysis][DXILResource] Correct bound computation (#184198)
The range is an unsigned integer where a value of `UINT32_MAX` denotes
an unbounded range
The current implementation implied that any size interpreted as a signed
integer that is negative was unbounded, which is incorrect.
Adds a note to the docs
Commit: 17aaa0e590a7e7a741946f166b1ff73023cf8576
https://github.com/llvm/llvm-project/commit/17aaa0e590a7e7a741946f166b1ff73023cf8576
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Use bitfield to store Cmp predicates and GEP wrap flags. (NFC) (#181571)
Instead of storing CmpInst::Predicate/GepNoWrapFlags, only store their
raw bitfield values. This reduces the size of VPIRFlags from 12 to 3
bytes.
PR: https://github.com/llvm/llvm-project/pull/181571
Commit: 8272546f6910e78f255830d9592c6926d93be04c
https://github.com/llvm/llvm-project/commit/8272546f6910e78f255830d9592c6926d93be04c
Author: Kaitlin Peng <kaitlinpeng at microsoft.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVCombinerHelper.cpp
Log Message:
-----------
[HLSL][SPIRV] Fix `faceforward` pattern matcher logic (#183630)
Fixes a logic issue in the `faceforward` pattern matcher in
`SPIRVCombinerHelper.cpp`.
Previously when `mi_match` failed, we would still go through the nested
`Pred == CmpInst::FCMP_OGT || Pred == CmpInst::FCMP_UGT` check. It was
possible that whatever garbage was in Pred could randomly pass this
check and make us continue through the code. This change fixes that
logic issue by returning false as soon as `mi_match` fails.
Likely fixes #177803. Can't confirm since it seems another change has
obscured the crash.
Commit: b4dfa43cb8aea45487033d1f21c49672ac33e02a
https://github.com/llvm/llvm-project/commit/b4dfa43cb8aea45487033d1f21c49672ac33e02a
Author: lihengda861-source <lihengda861 at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
Log Message:
-----------
[RISCV] Fix type inference ambiguity in SwapSysReg pattern (#184305)
Issue:
Building RISCVInstrInfo.td fails with the following TableGen error
during the generation of RISCVGenInstrInfo.inc:
` error: In test: Could not infer all types in pattern!`
Root Cause:
The riscv_swap_csr node has a polymorphic result type (i32 or i64
depending on the target architecture). When used inside the SwapSysReg
class pattern, TableGen's type inference engine cannot automatically
deduce the exact return type solely from the GPR:$rd output, leading to
the ambiguity error.
Fix:
This patch resolves the type ambiguity by explicitly wrapping the
riscv_swap_csr node with XLenVT, allowing TableGen to infer the types
correctly.
Commit: 5586d93a87eff7d6f01564c2ea0dfb82378a7fb2
https://github.com/llvm/llvm-project/commit/5586d93a87eff7d6f01564c2ea0dfb82378a7fb2
Author: Florian Mayer <fmayer at google.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope.ll
Log Message:
-----------
[NFC] [HWASan] more meaningful BB names in use-after-scope test (#183867)
Commit: 375d65ee8de7dd65e19faab567db2799a52dfe52
https://github.com/llvm/llvm-project/commit/375d65ee8de7dd65e19faab567db2799a52dfe52
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Dialect/Passes.h
M clang/include/clang/CIR/Dialect/Passes.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/Dialect/Transforms/CMakeLists.txt
A clang/lib/CIR/Dialect/Transforms/EHABILowering.cpp
M clang/lib/CIR/Lowering/CIRPasses.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/test/CIR/CodeGen/try-catch-tmp.cpp
M clang/test/CIR/CodeGen/try-catch.cpp
A clang/test/CIR/Transforms/eh-abi-lowering-itanium.cir
M clang/tools/cir-opt/cir-opt.cpp
Log Message:
-----------
[CIR] Implement EH lowering to Itanium form and LLVM IR (#184386)
This introduces a new pass to lower from a flattened, target-independent
form of CIR to a form that uses Itanium-specific representation for
exception handling. It also includes a small amount of code needed to
lower the Itanium form to LLVM IR.
Substantial amounts of this PR were created using agentic AI tools, but
I have carefully reviewed the code, comments, and tests and made changes
as needed.
Commit: 9d0c62c3ddb14f0cc2ed47a6088083257fa68f10
https://github.com/llvm/llvm-project/commit/9d0c62c3ddb14f0cc2ed47a6088083257fa68f10
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/test/CodeGen/X86/known-never-zero.ll
Log Message:
-----------
[X86] known-never-zero.ll - improve demandedelts test coverage for #183227 (#184411)
The original tests from #184350 were recognising every element as
non-zero
Commit: 80a1cf4f80583b688b4a04c83baada31a40b851d
https://github.com/llvm/llvm-project/commit/80a1cf4f80583b688b4a04c83baada31a40b851d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/amdhsa_abi.h
A clang/test/Headers/amdhsa_abi.cl
Log Message:
-----------
clang: Add builtin header for amdhsa abi (#181993)
Commit: 4b06e83885593112ab346c4753cc080ec3ef0ea3
https://github.com/llvm/llvm-project/commit/4b06e83885593112ab346c4753cc080ec3ef0ea3
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M .github/workflows/containers/github-action-ci-windows/Dockerfile
M .github/workflows/containers/github-action-ci/Dockerfile
Log Message:
-----------
[Github][CI] Bump CI containers to LLVM v22.1.0 (#184375)
Commit: df1a53ae242418f5ac22adb5bb2178d3f931565f
https://github.com/llvm/llvm-project/commit/df1a53ae242418f5ac22adb5bb2178d3f931565f
Author: Sean Fertile <sd.fertile at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M compiler-rt/test/lsan/TestCases/create_thread_leak.cpp
Log Message:
-----------
Disable leak sanitizer test on ppc. (#184414)
Test is flaky and fails due to machine load on the build bots. Disable
until we can split the build bots over more machines.
Commit: dc44bcafe08e6644a3f7b98144394d6f3ef5c3c2
https://github.com/llvm/llvm-project/commit/dc44bcafe08e6644a3f7b98144394d6f3ef5c3c2
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M flang-rt/CMakeLists.txt
Log Message:
-----------
[flang-rt] Fix NVPTX builds erroneously using backtrace support (#184415)
Summary:
This is caused by the CMake hacks I had to do to worm around NVIDIA's
proprietary binaries.
Commit: dc1e3e5dbf7805ff060c84135a63fc7239c52814
https://github.com/llvm/llvm-project/commit/dc1e3e5dbf7805ff060c84135a63fc7239c52814
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll
Log Message:
-----------
[X86] getFauxShuffleMask - add ISD::ROTL/ROTR handling (#184417)
Very similar to the existing X86ISD::VROTLI/VROTRI handling
Prep work for #184002
Commit: fdc4a982f5d6a41fdb0b00bf49b72446a1f0c5ea
https://github.com/llvm/llvm-project/commit/fdc4a982f5d6a41fdb0b00bf49b72446a1f0c5ea
Author: Yoonseo Choi <yoonchoi at amd.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/test/CodeGen/AMDGPU/implicit-arg-block-count.ll
M llvm/test/CodeGen/AMDGPU/implicit-arg-v5-opt.ll
A llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
Log Message:
-----------
[AMDGPU] Add dereferenceable retAttr to a call to llvm.amdgcn.implicitarg.ptr (#182206)
Commit: fe76fd292cc3815f2cc3877eb1641db0cb40e3fb
https://github.com/llvm/llvm-project/commit/fe76fd292cc3815f2cc3877eb1641db0cb40e3fb
Author: vporpo <vasileios.porpodas at amd.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Log Message:
-----------
[AMDGPU][SIInsertWaitcnts][NFC] Call applyWaitcnt() in a loop (#184426)
Commit: 6b5c55ef169cfb19e0159241a5932e593a8e1e3c
https://github.com/llvm/llvm-project/commit/6b5c55ef169cfb19e0159241a5932e593a8e1e3c
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M lldb/source/Core/Debugger.cpp
Log Message:
-----------
[lldb] Fix 10 year old leak of `g_debugger_list_ptr` (#184259)
Roughly 10 years ago, in aacb80853a46bd544fa76a945667302be1de706c, Greg
deleted the call to delete g_debugger_list_ptr because of a race
condition:
> Fixed a threading race condition where we could crash after calling
Debugger::Terminate().
>
> The issue was we have two global variables: one that contains a
DebuggerList pointer and one that contains a std::mutex > pointer. These
get initialized in Debugger::Initialize(), and everywhere that uses
these does:
>
> if (g_debugger_list_ptr && g_debugger_list_mutex_ptr)
> {
> std::lock_guard<std::recursive_mutex>
guard(*g_debugger_list_mutex_ptr);
> // do work while mutex is locked
> }
>
> Debugger::Terminate() was deleting and nulling out g_debugger_list_ptr
which meant we had a race condition where someone might do the if
statement and it evaluates to true, then another thread calls
Debugger::Terminate() and deletes and nulls out g_debugger_list_ptr
while holding the mutex, and another thread then locks the mutex and
tries to use g_debugger_list_ptr. The fix is to just not delete and null
out the g_debugger_list_ptr variable.
However, this isn't necessary as long as we persist ("leak") the mutex
and always check it first. That's exactly what this patch does. Without
it, the assert in Debugger::Initialize is incorrect.
```
assert(g_debugger_list_ptr == nullptr &&
"Debugger::Initialize called more than once!");
```
Commit: c4ea6cc3f736ab5b3feeaf16c448db5217b14306
https://github.com/llvm/llvm-project/commit/c4ea6cc3f736ab5b3feeaf16c448db5217b14306
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M lldb/source/Plugins/Process/FreeBSD-Kernel-Core/ProcessFreeBSDKernelCore.cpp
M lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp
M lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp
M lldb/source/Plugins/Process/scripted/ScriptedProcess.cpp
M lldb/source/Plugins/Process/wasm/ProcessWasm.cpp
M lldb/source/Plugins/RegisterTypeBuilder/RegisterTypeBuilderClang.cpp
M lldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.cpp
M lldb/source/Plugins/ScriptInterpreter/None/ScriptInterpreterNone.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
Log Message:
-----------
[lldb] Remove call_once wrappers around PluginManager::RegisterPlugin (#184273)
Remove call_once wrappers around PluginManager::RegisterPlugin. Plugins
can be registered and unregistered in Initialize and Terminate
respectively. In its current state, after having called Terminate, a
plugin can never be re-initialized.
Commit: 89a4bcf023493cb75aded5a70c082c1fa7d46cbc
https://github.com/llvm/llvm-project/commit/89a4bcf023493cb75aded5a70c082c1fa7d46cbc
Author: Henrich Lauko <xlauko at mail.muni.cz>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td
M clang/include/clang/CIR/Interfaces/CIROpInterfaces.td
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenOpenACCRecipe.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerItaniumCXXABI.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/test/CIR/CodeGen/assign-operator.cpp
M clang/test/CIR/CodeGen/atomic.c
M clang/test/CIR/CodeGen/basic.c
M clang/test/CIR/CodeGen/basic.cpp
M clang/test/CIR/CodeGen/binop.cpp
M clang/test/CIR/CodeGen/bitfields.c
M clang/test/CIR/CodeGen/complex-compound-assignment.cpp
M clang/test/CIR/CodeGen/complex-mul-div.cpp
M clang/test/CIR/CodeGen/complex.cpp
M clang/test/CIR/CodeGen/compound_assign.cpp
M clang/test/CIR/CodeGen/if.cpp
M clang/test/CIR/CodeGen/integer-overflow.c
M clang/test/CIR/CodeGen/lambda.cpp
M clang/test/CIR/CodeGen/namespace.cpp
M clang/test/CIR/CodeGen/new.cpp
M clang/test/CIR/CodeGen/no-odr-use.cpp
M clang/test/CIR/CodeGen/non-type-template-param.cpp
M clang/test/CIR/CodeGen/opaque.cpp
M clang/test/CIR/CodeGen/pointer-to-data-member-cast.cpp
M clang/test/CIR/CodeGen/pointer-to-member-func-cast.cpp
M clang/test/CIR/CodeGen/pointer-to-member-func-cmp.cpp
M clang/test/CIR/CodeGen/pointer-to-member-func.cpp
M clang/test/CIR/CodeGen/requires-expr.cpp
M clang/test/CIR/CodeGen/size-of-vla.cpp
M clang/test/CIR/CodeGen/struct-init.cpp
M clang/test/CIR/CodeGen/switch_flat_op.cpp
M clang/test/CIR/CodeGen/ternary.cpp
M clang/test/CIR/CodeGen/throws.cpp
M clang/test/CIR/CodeGen/try-catch.cpp
M clang/test/CIR/CodeGen/variable-decomposition.cpp
M clang/test/CIR/CodeGen/vector-ext-element.cpp
M clang/test/CIR/CodeGen/vector-ext.cpp
M clang/test/CIR/CodeGen/vector.cpp
M clang/test/CIR/CodeGen/vla.c
M clang/test/CIR/CodeGenBuiltins/AArch64/acle_sve_len.c
M clang/test/CIR/CodeGenBuiltins/X86/avx10_2_512bf16-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/avx10_2bf16-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/avx2-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/avx512bw-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/avx512dq-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/avx512fp16-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/avx512vldq-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/cmp-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/sse2-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/sse41-builtins.c
M clang/test/CIR/CodeGenOpenACC/atomic-capture.cpp
M clang/test/CIR/CodeGenOpenACC/atomic-update.cpp
M clang/test/CIR/CodeGenOpenACC/atomic-write.cpp
M clang/test/CIR/CodeGenOpenACC/combined-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/combined-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-default-ops.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-float.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-int.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-outline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/combined.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.c
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-float.c
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-float.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-int.c
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-int.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-outline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-unsigned-int.c
M clang/test/CIR/CodeGenOpenACC/firstprivate-clause-recipes.cpp
M clang/test/CIR/CodeGenOpenACC/loop-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-default-ops.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-float.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-int.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-outline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/loop.cpp
M clang/test/CIR/CodeGenOpenACC/private-clause-array-recipes-CtorDtor.cpp
M clang/test/CIR/CodeGenOpenACC/private-clause-pointer-array-recipes-CtorDtor.cpp
M clang/test/CIR/CodeGenOpenACC/private-clause-pointer-array-recipes-NoOps.cpp
M clang/test/CIR/CodeGenOpenACC/private-clause-pointer-array-recipes-int.cpp
M clang/test/CIR/CodeGenOpenACC/private-clause-pointer-recipes-CtorDtor.cpp
M clang/test/CIR/CodeGenOpenACC/private-clause-pointer-recipes-NoOps.cpp
M clang/test/CIR/CodeGenOpenACC/private-clause-pointer-recipes-int.cpp
M clang/test/CIR/CodeGenOpenACC/reduction-clause-recipes.cpp
M clang/test/CIR/CodeGenOpenMP/omp-llvmir.c
M clang/test/CIR/CodeGenOpenMP/parallel.c
M clang/test/CIR/IR/throw.cir
M clang/test/CIR/IR/vector.cir
M clang/test/CIR/Lowering/binop-bool.cir
M clang/test/CIR/Lowering/binop-fp.cir
M clang/test/CIR/Lowering/binop-signed-int.cir
M clang/test/CIR/Lowering/binop-unsigned-int.cir
M clang/test/CIR/Transforms/switch.cir
M clang/test/CodeGen/AArch64/neon/intrinsics.c
Log Message:
-----------
[CIR] Split cir.binop into separate per-operation binary ops (#184227)
Replace the single `cir.binop` operation (dispatched via a `BinOpKind`
enum) with nine distinct ops — `cir.add`, `cir.sub`, `cir.mul`,
`cir.div`, `cir.rem`, `cir.and`, `cir.or`, `cir.xor`, and `cir.max` —
each with precise type constraints and only the attributes it needs
(nsw/nuw/sat on add/sub via `BinaryOverflowOp`).
A new `BinaryOpInterface` provides uniform `getLhs`/`getRhs`/`getResult`
access for passes and analyses.
The monolithic switch-based CIRToLLVMBinOpLowering is replaced by per-op
patterns generated through the existing CIRLowering.inc TableGen
infrastructure, with shared dispatch factored into two helpers:
`lowerSaturatableArithOp` for add/sub and `lowerIntFPBinaryOp` for
div/rem.
Commit: 1953b87a31a9b7de9e34deaa7e94ee59b3e7de39
https://github.com/llvm/llvm-project/commit/1953b87a31a9b7de9e34deaa7e94ee59b3e7de39
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
A clang/test/CIR/CodeGenBuiltins/builtin-isinf-sign.c
Log Message:
-----------
[CIR][CodeGen] Upstream support for `__builtin_isinf_sign` (#183977)
This adds CIR codegen and lowering support for `__builtin_isinf_sign`.
Commit: 5b144c0aec63fe80a610b77e27de926869391b64
https://github.com/llvm/llvm-project/commit/5b144c0aec63fe80a610b77e27de926869391b64
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-tensor-load-store.cl
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/MIMGInstructions.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
M llvm/test/CodeGen/AMDGPU/reg-coalescer-subreg-liveness.mir
Log Message:
-----------
[AMDGPU] Add suffix _d4 to tensor load/store with 4 groups D#, NFC (#184176)
Rename TENSOR_LOAD_TO_LDS to TENSOR_LOAD_TO_LDS_d4;
Rename TENSOR_STORE_FROM_LDS to TENSOR_STORE_FROM_LDS_d4;
Also rename function names in a couple of tests to reflect this change.
Commit: 9264159ae1df6910777ffa94b37a932775ae00c7
https://github.com/llvm/llvm-project/commit/9264159ae1df6910777ffa94b37a932775ae00c7
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M lldb/unittests/DAP/TestBase.cpp
M lldb/unittests/DAP/TestBase.h
M lldb/unittests/DAP/VariablesTest.cpp
Log Message:
-----------
[lldb] Fix the GoogleTest teardown in the DAP unit tests (#184262)
Some of the DAP tests define a static method named `TeatUpTestSuite`
which is calling `SBDebugger::Terminate`. Besides the typo, the correct
method is `TearDownTestSuite`, which GoogleTest calls after running the
last test in the test suite.
When addressing this, I realized that currently you can't really call
Initialize and Terminate multiple times in the same process. This
depends on:
- https://github.com/llvm/llvm-project/pull/184259
- https://github.com/llvm/llvm-project/pull/184261
Commit: 685a65a7f03d40d81d277402f662fec4bb97b325
https://github.com/llvm/llvm-project/commit/685a65a7f03d40d81d277402f662fec4bb97b325
Author: mitchell <mitchell.xu2 at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang-tools-extra/Maintainers.rst
Log Message:
-----------
[clang-tidy] Add zeyi2 as maintainer (#183883)
I've been actively contributing to `clang-tidy` for the past 4 months,
reviewing PRs, [fixing
issues](https://github.com/pulls?q=is%3Apr+author%3Azeyi2+archived%3Afalse+user%3Allvm+is%3Aclosed+label%3Aclang-tidy+sort%3Aupdated-desc),
engaging in discourse discussions and building [new testing
tools](https://github.com/clang-tidy-infra/CTIT). I'm passionate about
and project and would like to volunteer as a maintainer to continue
supporting the project's growth :)
Commit: f4e64ceb4bd818b5d6d7a52935e0282847d7b51c
https://github.com/llvm/llvm-project/commit/f4e64ceb4bd818b5d6d7a52935e0282847d7b51c
Author: Jason Molenda <jmolenda at apple.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M lldb/source/Plugins/ABI/AArch64/ABIAArch64.cpp
M lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm64.cpp
M lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
M lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h
M lldb/source/Plugins/Process/minidump/RegisterContextMinidump_ARM64.cpp
M lldb/source/Utility/ARM64_DWARF_Registers.h
M lldb/source/Utility/ARM64_ehframe_Registers.h
Log Message:
-----------
[lldb] AArch64 register 33 is not cpsr (#183860)
I have an unwind failure where the eh_frame for a
trap handler states that the caller's return address is in eh_frame
register 33, which lldb treats as cpsr.
https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst#dwarf-register-names
Register 33 is ELR_mode, which isn't defined as a register in any of the
AArch64 register definition files in lldb today, so I'm not adding it to
the header files.
rdar://170602999
Commit: 28638f519783a705489237f9158ecd4692208b5c
https://github.com/llvm/llvm-project/commit/28638f519783a705489237f9158ecd4692208b5c
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M lldb/include/lldb/Core/Debugger.h
M lldb/include/lldb/Target/Process.h
M lldb/source/Core/Debugger.cpp
M lldb/source/Target/Process.cpp
Log Message:
-----------
[lldb] Remove Debugger::{FindTargetWithProcessID, FindTargetWithProcess} (#184446)
In #184259, Jim noticed that Debugger::FindTargetWithProcess and
Debugger::FindTargetWithProcessID are rather poorly designed APIs as
tehy allow code running in one Debugger to mess with Targets from
another Debugger. The only use is Process::SetProcessExitStatus which
isn't actually used.
Commit: 1b633d6d6d75c172ecd9b9a4e250842468edb137
https://github.com/llvm/llvm-project/commit/1b633d6d6d75c172ecd9b9a4e250842468edb137
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaChecking.cpp
M clang/test/Sema/atomic-ops.c
M clang/test/Sema/scoped-atomic-ops.c
Log Message:
-----------
[Clang] Permit floating point and pointer values in most atomic ops (#183843)
Summary:
We already support floating point arguments for the standard atomic
functions. LLVM supports these in most cases as well. This PR unifies
the handling and allows this in the cases that the LLVM IR supports.
Commit: e71f327b46059fe232b205414a3e8c1fc537c80f
https://github.com/llvm/llvm-project/commit/e71f327b46059fe232b205414a3e8c1fc537c80f
Author: zhouguangyuan0718 <89333397+zhouguangyuan0718 at users.noreply.github.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/lib/Basic/Targets/X86.h
M clang/lib/Driver/ToolChains/Arch/X86.cpp
A clang/test/Driver/x86_64-fixed-r-register.c
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/X86/X86Subtarget.cpp
M llvm/lib/Target/X86/X86Subtarget.h
A llvm/test/CodeGen/X86/reserveRreg.ll
Log Message:
-----------
[X86] support reserve r8~r15 on X86_64 (#180242)
Which is under discussion in
https://github.com/llvm/llvm-project/issues/179036
Add new options -ffixed_r{8-15} for clang X86 target, like option
"-ffixed_x" for RISCV/AArch64 target.
Also, add target-feature +reserve-r{8-15} for the X86 backend.
The registers which are specified reserved will not be used in
RegAlloc/CalleeSave. Then the reserved registers can be maintained by
user. It will be useful for the runtime/interpreter implementation.
Other registers are used in specific instructions or mechanism, so they
can't be reserved.
Commit: 87a4b36fbe7f46082c7ddb30ccf702a0913c1e08
https://github.com/llvm/llvm-project/commit/87a4b36fbe7f46082c7ddb30ccf702a0913c1e08
Author: Derek Schuff <dschuff at chromium.org>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
A llvm/test/CodeGen/WebAssembly/simd-memcmp.ll
Log Message:
-----------
[WebAssembly] Use MVT::i32 instead of i1 in performAnyAllCombine (#183866)
The CombineSetCC helpers and performAnyAllCombine generate MVT::i1
results.
However MVT::i1 is an illegal type in WebAssembly, and this combiner can
run either before or after legalization. Directly creating the intrinsic
and negating its result using XOR instead of i1 and a NOT operation
avoids this problem.
Fixes #183842
Commit: 0c9734f120550f4984363c7cf0a33453f2154721
https://github.com/llvm/llvm-project/commit/0c9734f120550f4984363c7cf0a33453f2154721
Author: Florian Mayer <fmayer at google.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[NFC] [doc] fix invalid comment syntax in IR (#184457)
Commit: 393bbd55201abdf327f7fc0aab90269393c71d67
https://github.com/llvm/llvm-project/commit/393bbd55201abdf327f7fc0aab90269393c71d67
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/performance/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Analysis/Scalable/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/Analysis/Scalable/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/DependencyScanning/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/NVPTX/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/X86/AsmParser/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
Log Message:
-----------
[gn build] Port commits (#184454)
282a2b77c358
60eac414b794
6d82f143dee1
80a1cf4f8058
8a9049198d18
a171b8d4d523
f3e8508ac771
Move X86GenAsmMatcher into llvm/lib/Target/X86
Commit: 62144f48d43fc33d7e73fff68aea31dd287d5349
https://github.com/llvm/llvm-project/commit/62144f48d43fc33d7e73fff68aea31dd287d5349
Author: Susan Tan (ス-ザン タン) <zujunt at nvidia.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M flang/lib/Lower/PFTBuilder.cpp
M flang/test/Lower/OpenMP/target.f90
M flang/test/Lower/do-while-to-scf-while.f90
M flang/test/Lower/loops.f90
M flang/test/Lower/mixed_loops.f90
M flang/test/Lower/pre-fir-tree02.f90
M flang/test/Lower/while_loop.f90
Log Message:
-----------
[flang] make lowering to scf.while default (#184234)
We've tested the implementation of fortran do-while loops being lowered
to scf.while and want to make it the default option.
Commit: 0c04d019f0a601cad2acab8d4d53704ec773fcd3
https://github.com/llvm/llvm-project/commit/0c04d019f0a601cad2acab8d4d53704ec773fcd3
Author: Florian Mayer <fmayer at google.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[NFC] [Doc] Fix text codeblock being declared llvm (#184461)
Commit: 76568dc89916b660cb3943f3871759b87c5fde4e
https://github.com/llvm/llvm-project/commit/76568dc89916b660cb3943f3871759b87c5fde4e
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
Log Message:
-----------
[LoopUnrollPass] Add `const` to parameters in `computeUnrollCount` (NFC) (#184058)
Commit: ece4b759327c03fa09edc90b802db3a74fa19e33
https://github.com/llvm/llvm-project/commit/ece4b759327c03fa09edc90b802db3a74fa19e33
Author: Dave Lee <davelee.com at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M lldb/examples/python/formatter_bytecode.py
Log Message:
-----------
[lldb] Add C source output mode to formatter_bytecode.py (#184242)
Add the ability to generate a C source file, which is in addition to the
existing functionality of generating binary.
An example of the generated source:
```c
#ifdef __APPLE__
#define FORMATTER_SECTION "__DATA_CONST,__lldbformatters"
#else
#define FORMATTER_SECTION ".lldbformatters"
#endif
__attribute__((used, section(FORMATTER_SECTION)))
unsigned char _Account_synthetic[] =
// version
"\x01"
// remaining record size
"\x15"
// type name size
"\x07"
// type name
"Account"
// flags
"\x00"
// sig_get_num_children
"\x02"
// program size
"\x02"
// program
"\x20\x01"
// sig_get_child_at_index
"\x04"
// program size
"\x06"
// program
"\x02\x20\x00\x23\x11\x60"
;
```
Commit: 630b9570d199dca19dc85834f583bc8590a21876
https://github.com/llvm/llvm-project/commit/630b9570d199dca19dc85834f583bc8590a21876
Author: Ian Wood <ianwood2024 at u.northwestern.edu>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/Math/IR/MathOps.td
M mlir/lib/Dialect/Math/IR/MathOps.cpp
M mlir/test/Dialect/Math/canonicalize.mlir
Log Message:
-----------
[mlir][math] Add constant folding for math.rsqrt (#184443)
Add a fold() method to RsqrtOp, matching the pattern used by SqrtOp and
other math unary ops. The fold computes `1.0 / sqrt(x)` using APFloat
division.
---------
Signed-off-by: Ian Wood <ianwood at u.northwestern.edu>
Commit: 60d729fdb226227f7b661558572ce538fa140c8a
https://github.com/llvm/llvm-project/commit/60d729fdb226227f7b661558572ce538fa140c8a
Author: Peter Klausler <pklausler at nvidia.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M flang/lib/Parser/prescan.cpp
M flang/lib/Parser/prescan.h
A flang/test/Parser/not-sentinel.f90
Log Message:
-----------
[flang] Fix test breakage from recent preprocessor change (#184455)
!$omp must never be recognized as a compiler directive sentinel when it
is immediately followed by anything other than a space or &. Revert a
bit of a recent change that broke this.
Commit: 5e5f7efd77064a1b05b2596dfab39966ce828359
https://github.com/llvm/llvm-project/commit/5e5f7efd77064a1b05b2596dfab39966ce828359
Author: John Harrison <harjohn at google.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M lldb/include/lldb/API/SBBlock.h
M lldb/source/API/SBBlock.cpp
A lldb/test/API/python_api/block/Makefile
A lldb/test/API/python_api/block/TestBlocks.py
A lldb/test/API/python_api/block/fn.c
A lldb/test/API/python_api/block/main.c
Log Message:
-----------
[lldb] Expose block equality with SBBlock. (#184222)
Adding the `operator==` and `operator!=` for SBBlock. This should allow
us to compare blocks within a frame, like:
```python
block = frame.GetBlock()
while True:
if block == frame.GetFrameBlock():
# we're at the top function scope.
else:
# we're at an inner block scope.
```
Commit: 699563e0da93f5047a379c9816be081afc3d0db9
https://github.com/llvm/llvm-project/commit/699563e0da93f5047a379c9816be081afc3d0db9
Author: Alexey Bader <alexey.bader at intel.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
M llvm/lib/Transforms/Utils/SplitModuleByCategory.cpp
M llvm/tools/llvm-split/llvm-split.cpp
Log Message:
-----------
[NFC] Don't replicate hasKernelCallingConv. (#184464)
isKernel function duplicates llvm::Function::hasKernelCallingConv
method.
Commit: 53fbbaa577f2321d58c3dad78c001561c02939a7
https://github.com/llvm/llvm-project/commit/53fbbaa577f2321d58c3dad78c001561c02939a7
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M lldb/source/Initialization/SystemInitializerCommon.cpp
M lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.cpp
M lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDPLog.cpp
M lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDPLog.h
M lldb/source/Plugins/Process/POSIX/ProcessPOSIXLog.cpp
M lldb/source/Plugins/Process/POSIX/ProcessPOSIXLog.h
M lldb/source/Plugins/Process/Windows/Common/ProcessWindowsLog.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemoteLog.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemoteLog.h
Log Message:
-----------
[lldb] Fix Initialization/Termination for all log channels (#184467)
Similar to #184261, but for all the other log channels.
Commit: 45dbce3a3a3e05111a7fef4bb33f323996331a59
https://github.com/llvm/llvm-project/commit/45dbce3a3a3e05111a7fef4bb33f323996331a59
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M lldb/include/lldb/Utility/LLDBLog.h
M lldb/source/Initialization/SystemInitializerCommon.cpp
M lldb/source/Utility/LLDBLog.cpp
Log Message:
-----------
[lldb] Wrap LLDBLog Initialize/Terminate in a class (NFC) (#184469)
This matches what we do for all the other log channels (GDB Remote,
POSIX, Windows, KDP, etc).
Commit: 3b4d5ffe847ce194173c3b778a34e55d416e6544
https://github.com/llvm/llvm-project/commit/3b4d5ffe847ce194173c3b778a34e55d416e6544
Author: Jianhui Li <jian.hui.li at intel.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
M mlir/test/Dialect/XeGPU/subgroup-distribute-unit.mlir
M mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
Log Message:
-----------
[MLIR][XeGPU] Add blocking and subgroup to lane distribution support for ConvertLayout operation (#183837)
This PR refactors blocking support for ConvertLayout op to allow it
unrollable, not just removing it for specialize case.
It also removes the foldable attribute for ConvertLayout op, as we
expect the OP to be explicitly handled by XeGPU lowering.
It adds subgroup to lane distribution support for ConvertLayout op.
Commit: 928505c98345e0494f2d260788adb291efc9ee38
https://github.com/llvm/llvm-project/commit/928505c98345e0494f2d260788adb291efc9ee38
Author: Sam Clegg <sbc at chromium.org>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
R lld/test/wasm/Inputs/archive1.ll
A lld/test/wasm/Inputs/archive1.s
R lld/test/wasm/Inputs/archive2.ll
A lld/test/wasm/Inputs/archive2.s
R lld/test/wasm/Inputs/archive3.ll
A lld/test/wasm/Inputs/archive3.s
M lld/test/wasm/archive-export.test
R lld/test/wasm/archive.ll
A lld/test/wasm/archive.s
Log Message:
-----------
[lld][WebAssembly] Convert more tests to assembly. NFC (#184418)
The only expectations change here is that `__stack_pointer` is
no longer exports in the `archive-export.test` test. This is because
we don't enable the mutable-globals feature (since the assembly files
don't contains all the now-default features of the generic CPU).
Commit: 3a85d99a1606f30f7e1519b98d2156790eb553dc
https://github.com/llvm/llvm-project/commit/3a85d99a1606f30f7e1519b98d2156790eb553dc
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/third-party/BUILD.bazel
M utils/bazel/third_party_build/zlib-ng.BUILD
Log Message:
-----------
[bazel] Fix building lldb with zlib disabled (#184525)
In cmake this value is set in llvm-config.h, we're not really handling
that the same way in bazel so we can just allow all targets to inherit
this disabled, otherwise it fails since lldb assumes it is always
something
Commit: 1c434928d26cd10c0d844f59ca1b686908d4b79e
https://github.com/llvm/llvm-project/commit/1c434928d26cd10c0d844f59ca1b686908d4b79e
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M utils/bazel/.bazelrc
Log Message:
-----------
[bazel] Remove old zlib config variable (#184527)
Use was removed in a268127736e4d703cef8c9f4841f9a8e8ac21ba7
Commit: 98c46261d926bc91a9389cf25fcc06831cb63a36
https://github.com/llvm/llvm-project/commit/98c46261d926bc91a9389cf25fcc06831cb63a36
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/PowerPC/clmul-vector.ll
Log Message:
-----------
[TargetLowering][PowerPC] Don't unroll vector CLMUL when MUL is not supported. (#184238)
We can use the bittest lowering instead.
Commit: 7fb92cdf5fa69423b4b99259057eb8de813c1344
https://github.com/llvm/llvm-project/commit/7fb92cdf5fa69423b4b99259057eb8de813c1344
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M third-party/benchmark/include/benchmark/benchmark.h
Log Message:
-----------
[Benchmark] Fix warnings around usage of __COUNTER__ (#184524)
Premerge CI is currently failing with the following after the update to
clang v22:
```
/home/gha/llvm-project/clang-tools-extra/clangd/benchmarks/IndexBenchmark.cpp:92:1: error: '__COUNTER__' is a C2y extension [-Werror,-Wc2y-extensions]
92 | BENCHMARK(dexQueries);
| ^
```
Some original work was done around this in
df1d786c460e0e47c9074f3533f098190ebfbc1b, which was then done in
upstream Google benchmark in
https://github.com/google/benchmark/commit/d8db2f90b643eb28a12976beb4d57bcfb639911d.
The original work done in the patch implementing this feature doesn't
seem to account for as many cases as the upstream patch does. This patch
reverts the diff in df1d786c460e0e47c9074f3533f098190ebfbc1b and applies
the applicable hunks from the upstream patch.
Commit: 6e1ab3a4310d3c385a06e1c575f1eca58990e733
https://github.com/llvm/llvm-project/commit/6e1ab3a4310d3c385a06e1c575f1eca58990e733
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/lib/Sema/SemaType.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
A clang/test/Modules/demote-var-def.cpp
A clang/test/Modules/module-init-forcelly-loaded-module.cpp
A clang/test/Modules/pr149404-02.cppm
A clang/test/Modules/pr172241.cppm
A clang/test/Modules/var-inst-def.cppm
Log Message:
-----------
[Serialization] Stop demote var definition as declaration (#172430) (#177117) (#184287)
Close https://github.com/llvm/llvm-project/issues/172241 Close
https://github.com/llvm/llvm-project/issues/64034 Close
https://github.com/llvm/llvm-project/issues/149404 Close
https://github.com/llvm/llvm-project/issues/174858
After this patch, we (the clang dev) no longer assumes there are at most
one definition in a redeclaration chain.
See
https://discourse.llvm.org/t/rfc-clang-not-assuming-there-is-at-most-one-definition-in-a-redeclaration-chain/89360
for details.
---
Update since last commit:
Previously I remove the code to update visibility accidently. This is
the root cause of the failure.
---
Update since last commit:
Still demote var definition as declaration if it is in headers. This is
meant to avoid https://github.com/llvm/llvm-project/issues/181076
See the comments in ASTDeclReader::attachPreviousDeclImpl .
Close https://github.com/llvm/llvm-project/issues/181076
Commit: dcbc5de7f85f73066afede5c34fc909d45e73857
https://github.com/llvm/llvm-project/commit/dcbc5de7f85f73066afede5c34fc909d45e73857
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M lldb/include/lldb/Host/LZMA.h
Log Message:
-----------
[lldb][NFC] Add missing include to LZMA.h (#184536)
This header assumed you already included this otherwise it has errors
Commit: e6b9d816f6a28c9fe2b908e845a6b8e32ca460a2
https://github.com/llvm/llvm-project/commit/e6b9d816f6a28c9fe2b908e845a6b8e32ca460a2
Author: Alexey Karyakin <akaryaki at qti.qualcomm.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
A clang/lib/Headers/.clang-format-ignore
M clang/lib/Headers/hvx_hexagon_protos.h
Log Message:
-----------
[Hexagon] Ignore formatting of generated proto files (#184427)
hexagon_protos.h, hexagon_circ_brev_intrinsics.h, and
hvx_hexagon_protos.h are generated C header files that consist of
macro definitions and help fields in comments. These files are large.
Automatic formatting of these files breaks their regular structure
and increases maintenance effort.
Commit: e808a7f844ca4e9df47d2a09f8da441f6eab48e0
https://github.com/llvm/llvm-project/commit/e808a7f844ca4e9df47d2a09f8da441f6eab48e0
Author: Jianjian Guan <jacquesguan at me.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
Log Message:
-----------
[RISCV][GISel] Replace buildInstr with BuildMI (#183714)
As @arsenm mentioned in some of my PRs, such as:
https://github.com/llvm/llvm-project/pull/171092, we should use
`BuildMI` instead of `MachineInstrBuilder::buildInstr` in Selector.
This PR is tring to replace all `MachineInstrBuilder::buildInstr` with
`BuildMI`.
Commit: a6bbe463ce67c52dc120f5ea4c9f1a94e1d4988c
https://github.com/llvm/llvm-project/commit/a6bbe463ce67c52dc120f5ea4c9f1a94e1d4988c
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
Log Message:
-----------
[clang][CIR] Pass VFS to command-line parsing (#184226)
This explicitly passes Clang's VFS to MLIR command-line parsing that
runs when ClangIR is enabled. This matches the rest of Clang and fixes a
sandbox violation.
Commit: 4b85c1301fb61c6965a5143113f5170a4b062e3a
https://github.com/llvm/llvm-project/commit/4b85c1301fb61c6965a5143113f5170a4b062e3a
Author: Aditya Singh <aditya26189 at kgpian.iitkgp.ac.in>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang-tools-extra/clang-tidy/readability/RedundantPreprocessorCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/readability/redundant-preprocessor.cpp
Log Message:
-----------
[clang-tidy] Fix false positive in readability-redundant-preprocessor for builtin checks (#181734)
Different `__has_builtin()` checks were incorrectly flagged as redundant
because ConditionRange collapsed after macro expansion. It now reads
condition text directly from source to fix this.
Assisted-by: Claude
Fixes #64825
Commit: 5f29cdc175f61924c97de10450667f144dd9d195
https://github.com/llvm/llvm-project/commit/5f29cdc175f61924c97de10450667f144dd9d195
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
Log Message:
-----------
[RISCV] Remove OperandType OPERAND_SIMM10_UNSIGNED. Rename OPERAND_SIMM8_UNSIGNED->OPERAND_SIMM8 (#184540)
The UNSIGNED only refers to what we allow in assembly parsing. The
MachineInstr/MCInst should always be canonicalized to signed.
Commit: f5f0930c4715749df5a92f2b055647450f5308d4
https://github.com/llvm/llvm-project/commit/f5f0930c4715749df5a92f2b055647450f5308d4
Author: Madhur Amilkanthwar <madhura at nvidia.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Utils/VNCoercion.cpp
A llvm/test/Transforms/GVN/svcount-access.ll
Log Message:
-----------
[GVN] Fix crash when svcount is used with globals-aa (#184347)
When -globals-aa is used, `analyzeLoadAvailiability` calls
`analyzeLoadClobberringStore` which in turn calls
`isFirstClassAggregateOrScalableType` which is using
`isa<ScalableVectorType>`. Ideally it should use type's isScalableType()
method.
The crash does not occur when default (BasicAA) is used because
`analyzeLoadAvailiability` function does not take the load clobbering
path as BasicAA returns `Def`.
Fixes #159368
Commit: 348f4fb9e00a4594d8e181803e17071e626fa40c
https://github.com/llvm/llvm-project/commit/348f4fb9e00a4594d8e181803e17071e626fa40c
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
A llvm/test/Analysis/DependenceAnalysis/weak_zero_siv_parametric_coeff.ll
A llvm/test/Analysis/DependenceAnalysis/weak_zero_siv_parametric_const.ll
Log Message:
-----------
[DA] Add tests that represent edge cases for the Weak Zero SIV tests (NFC) (#183735)
This patch adds test cases that capture edge cases for the Weak‑Zero SIV
tests. These cases involve loop‑invariant, non‑constant variables, and
special care is required when those variables may be zero.
Commit: dd8d5ffe0d087da8688f0af17318c2fc0b14983f
https://github.com/llvm/llvm-project/commit/dd8d5ffe0d087da8688f0af17318c2fc0b14983f
Author: Luke Lau <luke at igalia.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vadd.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vfadd.ll
M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
M llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
M llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
M llvm/test/CodeGen/RISCV/rvv/nontemporal-vp-scalable.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
Log Message:
-----------
[RISCV] Sink instructions so AVL dominates in RISCVVLOptimizer (#184155)
The last feature that RISCVVectorPeephole::tryToReduceVL has that
RISCVVLOptimizer doesn't is that if the vl to reduce to doesn't dominate
a vector pseudo, it can sink the pseudo below the vl definition if it's
safe to do so.
This PR shares the logic to check for physical register clobbering in
RISCVInstrInfo, but there may be a better place for it.
The DemandedVLs DenseMap needs to be switched to a MapVector to get
deterministic ordering, since the order in which we sink instructions
can affect the resulting codegen.
This helps removes a few vsetvli toggles in llvm-test-suite.
Commit: 027447c61724385ae82f0a8dea34b45da2fd4c39
https://github.com/llvm/llvm-project/commit/027447c61724385ae82f0a8dea34b45da2fd4c39
Author: Fangrui Song <i at maskray.me>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
A llvm/test/MC/ELF/relax-branch-align.s
Log Message:
-----------
[MC][test] Add relax-branch-align.s demonstrating unnecessary branch relaxation (#184551)
The two-pass relaxation approach (relaxFragment, then layoutSection)
can unnecessarily relax a backward branch from short (2B) to near (5B).
When a forward branch relaxes (2B->6B), it shifts the backward target
by +4B. A .p2align between target and source absorbs this growth. The
true displacement is -125 (fits short), but the two-pass approach
evaluates the backward branch with stale target offsets, seeing -129
(beyond [-128,127]) and relaxing it unnecessarily.
Commit: cd01e6526af6dbe2653d9a9e5589afe97b03b914
https://github.com/llvm/llvm-project/commit/cd01e6526af6dbe2653d9a9e5589afe97b03b914
Author: Fangrui Song <i at maskray.me>
Date: 2026-03-03 (Tue, 03 Mar 2026)
Changed paths:
M lld/ELF/Arch/LoongArch.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/Relocations.cpp
M lld/ELF/Relocations.h
Log Message:
-----------
[ELF] Add target-specific relocation scanning for LoongArch (#182236)
Implement LoongArch::scanSectionImpl, following the pattern established
for x86, PPC64, SystemZ, AArch64. This merges the getRelExpr and TLS
handling for SHF_ALLOC sections into the target-specific scanner,
enabling devirtualization and eliminating abstraction overhead.
- Inline relocation classification into scanSectionImpl with a switch
on relocation type, replacing the generic rs.scan() path.
- Use processR_PC/processR_PLT_PC for common PC-relative and PLT
relocations.
- Inline TLS handling: IE->LE optimization for _PC_ variants only (not
_PCADD_ or absolute), TLSDESC->IE/LE for non-extreme code model,
GD/LD flag setting without going through generic handleTlsRelocation.
- Remove adjustTlsExpr by inlining its logic into scanSectionImpl.
- Remove LoongArch-specific code from Relocations.cpp:
handleTlsRelocation, execOptimizeInLoongArch, and the sort condition.
- Simplify getRelExpr to only handle relocations needed by
relocateNonAlloc, scanEhSection, and the extreme code model fallback
in relocateAlloc.
Commit: debb2514ea7f062a29e5e4740f9d6ee4cea3b978
https://github.com/llvm/llvm-project/commit/debb2514ea7f062a29e5e4740f9d6ee4cea3b978
Author: Fangrui Song <i at maskray.me>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/include/llvm/MC/MCAssembler.h
M llvm/lib/MC/MCAssembler.cpp
M llvm/test/MC/ELF/relax-branch-align.s
A llvm/test/MC/X86/align-branch-convergence.s
Log Message:
-----------
[MC] Fuse relaxation and layout into a single forward pass (#184544)
Replace the two-pass inner loop in relaxOnce (relaxFragment +
layoutSection) with a single forward pass that sets each fragment's
offset before processing it.
- Extract relaxAlign from layoutSection's FT_Align handling and call
it from relaxFragment. FT_Align padding is computed inline with the
tracked Offset, so alignment fragments always see fresh upstream
offsets. This structurally eliminates the O(N) convergence pitfall
where stale offsets caused each iteration to fix only one more
alignment fragment.
- The new MCAssembler::Stretch field tracks the cumulative upstream size
delta. In evaluateFixup, for PCRel fixups during relaxation, Stretch
is added to forward-reference target values (LayoutOrder comparison).
This makes displacement = target_old - source_old, identical to the
old two-pass approach, preventing premature relaxation for
span-dependent instructions.
- FT_Fill/FT_Org removed from relaxFragment; `if (F.Offset != Offset) in
the fused loop detects their size changes.
- layoutSection is retained for initial layout and post-finishLayout.
This fixes the FT_BoundaryAlign linear time convergence issue reported
by #176535. In addition, backward branches near the short/near boundary
may benefit from tighter encoding when a .p2align between the target and
the branch absorbs upstream growth (see relax-branch-align.s).
Key commits that updated relaxFragment/layoutSection:
- 742ecfc13e8a [MC] Relax MCFillFragment and compute fragment offsets
eagerly
- 9f66ebe42715 MC: Eliminate redundant fragment relaxation
- df71243fa885 MC: Evaluate .org during fragment relaxation
- b1d58f025e83 MCAssembler: Simplify fragment relaxation
- 58d16db8b5d2 MCAssembler: Simplify relaxation of FT_Fill and FT_Org
Commit: 6fae863eba8a72cdd82f37e7111a46a70be525e0
https://github.com/llvm/llvm-project/commit/6fae863eba8a72cdd82f37e7111a46a70be525e0
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
M llvm/test/CodeGen/X86/reserveRreg.ll
Log Message:
-----------
[X86][APX] Add a few pseudo opcodes support EGPR (#184550)
Found in post testing in #180242
Commit: 6b59ad6e8d88eacde185160e20f662985f083d00
https://github.com/llvm/llvm-project/commit/6b59ad6e8d88eacde185160e20f662985f083d00
Author: Adam Siemieniuk <adam.siemieniuk at intel.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/test/Dialect/Linalg/data-layout-propagation.mlir
A mlir/test/Dialect/Linalg/td/propagate-data-layout.mlir
M mlir/test/lib/Dialect/Linalg/CMakeLists.txt
R mlir/test/lib/Dialect/Linalg/TestDataLayoutPropagation.cpp
M mlir/tools/mlir-opt/mlir-opt.cpp
Log Message:
-----------
[mlir][linalg] Data layout propagation test schedule (#184151)
Replaces data layout propagation test pass with equivalent transform
schedule.
The two required patterns are wrapped in new linalg transform ops
improving reusability.
Commit: 5b156a4372acb1c8dcc837211ede7216d1454de3
https://github.com/llvm/llvm-project/commit/5b156a4372acb1c8dcc837211ede7216d1454de3
Author: Steffen Larsen <sholstla at amd.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-acos.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-acosh.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-acospi.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-asin.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-asinh.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-asinpi.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-atan.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-atanh.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-atanpi.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cbrt.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cos.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cosh.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cospi.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-erf.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-erfc.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-exp.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-exp10.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-exp2.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-expm1.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-log.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-log10.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-log2.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-rsqrt.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sin.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sinh.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sinpi.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sqrt.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tan.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tanh.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tanpi.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tgamma.ll
Log Message:
-----------
[AMDGPU] Add half vector support for table-driven libcall optimization (#178638)
When replacing certain AMDGPU library calls with constant data vectors,
the existing implementation only handled single and double-precision
floats. This change extends the functionality to also support
half-precision floats.
Additionally, it refactors the function responsible for generating
constant float data vectors to improve readability and reduces code
duplication. In tandem with this refactoring, the patch relaxes the
check for constant data vectors to include any constant of vector type.
This allows other constant vectors to be processed, such as those
created from constant aggregate zeros (e.g. `<2 x float>
zeroinitializer`).
---------
Signed-off-by: Steffen Holst Larsen <sholstla at amd.com>
Commit: ae438677566397b947b987acaba170388c089017
https://github.com/llvm/llvm-project/commit/ae438677566397b947b987acaba170388c089017
Author: Ryotaro Kasuga <kasuga.ryotaro at fujitsu.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/include/llvm/Analysis/DependenceAnalysis.h
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/test/Analysis/DDG/print-dot-ddg.ll
M llvm/test/Analysis/DependenceAnalysis/Banerjee.ll
M llvm/test/Analysis/DependenceAnalysis/BasePtrBug.ll
M llvm/test/Analysis/DependenceAnalysis/Constraints.ll
M llvm/test/Analysis/DependenceAnalysis/DADelin.ll
M llvm/test/Analysis/DependenceAnalysis/DifferentOffsets.ll
M llvm/test/Analysis/DependenceAnalysis/ExactRDIV.ll
M llvm/test/Analysis/DependenceAnalysis/FlipFlopBaseAddress.ll
M llvm/test/Analysis/DependenceAnalysis/MIVCheckConst.ll
M llvm/test/Analysis/DependenceAnalysis/MismatchingNestLevels.ll
M llvm/test/Analysis/DependenceAnalysis/NonAffineExpr.ll
M llvm/test/Analysis/DependenceAnalysis/PR21585.ll
M llvm/test/Analysis/DependenceAnalysis/PR51512.ll
M llvm/test/Analysis/DependenceAnalysis/Preliminary.ll
M llvm/test/Analysis/DependenceAnalysis/Propagating.ll
M llvm/test/Analysis/DependenceAnalysis/SimpleSIVNoValidityCheck.ll
M llvm/test/Analysis/DependenceAnalysis/SimpleSIVNoValidityCheckFixedSize.ll
M llvm/test/Analysis/DependenceAnalysis/StrongSIV.ll
M llvm/test/Analysis/DependenceAnalysis/SymbolicRDIV.ll
M llvm/test/Analysis/DependenceAnalysis/SymbolicSIV.ll
M llvm/test/Analysis/DependenceAnalysis/UsefulGEP.ll
M llvm/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll
M llvm/test/Analysis/DependenceAnalysis/WeakZeroDstSIV.ll
M llvm/test/Analysis/DependenceAnalysis/WeakZeroSrcSIV.ll
M llvm/test/Analysis/DependenceAnalysis/ZIV.ll
M llvm/test/Analysis/DependenceAnalysis/becount-couldnotcompute.ll
M llvm/test/Analysis/DependenceAnalysis/compute-absolute-value.ll
M llvm/test/Analysis/DependenceAnalysis/exact-rdiv-addrec-wrap.ll
M llvm/test/Analysis/DependenceAnalysis/exact-siv-addrec-wrap.ll
M llvm/test/Analysis/DependenceAnalysis/exact-siv-overflow.ll
M llvm/test/Analysis/DependenceAnalysis/gcd-miv-overflow.ll
M llvm/test/Analysis/DependenceAnalysis/infer_affine_domain_ovlf.ll
M llvm/test/Analysis/DependenceAnalysis/lcssa.ll
M llvm/test/Analysis/DependenceAnalysis/monotonicity-cast.ll
M llvm/test/Analysis/DependenceAnalysis/monotonicity-invariant.ll
M llvm/test/Analysis/DependenceAnalysis/rdiv-large-btc.ll
M llvm/test/Analysis/DependenceAnalysis/rdiv-minor-algebra.ll
M llvm/test/Analysis/DependenceAnalysis/run-specific-dependence-test.ll
M llvm/test/Analysis/DependenceAnalysis/same-sd-for-diff-becount-type-loops.ll
M llvm/test/Analysis/DependenceAnalysis/strong-siv-large-btc.ll
M llvm/test/Analysis/DependenceAnalysis/strong-siv-overflow.ll
M llvm/test/Analysis/DependenceAnalysis/symbolic-rdiv-addrec-wrap.ll
M llvm/test/Analysis/DependenceAnalysis/symbolic-rdiv-overflow.ll
M llvm/test/Analysis/DependenceAnalysis/weak-crossing-siv-addrec-wrap.ll
M llvm/test/Analysis/DependenceAnalysis/weak-crossing-siv-large-btc.ll
M llvm/test/Analysis/DependenceAnalysis/weak-crossing-siv-overflow.ll
M llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-large-btc.ll
M llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-overflow.ll
M llvm/test/Analysis/DependenceAnalysis/weak_zero_siv_parametric_coeff.ll
M llvm/test/Analysis/DependenceAnalysis/weak_zero_siv_parametric_const.ll
M llvm/test/Analysis/DependenceAnalysis/zero-coefficient.ll
Log Message:
-----------
[DA] Remove consistent flag from Dependence class (#181608)
The `Dependence` class has a flag `Consistent`, but it's not clear what
it represents. This flag doesn't seem to be updated correctly during
analysis. There are no users of it, so I think this flag would be
unnecessary.
In addition, because of this flag, even minor code changes can alter
test results unintentionally (specifically, the presence/absence of a
string "consistent" in the test output). Such test changes can be
confusing and gradually add to the maintenance burden.
Given these points, it's better to remove the `Consistent` flag from the
`Dependence` class entirely.
Commit: c612c98fa6dc613ebc1350cc1d87c8cd5d840428
https://github.com/llvm/llvm-project/commit/c612c98fa6dc613ebc1350cc1d87c8cd5d840428
Author: Mel Chen <mel.chen at sifive.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
Log Message:
-----------
[VPlan] Add const to VPPredicator methods. nfc (#184359)
Add const to VPBasicBlock pointer parameters and cache key types where
the blocks are not modified.
Commit: deb70a6d643d090c0fcff7be940ce9513c1b5f77
https://github.com/llvm/llvm-project/commit/deb70a6d643d090c0fcff7be940ce9513c1b5f77
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Transforms/InstCombine/getelementptr.ll
Log Message:
-----------
[InstCombine] Don't strip leading zero index for overaligned vector GEP (#184364)
In this case the stride is not equal to the type alloc size.
Fixes issue reported in:
https://github.com/llvm/llvm-project/pull/180745#discussion_r2860093376
Commit: 9a821584a5165809fdfeffdb086d398e7a66e101
https://github.com/llvm/llvm-project/commit/9a821584a5165809fdfeffdb086d398e7a66e101
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/lib/AST/ByteCode/Program.cpp
M clang/lib/AST/ByteCode/Record.cpp
Log Message:
-----------
[clang][bytecode] Fix a mishap in HasPtrField calculation (#184557)
The Record constructor has a parameter and a class member of the same
name. Also include composite array element types in the calculation in
Program.cpp.
Commit: 7fbc0734f5b38f49d21addf5b400319f2aaff07d
https://github.com/llvm/llvm-project/commit/7fbc0734f5b38f49d21addf5b400319f2aaff07d
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/Program.cpp
Log Message:
-----------
[clang][bytecode] Fix a few comment typos (#184561)
Commit: 2be2926b56ea8c69a6ef5a9e1cb47033617ba268
https://github.com/llvm/llvm-project/commit/2be2926b56ea8c69a6ef5a9e1cb47033617ba268
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Analysis/Loads.cpp
M llvm/unittests/Analysis/LoadsTest.cpp
Log Message:
-----------
[Loads] Allow replacement of null with ptr in `canReplacePointersIfEqual`
It should always be valid to allow the replacement of null with the
destination pointer, as moving from nullary provenance to a non-nullary
one preserves provenance monotonicity.
Commit: 52dd63d3caa377b993855e1161cfde2e55fafe8c
https://github.com/llvm/llvm-project/commit/52dd63d3caa377b993855e1161cfde2e55fafe8c
Author: jumerckx <31353884+jumerckx at users.noreply.github.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M mlir/include/mlir/IR/OperationSupport.h
M mlir/lib/IR/OperationSupport.cpp
M mlir/test/IR/operation-equality.mlir
M mlir/test/lib/IR/TestOperationEquals.cpp
Log Message:
-----------
[mlir] Add option to ignore commutativity in OperationEquality (#181507)
This adds a new flag, `IgnoreCommutativity`, to the OperationEquivalence
flags. When toggled, regular equivalence and hashing will be used
instead of calls to `checkCommutativeEquivalent` and
commutative-invariant hashing.
This means that commutative operations will not be considered equivalent
when their operands are in a different order (i.e. `arith.addi(%a, %b)`
vs. `arith.addi(%b, %a)`).
Commit: 3bb4a506c590a6645db96b40f238ccd1a1353a57
https://github.com/llvm/llvm-project/commit/3bb4a506c590a6645db96b40f238ccd1a1353a57
Author: hanbeom <kese111 at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrCall.td
M llvm/test/CodeGen/WebAssembly/call-pic.ll
M llvm/test/CodeGen/WebAssembly/call.ll
M llvm/test/CodeGen/WebAssembly/function-bitcasts.ll
M llvm/test/CodeGen/WebAssembly/multivalue.ll
M llvm/test/CodeGen/WebAssembly/reg-stackify.ll
M llvm/test/CodeGen/WebAssembly/swiftcc.ll
M llvm/test/CodeGen/WebAssembly/tailcall.ll
Log Message:
-----------
[WebAssembly] Print type signature and table for call_indirect (#179120)
Update WebAssemblyInstPrinter.cpp to correctly print type
and table operands for both register and stack modes.
Commit: c9355cc121dfb1a0876547c5f68946eb4fc7ca01
https://github.com/llvm/llvm-project/commit/c9355cc121dfb1a0876547c5f68946eb4fc7ca01
Author: Fangrui Song <i at maskray.me>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M lld/ELF/Arch/ARM.cpp
M lld/ELF/SyntheticSections.h
Log Message:
-----------
[ELF] Move ArmCmseSGSection into Arch/ARM.cpp (#184570)
Move the ArmCmseSGVeneer and ArmCmseSGSection class definitions from
SyntheticSections.h into the anonymous namespace in Arch/ARM.cpp, where
the implementations already reside. Rename ArmCmseSGVeneer to
CmseSGVeneer as it no longer needs the Arm prefix for disambiguation.
Commit: 8fcb60aa47e792641dcbe6dcaa8b4a822a565cfc
https://github.com/llvm/llvm-project/commit/8fcb60aa47e792641dcbe6dcaa8b4a822a565cfc
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M libcxx/include/string
Log Message:
-----------
[libc++][NFC] Introduce __data() to std::string to replace std::__to_address(__get_pointer()) (#178212)
`std::__to_address(__get_pointer())` is an extremely common pattern
inside `string` and is basically equivalent to `data()`, except that
`data()` only returns a non-const pointer since C++17. This patch
introduces `__data()` to back-port returning a non-const pointer.
Commit: b86f24fd0ed47238ddfa1292bbd89d1ec10d774c
https://github.com/llvm/llvm-project/commit/b86f24fd0ed47238ddfa1292bbd89d1ec10d774c
Author: Kiva <imkiva at islovely.icu>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Transforms/InstCombine/binop-phi-operands.ll
M llvm/test/Transforms/InstCombine/fmul.ll
M llvm/test/Transforms/InstCombine/icmp-binop.ll
M llvm/test/Transforms/InstCombine/or-select-zero-icmp.ll
M llvm/test/Transforms/InstCombine/recurrence.ll
M llvm/test/Transforms/InstCombine/select.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
Log Message:
-----------
[InstCombine] make `foldBinOpIntoSelectOrPhi` fold on all operands (#183692)
This PR makes `foldBinOpIntoSelectOrPhi` fold to select/phi both for
operands 0 and 1.
Alive2: https://alive2.llvm.org/ce/z/T56TMM
Also fixes #183498
Commit: e7db3f1d3df66e8d0e0adb13b14099e64b124f5a
https://github.com/llvm/llvm-project/commit/e7db3f1d3df66e8d0e0adb13b14099e64b124f5a
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
M llvm/test/Transforms/DeadStoreElimination/noop-stores.ll
Log Message:
-----------
[DSE] Handle provenance when eliminating tautological assignments
Similarly to what already being done in GVN (fb632ed2377d280b581b8d4653b855e60d611f77),
when a dominating equality condition of two pointers holds, and the
value being stored is implied by such a condition, ensure the store
may be removed by leveraging `canReplacePointersIfEqual`, subject to
the known approximations.
Fixes: https://github.com/llvm/llvm-project/issues/184088.
Commit: 1a7502592f0f8318b90d320621aa0026662669a1
https://github.com/llvm/llvm-project/commit/1a7502592f0f8318b90d320621aa0026662669a1
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/test/CodeGen/ARM/vminmaxnm-safe.ll
Log Message:
-----------
[ARM] Generate test checks (NFC) (#184574)
I had to rename some functions to make them UTC compatible.
Commit: a636928bb4db9d78e32af0a27e048687506af841
https://github.com/llvm/llvm-project/commit/a636928bb4db9d78e32af0a27e048687506af841
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/include/llvm/ADT/APFloat.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Support/APFloat.cpp
A llvm/test/CodeGen/AMDGPU/arbitrary-fp-to-float.ll
A llvm/test/CodeGen/NVPTX/arbitrary-fp-to-float.ll
A llvm/test/CodeGen/X86/arbitrary-fp-convert-error.ll
A llvm/test/CodeGen/X86/arbitrary-fp-to-float.ll
Log Message:
-----------
[SelectionDAG] Add expansion for llvm.convert.from.arbitrary.fp (#179318)
The expansion converts arbitrary-precision FP represented as integer
following these algorithm:
1. Extract sign, exponent, and mantissa bit fields via masks and shifts.
2. Classify the input (zero, denormal, normal, Inf, NaN) using the
exponent and mantissa fields.
3. Normal path: adjusting the exponent bias and left-shifting the
mantissa to fit the wider destination format.
4. Denormal path: normalizing by finding the MSB position of the
mantissa (via count-leading-zeros), computing the correct exponent from
that position, stripping the implicit leading 1, and shifting the
fraction into the destination mantissa field.
5. Assemble the destination IEEE bit pattern (sign | exponent |
mantissa) and select among the normal, denormal, and special-value
results.
Currently only conversions from OCP floats are covered, in LLVM terms
these are: Float8E5M2, Float8E4M3FN, Float6E3M2FN, Float6E2M3FN,
Float4E2M1FN.
OCP spec:
https://www.opencompute.org/documents/ocp-microscaling-formats-mx-v1-0-spec-final-pdf
AI has assisted in X86 E2E testing.
Commit: 3d52f0c539d8b5a372becdb40a651baa78c5fa9a
https://github.com/llvm/llvm-project/commit/3d52f0c539d8b5a372becdb40a651baa78c5fa9a
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/test/CodeGen/SPIRV/transcoding/OpExtInst_vector_promotion_bug.ll
A llvm/test/CodeGen/SPIRV/user-function-with-builtin-name.ll
Log Message:
-----------
[SPIR-V] Don't consider a function be a builtin just by checking name (#182776)
If a function has the same name as a (n OpenCL) builtin, but not
matching number of arguments to the builtin - consider it to be a user
function.
Fixes: https://github.com/llvm/llvm-project/issues/165237
Commit: 31f69d333e4906a9180ee76e48096e3d1a1f1234
https://github.com/llvm/llvm-project/commit/31f69d333e4906a9180ee76e48096e3d1a1f1234
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/utils/libctest/format.py
Log Message:
-----------
[libc] Fix integration test args/env in LibcTest lit format (#184438)
Integration tests with ARGS or ENV in their add_integration_test() call
were being run with no arguments or environment variables by the
LibcTest lit format, causing failures in startup_args_test,
sprintf_size_test, getenv_test, execv_test, execve_test, and
getcwd_test.
Fix this by having add_integration_test() emit a sidecar
<executable>.params JSON file (via file(GENERATE)) whenever ARGS or ENV
are specified. LibcTest.execute() reads this file at test time and
passes the args and environment to the test executable.
Also always set PWD=exec_dir in the test environment so that
getenv("PWD") matches getcwd() for tests that compare them.
Commit: 732f66eccc24fc90c9fe9df65bfbe3ddedf220fc
https://github.com/llvm/llvm-project/commit/732f66eccc24fc90c9fe9df65bfbe3ddedf220fc
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M libclc/clc/lib/amdgcn/workitem/clc_get_global_offset.cl
M libclc/clc/lib/amdgcn/workitem/clc_get_work_dim.cl
M libclc/cmake/modules/AddLibclc.cmake
Log Message:
-----------
libclc: Reimplement amdhsa workitem functions (#184571)
These were quite out of date and broken. These were originally
implemented for clover, which at one point was aiming for HSA v2 ABI
near compatibility. Since clover has been removed, that path is dead.
This was also broken for the modern HSA ABIs. Update to assume the
v5 ABI.
Commit: b6761b287f6b58a0f25849f5a0b4c97fee4b6d75
https://github.com/llvm/llvm-project/commit/b6761b287f6b58a0f25849f5a0b4c97fee4b6d75
Author: mitchell <mitchell.xu2 at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
A clang-tools-extra/test/clang-tidy/checkers/bugprone/implicit-widening-of-multiplication-result-options.cpp
A clang-tools-extra/test/clang-tidy/checkers/bugprone/not-null-terminated-result-no-safe-functions.c
A clang-tools-extra/test/clang-tidy/checkers/bugprone/signed-char-misuse-no-comparison.cpp
A clang-tools-extra/test/clang-tidy/checkers/bugprone/sizeof-expression-disable-options.cpp
A clang-tools-extra/test/clang-tidy/checkers/bugprone/string-constructor-options.cpp
A clang-tools-extra/test/clang-tidy/checkers/bugprone/suspicious-missing-comma-options.cpp
A clang-tools-extra/test/clang-tidy/checkers/bugprone/suspicious-string-compare-custom-functions.cpp
A clang-tools-extra/test/clang-tidy/checkers/bugprone/suspicious-stringview-data-usage-options.cpp
A clang-tools-extra/test/clang-tidy/checkers/bugprone/unused-return-value-checked-return-types.cpp
Log Message:
-----------
[clang-tidy][NFC] Add missing Option tests in `bugprone` [1/N] (#184015)
This PR adds testcases for untested Options in `bugprone` module for
better test coverage, specifically:
- `bugprone-implicit-widening-of-multiplication-result`:
`UseCXXHeadersInCppSources` and `IncludeStyle`.
- `bugprone-not-null-terminated-result`: `WantToUseSafeFunctions`
- `bugprone-signed-char-misuse`: `DiagnoseSignedUnsignedCharComparisons`
- `bugprone-sizeof-expression`: `WarnOnSizeOfConstant`,
`WarnOnSizeOfThis`, `WarnOnSizeOfCompareToConstant`,
`WarnOnSizeOfInLoopTermination`.
- `bugprone-string-constructor`: `WarnOnLargeLength`,
`LargeLengthThreshold`, `StringNames`.
- `bugprone-suspicious-missing-comma`: `SizeThreshold`,
`RatioThreshold`, `MaxConcatenatedTokens`.
- `bugprone-suspicious-string-compare`: `StringCompareLikeFunctions`
- `bugprone-suspicious-stringview-data-usage`: `StringViewTypes`,
`AllowedCallees`
As of AI Usage: Assisted by Gemini 3 and Claude (Writing part of the
testcases and pre-commit reviewing).
Commit: 14af5be5da77a90acbc2d5d47488d9400d7cfed7
https://github.com/llvm/llvm-project/commit/14af5be5da77a90acbc2d5d47488d9400d7cfed7
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M lldb/docs/dil-expr-lang.ebnf
M lldb/include/lldb/ValueObject/DILAST.h
M lldb/include/lldb/ValueObject/DILEval.h
M lldb/source/ValueObject/DILAST.cpp
M lldb/source/ValueObject/DILEval.cpp
M lldb/source/ValueObject/DILParser.cpp
M lldb/test/API/commands/frame/var-dil/basics/BitFieldExtraction/TestFrameVarDILBitFieldExtraction.py
M lldb/test/API/commands/frame/var-dil/expr/Arithmetic/TestFrameVarDILArithmetic.py
M lldb/test/API/commands/frame/var-dil/expr/Arithmetic/main.cpp
Log Message:
-----------
[lldb] Add arithmetic binary subtraction to DIL (#184017)
Commit: c62d5f35b6785ff1fac0047c6e5d9e6dd8f745f8
https://github.com/llvm/llvm-project/commit/c62d5f35b6785ff1fac0047c6e5d9e6dd8f745f8
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h
M llvm/test/CodeGen/AArch64/combine-sdiv.ll
A llvm/test/CodeGen/AArch64/extend_vecreduce_add.ll
Log Message:
-----------
[AArch64] Avoid folding sign-extend of vector extracts into ALU ops (#183522)
This breaks a tie where the `SEXT_IN_REG` in an expression like
`SUB(0, SEXT_IN_REG(VECTOR_EXTRACT(..))` can fold into the `SUB` or the
`VECTOR_EXTRACT`. Currently, the `SUB` is always preferred, but it's
better to fold the `SEXT_IN_REG` into the `VECTOR_EXTRACT` extract,
which allows for `SMOV` to be used.
Commit: 9cc0df99de853a3cdf778c0c33e4fb5050c46c5b
https://github.com/llvm/llvm-project/commit/9cc0df99de853a3cdf778c0c33e4fb5050c46c5b
Author: Devajith <devajith.valaparambil.sreeramaswamy at cern.ch>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/lib/Frontend/VerifyDiagnosticConsumer.cpp
M clang/lib/Interpreter/IncrementalParser.cpp
A clang/test/Interpreter/verify-diagnostics.cpp
Log Message:
-----------
[clang-repl] Create virtual files for `input_line_N` buffers (#182044)
Instead of using memory buffers without file backing, this patch
`input_line_N` buffers as virtual files.
This patch enables us to use input line numbers when verifying tests
`clang-repl`.
Co-authored-by: Vassil Vassilev <v.g.vassilev at gmail.com>
Commit: 756d068ead7e8d3b158ddc7b0f806da8a357b378
https://github.com/llvm/llvm-project/commit/756d068ead7e8d3b158ddc7b0f806da8a357b378
Author: Rolf Morel <rolf.morel at intel.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M mlir/include/mlir-c/Dialect/Transform.h
M mlir/include/mlir-c/Rewrite.h
M mlir/lib/Bindings/Python/DialectTransform.cpp
M mlir/lib/Bindings/Python/Rewrite.cpp
M mlir/lib/Bindings/Python/Rewrite.h
M mlir/lib/CAPI/Dialect/Transform.cpp
M mlir/lib/CAPI/Transforms/Rewrite.cpp
A mlir/test/python/dialects/transform_pattern_descriptor_op_interface.py
Log Message:
-----------
[MLIR][Python][Transform] Expose PatternDescriptorOpInterface to Python (#184331)
Makes it possible to include Python-defined rewrite patterns in
transform-dialect schedules, inside of `transform.apply_patterns`, which
upon execution of the schedule runs the pattern in a greedy rewriter.
With assistance of Claude.
Commit: d737cd505562228b9c5f9e57b7d7f3786773ab26
https://github.com/llvm/llvm-project/commit/d737cd505562228b9c5f9e57b7d7f3786773ab26
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang-tools-extra/clangd/Preamble.cpp
M clang-tools-extra/clangd/XRefs.cpp
Log Message:
-----------
[clang-tools-extra] Turn misc copy-assign into move-assign (#184146)
That's an automated patch generated from clang-tidy
performance-use-std-move as a follow-up to #184136
Commit: 1582dd9c31d5f0f3d234d165b0a770b8118f6a48
https://github.com/llvm/llvm-project/commit/1582dd9c31d5f0f3d234d165b0a770b8118f6a48
Author: David Spickett <david.spickett at arm.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M lldb/source/Commands/CommandObjectApropos.cpp
M lldb/source/Commands/CommandObjectBreakpointCommand.cpp
M lldb/source/Commands/CommandObjectPlatform.cpp
M lldb/source/Commands/CommandObjectSource.cpp
M lldb/source/Commands/CommandObjectType.cpp
M lldb/source/Commands/CommandObjectVersion.cpp
M lldb/source/Commands/CommandObjectWatchpointCommand.cpp
M lldb/source/Plugins/LanguageRuntime/CPlusPlus/ItaniumABI/ItaniumABILanguageRuntime.cpp
Log Message:
-----------
[lldb] Change more uses of AppendMessageWithFormat to AppendMessageWithFormatv (#184337)
When the message includes a final newline, Formatv can add that for you.
The only unusual change is one place in platform where we need to print
octal. LLVM doesn't have a built in way to do this (see
llvm/include/llvm/Support/FormatProviders.h) and this is probably the
only place in the codebase that wants to. So I decided not to add it
there.
Instead I've put the number info a format adapter with the normal printf
specifier, then put that into the Formatv format.
Commit: 6bdf076137d0cd7f4490522751c0e07efdd4d5e4
https://github.com/llvm/llvm-project/commit/6bdf076137d0cd7f4490522751c0e07efdd4d5e4
Author: Henry Baba-Weiss <henry.babaweiss at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/LangOptions.h
M clang/lib/Basic/Targets/OSTargets.cpp
M clang/test/Preprocessor/predefined-win-macros.c
Log Message:
-----------
[clang] Predefine `_MSVC_TRADITIONAL` in MSVC compatibility mode (#184278)
As of version 19.15 (Visual Studio 2017 version 15.8), MSVC predefines
the `_MSVC_TRADITIONAL` macro to indicate whether it is using the old
"traditional" preprocessor or the new standards-conforming preprocessor.
Clang now predefines `_MSVC_TRADITIONAL` as 1 when emulating MSVC 19.15
or later, since Clang supports most traditional preprocessor behaviors
(e.g. `/##/` turning into `//`) when running in MSVC compatibility mode.
Currently there isn't a situation where it makes sense for Clang to
report `_MSVC_TRADITIONAL` as 0, since MSVC compatibility mode only
attempts to be compatible with the traditional MSVC preprocessor.
However, this does mean that clang-cl cannot match MSVC's behavior of
implicitly enabling the conforming C preprocessor when compiling with
`/std:c11`, `/std:c17`, or `/std:clatest`.
Fixes #47114
Commit: 177211a99f70d21fb73e1417d51cf86b1d1e4dd5
https://github.com/llvm/llvm-project/commit/177211a99f70d21fb73e1417d51cf86b1d1e4dd5
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-fmax-safe.ll
Log Message:
-----------
[AArch64] Generate test checks (NFC) (#184582)
Commit: 2aab31a94e7b9eb0c66d3a9639e987a257efc444
https://github.com/llvm/llvm-project/commit/2aab31a94e7b9eb0c66d3a9639e987a257efc444
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/test/CodeGen/X86/combine-fcopysign.ll
Log Message:
-----------
[X86] combine-fcopysign.ll - extend test coverage to all x86-64/x86-64-v2/x86-64-v3/x86-64-v4 levels (#184579)
Commit: f702ee89c1d72fa5ff9b3b9b4e58f4f41321419b
https://github.com/llvm/llvm-project/commit/f702ee89c1d72fa5ff9b3b9b4e58f4f41321419b
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Fix partially uninitialized accesses after 17aaa0e590a7. (#184583)
17aaa0e590a7 adjusted how parts of the union members are managed. Make
sure the full union is initialized, to fix MSan failure in
https://lab.llvm.org/buildbot/#/builders/164/builds/19313.
Commit: f1aa7c3c5fc9d818ccef49a919cf5f9a42a64e28
https://github.com/llvm/llvm-project/commit/f1aa7c3c5fc9d818ccef49a919cf5f9a42a64e28
Author: Fedor Nikolaev <fridrixnm at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp
M mlir/test/Dialect/ControlFlow/canonicalize.mlir
Log Message:
-----------
[mlir][cf] Canonicalize block args with uniform incoming values (#183966)
Add a canonicalization pattern that replaces block arguments with a
common SSA value when all predecessors pass the same value for that
argument. This allows the block argument to be removed by dead code
elimination. First itteration
Idea from #182711
Commit: 8ac00ba7f9f1b50732ae568de8ed44cce9b2a303
https://github.com/llvm/llvm-project/commit/8ac00ba7f9f1b50732ae568de8ed44cce9b2a303
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M mlir/lib/Conversion/SCFToEmitC/SCFToEmitC.cpp
M mlir/test/Conversion/SCFToEmitC/scf-to-emitc-failed.mlir
Log Message:
-----------
[mlir][SCFToEmitC] Fix crash when scf.while carries a memref loop variable (#183944)
When a scf.while op has a loop-carried value whose type converts to
emitc::ArrayType (e.g. memref<1xf64>), the WhileLowering pattern
unconditionally called emitc::LValueType::get(arrayType), which
triggered an assertion because LValueType cannot wrap an array type.
Fix by returning a match failure in createVariablesForResults and
createVariablesForLoopCarriedValues when the converted type is an
emitc::ArrayType. This converts the crash into a proper legalization
failure.
Fixes #182649
Commit: de5e081a833910ec33e8017b6be8247a7788ee27
https://github.com/llvm/llvm-project/commit/de5e081a833910ec33e8017b6be8247a7788ee27
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M flang/test/Lower/Intrinsics/adjustr.f90
M flang/test/Lower/Intrinsics/all.f90
M flang/test/Lower/Intrinsics/any.f90
M flang/test/Lower/Intrinsics/asinpi.f90
M flang/test/Lower/Intrinsics/associated.f90
Log Message:
-----------
[flang][NFC] Converted five tests from old lowering to new lowering (part 23) (#184533)
Tests converted from test/Lower/Intrinsics: adjustr.f90, all.f90,
any.f90, asinpi.f90, associated.f90
Commit: d0f50d55746aa27e6467cb2bce66596da9da065b
https://github.com/llvm/llvm-project/commit/d0f50d55746aa27e6467cb2bce66596da9da065b
Author: Mirko Brkušanin <Mirko.Brkusanin at amd.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/test/CodeGenOpenCL/amdgpu-ieee.cl
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCKernelDescriptor.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.cpp
M llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.cpp
M llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-default.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll
A llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp-on.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll
M llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll
M llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
M llvm/test/MC/AMDGPU/hsa-diag-v4.s
M llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-dx10-clamp.ll
M llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-ieee.ll
Log Message:
-----------
[AMDGPU] Remove DX10_CLAMP and IEEE bits from gfx1170 (#182107)
Add `DX10ClampAndIEEEMode` feature and set it for every subtarget prior
to gfx1170
Commit: 943eb6fd958e8b130ee94f5c65b7d53ec3419acc
https://github.com/llvm/llvm-project/commit/943eb6fd958e8b130ee94f5c65b7d53ec3419acc
Author: Graham Hunter <graham.hunter at arm.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/test/Transforms/LoopVectorize/find-last.ll
Log Message:
-----------
[LV] Use make_early_inc_range in handleFindLastReductions (#184340)
Fixes #182152
Commit: ee92ac2343f6e0ff787bbe660c9a9293caa5269c
https://github.com/llvm/llvm-project/commit/ee92ac2343f6e0ff787bbe660c9a9293caa5269c
Author: Jueon Park <79134656+JueonPark at users.noreply.github.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M mlir/lib/Dialect/NVGPU/Transforms/OptimizeSharedMemory.cpp
M mlir/test/Dialect/NVGPU/optimize-shared-memory.mlir
Log Message:
-----------
[mlir][nvgpu] Fix crash in optimize-shared-memory pass with vector element types (#179111)
The `--nvgpu-optimize-shared-memory` pass crashed when processing
memrefs with vector element types (e.g., `memref<16x1xvector<16xf16>,
3>`). This occurred because getElementTypeBitWidth() calls
getIntOrFloatBitWidth(), which asserts the element type must be an
integer or float.
Thus, this PR adds an early-exit guard to return failure() when the
memref's element type is not a scalar int or float.
I wasn't sure if we should support vector types (by multiplying element
bit width by vector length) or just reject them. For now, I've
implemented it to return failure on non-scalar types.
Fixes #177823
Co-authored-by: rebel-jueonpark <jueonpark at rebellions.ai>
Commit: 7f044944e43eab4f5f52664a9022b1cc083ab258
https://github.com/llvm/llvm-project/commit/7f044944e43eab4f5f52664a9022b1cc083ab258
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/test/Dialect/Arith/canonicalize.mlir
M mlir/test/Dialect/Arith/invalid.mlir
M mlir/test/Dialect/Vector/invalid.mlir
Log Message:
-----------
[MLIR][Arith][Vector] Reject i0 integer type in arith and vector ops (#183589)
Add ODS type constraints that exclude zero-bitwidth integers (i0) from
operations in the arith and vector dialects. i0 has no meaningful
arithmetic representation and operations on it can trigger undefined
behavior (e.g. bitwidth calculations assuming non-zero width).
Changes:
- Add `AnyNonZeroBitwidthSignlessInteger` (as a `ConfinedType` over
`AnySignlessInteger`) and `AnyNonZeroBitwidthSignlessIntegerOrIndex`
to CommonTypeConstraints.td.
- Introduce `Arith_SignlessIntegerOrIndexLike` in ArithOps.td that wraps
`AnyNonZeroBitwidthSignlessIntegerOrIndex` via
`TypeOrValueSemanticsContainer`, and update
`SignlessFixedWidthIntegerLike`
to use `AnyNonZeroBitwidthSignlessInteger`. Replace all uses of the
shared `SignlessIntegerOrIndexLike` in ArithOps.td with the new
dialect-local constraint.
- Update `IndexCastTypeConstraint` to use
`Arith_SignlessIntegerOrIndexLike`.
- Update `BitcastTypeConstraint` to exclude i0 by composing the already-
defined `SignlessFixedWidthIntegerLike` and `FloatLike` constraints,
keeping the definition compact (3 alternatives instead of 7).
- Add `AnyVectorOfNonI0Elem` and `AnyVectorOfNonZeroRankNonI0Elem` in
VectorOps.td and apply them to `vector.contract`, `vector.reduction`,
`vector.multi_reduction`, `vector.outerproduct`, `vector.bitcast`, and
`vector.scan`.
- Update arith/invalid.mlir with explicit i0 rejection tests covering
all
integer op families (binary ops, cast ops, extended-multiply ops, cmpi,
bitcast, index_cast, index_castui) for both scalar and vector<N> forms.
- Update vector/invalid.mlir with i0 rejection tests for all covered
ops.
- Remove the now-invalid i0 canonicalization tests from
arith/canonicalize.mlir.
Fixes #177822
Fixes #179266
Fixes #180463
Fixes #181532
See also
https://discourse.llvm.org/t/rfc-reject-i0-integer-type-in-arith-and-vector-ops/90011
Commit: 9c2829f2e1883a8634edf4008f1cbc5928c63eeb
https://github.com/llvm/llvm-project/commit/9c2829f2e1883a8634edf4008f1cbc5928c63eeb
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M mlir/lib/Dialect/Func/IR/FuncOps.cpp
M mlir/test/Dialect/Func/invalid.mlir
M mlir/test/IR/test-region-branch-op-verifier.mlir
Log Message:
-----------
[mlir][Func] Use getMutableSuccessorOperands() in FuncOp verifier (#184589)
When verifying return-like terminators, use
getMutableSuccessorOperands() instead of getNumOperands() so that only
the operands passed to the parent region are checked against the
function result types. This handles terminators that implement
RegionBranchTerminatorOpInterface and carry additional operands for
other successor regions (e.g. loop back-edges).
Add tests using test.loop_block_term, which has both an iter operand
(passed back to the region) and an exit operand (passed to the parent).
Commit: ee8184573f03fde4aa642d2f90254096477d9805
https://github.com/llvm/llvm-project/commit/ee8184573f03fde4aa642d2f90254096477d9805
Author: jeanPerier <jperier at nvidia.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M flang/lib/Lower/PFTBuilder.cpp
M flang/test/Lower/OpenMP/target.f90
M flang/test/Lower/do-while-to-scf-while.f90
M flang/test/Lower/loops.f90
M flang/test/Lower/mixed_loops.f90
M flang/test/Lower/pre-fir-tree02.f90
M flang/test/Lower/while_loop.f90
Log Message:
-----------
Revert "[flang] make lowering to scf.while default" (#184592)
Reverts llvm/llvm-project#184234
This is breaking SPEC and other tests.
Reproducer:
```
subroutine foo()
logical :: l1, l2
do while (l1())
if (l2()) then
call bar()
endif
enddo
end
```
The cause is a pass ordering issue between the SCFToControlFlowPass and
CfgConversionPass
[here](https://github.com/llvm/llvm-project/blob/d0f50d55746aa27e6467cb2bce66596da9da065b/flang/lib/Optimizer/Passes/Pipelines.cpp#L239-L240).
I think they need to be run simultaneously somehow because the both SCF
and FIR structured operations may contain each other, and none will be
happy to get block CFG generated inside their region by the pass
lowering the other.
Reverting while this is sorted out.
Commit: 0a1e39517b229592c9a36eb366b0f70b73f1b4f3
https://github.com/llvm/llvm-project/commit/0a1e39517b229592c9a36eb366b0f70b73f1b4f3
Author: Ella Ma <alansnape3058 at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/test/Analysis/missing-z3-nocrash.c
M clang/test/lit.cfg.py
Log Message:
-----------
[nfc][analyzer][test][z3] Replace "REQUIRES: no-z3" with "UNSUPPORTED: z3" (#184349)
Fixing D120325, continuing #183724
Lit feature "no-z3" is the opposite of "z3", requiring "no-z3" is the
same as unsupporting "z3".
Commit: 1f4074b771bea3e29c9efbbd3d22689e62773af1
https://github.com/llvm/llvm-project/commit/1f4074b771bea3e29c9efbbd3d22689e62773af1
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
M mlir/test/Dialect/LLVMIR/sroa.mlir
Log Message:
-----------
[mlir][llvm] Fix SROA crash on empty LLVM struct types (#184596)
When SROA runs on an alloca of an empty struct type (llvm.struct<()>),
it crashes with:
Assertion `\!subelementIndexMap->empty()' failed.
The root cause is in LLVMStructType::getSubelementIndexMap(): for an
empty struct (no body fields), the loop doesn't execute and an empty
DenseMap is returned as a non-null optional. Later, getTypeAtIndex()
asserts the map is non-empty, triggering the crash.
Fix this by returning std::nullopt for empty structs, indicating they
cannot be destructured. This is consistent with how LLVMArrayType
handles the zero-element case.
Fixes #108366
Commit: c2784e11cc4405cbc64d1928cbcabbbd0759777b
https://github.com/llvm/llvm-project/commit/c2784e11cc4405cbc64d1928cbcabbbd0759777b
Author: Phoebe Linck <phoebelinck at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Semantics/OpenMP/resolve05.f90
Log Message:
-----------
[Flang][OpenMP] DEFAULT(NONE) error checking on implicit references (#182214)
A variable with an unspecified data-sharing attribute under a
DEFAULT(NONE) clause only emits an error if the variable is explicitly
referenced in the body of the construct with DEFAULT(NONE).
Ex:
```
!$omp parallel default(none)
!$omp task
a = 1
!$omp end task
!$omp end parallel
end
```
gfortran will error with `‘a’ not specified in enclosing ‘parallel’` on
the above. flang doesn't error.
Fix moves the error check to `CreateImplicitSymbols` and checks the
variable for a violation in any of its enclosing contexts.
Commit: 095e1694d9c095ab6b1f515811ea968e6f8f712d
https://github.com/llvm/llvm-project/commit/095e1694d9c095ab6b1f515811ea968e6f8f712d
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/Randstruct.cpp
M clang/lib/Basic/FileManager.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/Driver/CreateASTUnitFromArgs.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/OffloadBundler.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Lex/LiteralSupport.cpp
M clang/lib/Lex/PPExpressions.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/StaticAnalyzer/Checkers/IvarInvalidationChecker.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineCXX.cpp
M clang/lib/Tooling/DependencyScanningTool.cpp
Log Message:
-----------
[clang] Turn misc copy-assign to move-assign (#184144)
That's an automated patch generated from clang-tidy
performance-use-std-move as a follow-up to #184136
Commit: 8bb41c929f3ab6687a8681c5376f9078e4646878
https://github.com/llvm/llvm-project/commit/8bb41c929f3ab6687a8681c5376f9078e4646878
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
Log Message:
-----------
AMDGPU: Fix copy of Triple (#184594)
Commit: 98ed41718b0f2dfafdb2e54ad7c34f14ebcfdbc3
https://github.com/llvm/llvm-project/commit/98ed41718b0f2dfafdb2e54ad7c34f14ebcfdbc3
Author: Graham Hunter <graham.hunter at arm.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/AArch64/early_exit_with_stores.ll
A llvm/test/Transforms/LoopVectorize/RISCV/early_exit_with_stores.ll
A llvm/test/Transforms/LoopVectorize/VPlan/early_exit_with_stores_vplan.ll
M llvm/test/Transforms/LoopVectorize/early_exit_store_legality.ll
A llvm/test/Transforms/LoopVectorize/early_exit_with_stores.ll
Log Message:
-----------
[LV] Transform tests for early-exit with stores (#183288)
Precommit of transform tests for #178454
Commit: 5cf09a68a63dde0158973682717b1a5f2c0d552c
https://github.com/llvm/llvm-project/commit/5cf09a68a63dde0158973682717b1a5f2c0d552c
Author: Matthew Devereau <matthew.devereau at arm.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/clmul-fixed.ll
M llvm/test/CodeGen/AArch64/clmul.ll
Log Message:
-----------
[AArch64][ISel] Use vector register for scalar CLMUL (#183282)
Even though there are only v8i8 and v1i64 variants for pmul/pmull, Using
them is faster than the current implementation for scalar CLMUL.
Commit: 0af2d43e06415ce1e8a5d49e864c3881048dd08b
https://github.com/llvm/llvm-project/commit/0af2d43e06415ce1e8a5d49e864c3881048dd08b
Author: Tomohiro Kashiwada <kikairoya at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaDeclAttr.cpp
A clang/test/SemaCXX/attr-exclude_from_explicit_instantiation.ignore-dllattr.cpp
Log Message:
-----------
[Clang] Warn if both of `dllexport`/`dllimport` and `exclude_from_explicit_instantiation` are specified (#183515)
The attributes `exclude_from_explicit_instantiation` and
`dllexport`/`dllimport` serve opposite purposes.
Therefore, if an entity has both attributes, drop one with a warning,
depending on the context of the declaration.
In a template context, the `exclude_from_explicit_instantiation`
attribute takes precedence over the `dllexport` or `dllimport`
attribute. Conversely, the `dllexport` and `dllimport` attributes are
prioritized, in a non-template context.
Commit: 05fdd5383967042c7cb00871de2397d3d5e87b92
https://github.com/llvm/llvm-project/commit/05fdd5383967042c7cb00871de2397d3d5e87b92
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/lib/Sema/SemaConcept.cpp
M clang/test/SemaTemplate/concepts.cpp
Log Message:
-----------
[Clang] Fix the lambda context for constraint evaluation (#184319)
Constraint lambdas in the requires body need complete template arguments
before they can be evaluated. That was connected by
ImplicitConceptSpecializationDecl which is no longer created naturally
after the normalization patch.
This patch fixes the bug by creating a temporary decl for that purpose.
Though the temporary object should go away once we have the evaluation
context track template arguments.
No release note for being a regression fix.
Fixes #184047
Commit: 1b3545117df0dfcea164d33a2432c66aa3b7f559
https://github.com/llvm/llvm-project/commit/1b3545117df0dfcea164d33a2432c66aa3b7f559
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M mlir/lib/Dialect/IRDL/IR/IRDL.cpp
M mlir/test/Dialect/IRDL/invalid_names.irdl.mlir
Log Message:
-----------
[mlir][irdl] Fix crash in TypeOp/AttributeOp verify on empty sym_name (#184598)
TypeOp::verify() and AttributeOp::verify() called StringRef::front() to
check for leading '\!' or '#' sigils before passing the name to
isValidName(). When sym_name is empty, front() triggers an assertion
failure:
Assertion `\!empty()' failed.
Fix: guard the front() calls with an emptiness check. An empty sym_name
then falls through to isValidName(), which already emits a proper
diagnostic:
error: name of type is empty
Fixes #159949
Commit: 47766d7f8c397da857d9f78db36c71e8a2ca1fbf
https://github.com/llvm/llvm-project/commit/47766d7f8c397da857d9f78db36c71e8a2ca1fbf
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.td
M clang/include/clang/Basic/BuiltinsAMDGPUDocs.td
Log Message:
-----------
[AMDGPU][Clang][Doc] Add documentation for WMMA builtins (#183939)
Commit: c2e22e3b797da806e8d67eb5dafd31b425d0c1af
https://github.com/llvm/llvm-project/commit/c2e22e3b797da806e8d67eb5dafd31b425d0c1af
Author: Ken Matsui <26405363+ken-matsui at users.noreply.github.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/utils/hmaptool/CMakeLists.txt
Log Message:
-----------
[clang][cmake] Add option to control hmaptool installation (#172725)
Commit: 21c1ba16edc01cc14d8d0f6893beebad5afc3619
https://github.com/llvm/llvm-project/commit/21c1ba16edc01cc14d8d0f6893beebad5afc3619
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir
M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
M llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
M llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
M llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
M llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
M llvm/test/CodeGen/AMDGPU/mai-hazards.mir
M llvm/test/CodeGen/AMDGPU/no-limit-coalesce.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-no-fold-exec-copy.mir
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
A llvm/test/TableGen/ArtificialRegs.td
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.h
Log Message:
-----------
[TableGen] Complete the support for artificial registers (#183371)
Artificial registers were added in
eb0c510ecde667cd911682cc1e855f73f341d134
as a means of giving super-registers heavier weights than that
of their subregisters, even when they only contain a single
physical subregister.
Artifical registers thus do exist in code and participate in
register unit weight calculations, but are not supposed to be
available for register allocation.
This patch completes the support for artificial registers to:
- Ignore artificial registers when joining register unit uber
sets. Artificial registers may be members of classes that
together include registers and their sub-registers, making it
impossible to compute normalised weights for uber sets they
belong to.
We have a use case downstream relying on this being supported,
which allows to avoid introducing a large number of additional
register classes.
- Not generate purely artificial register class intersections.
It is critical not to have such classes, as the common LLVM
codegen infrastructure will try to use them to constrain
classes of virtual registers instead of producing COPYs
whenever both the source and target register classes contain
the same artificial registers.
- Not generate sub-classes where classes with the same
non-artificial members already exist. This is mostly for
convenience. For example, the HI16-capable subset of AMDGPU's
AV_32 is VGPR_32, except VGPR_32 also contains the artificial
staging registers. If the staging registers are not ignored,
we'll end up having an additional generated register class,
AV_32_with_hi16_in_VGPR_16, -- harmless, but also useless.
Eliminates a few inferred AMDGPU register classes:
- VS_32_with_hi16
- VS_32_Lo256_with_hi16
- VS_32_Lo128_with_hi16
- VRegOrLds_32_and_VS_32_Lo256
- VRegOrLds_32_and_VS_32_Lo128
- SRegOrLds_32_and_VRegOrLds_32
Causes no register class changes for other targets.
Commit: 71de1e47c012aa4621068634fa955052aa7f56a7
https://github.com/llvm/llvm-project/commit/71de1e47c012aa4621068634fa955052aa7f56a7
Author: Lukacma <Marian.Lukac at arm.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64InstrAtomics.td
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/test/CodeGen/AArch64/aarch64-addv.ll
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/aarch64-pmull2.ll
M llvm/test/CodeGen/AArch64/aarch64-scal-to-vec-bitcast-insert.ll
M llvm/test/CodeGen/AArch64/arm64-cvt-simd-intrinsics.ll
M llvm/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll
M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
M llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
M llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
M llvm/test/CodeGen/AArch64/arm64-vcvt.ll
M llvm/test/CodeGen/AArch64/arm64-vshift.ll
M llvm/test/CodeGen/AArch64/avoid-pre-trunc.ll
M llvm/test/CodeGen/AArch64/bitcast-extend.ll
M llvm/test/CodeGen/AArch64/bitcnt-i256.ll
M llvm/test/CodeGen/AArch64/concat-vector-add-combine.ll
M llvm/test/CodeGen/AArch64/ctpop.ll
M llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
M llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
M llvm/test/CodeGen/AArch64/fsh.ll
M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
M llvm/test/CodeGen/AArch64/select-bitcast.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
M llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
M llvm/test/CodeGen/AArch64/vector-llrint.ll
M llvm/test/CodeGen/AArch64/vector-lrint.ll
M llvm/test/CodeGen/AArch64/zext.ll
Log Message:
-----------
Reapply "[AArch64] Wrap integer SCALAR_TO_VECTOR nodes in bitcasts (#172837)" (#183380) (#184403)
This reverts commit b7ce37c6703f2d82376f50f82a05b807a0ad90ad.
The
[issue](https://github.com/llvm/llvm-project/pull/172837#issuecomment-3961532435)
this patch revealed was fixed by [this
patch](https://github.com/llvm/llvm-project/pull/183549).
Commit: c6bb6a7e425472d670da80036f39645580668282
https://github.com/llvm/llvm-project/commit/c6bb6a7e425472d670da80036f39645580668282
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/VPlan/conditional-scalar-assignment-vplan.ll
A llvm/test/Transforms/LoopVectorize/tail-folding-masked-mem-opts.ll
Log Message:
-----------
[LV] Add `-force-target-supports-masked-memory-ops` option (#184325)
This can be used to make target agnostic tail-folding tests much less
verbose, as masked loads/stores can be used rather than scalar
predication.
Commit: 0cbba3ed5f12476140ec1b47b777c743e705bf26
https://github.com/llvm/llvm-project/commit/0cbba3ed5f12476140ec1b47b777c743e705bf26
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M flang-rt/CMakeLists.txt
Log Message:
-----------
[flang-rt] Fix incorrect condition for removing backtrace (#184610)
Commit: 073de3b80375bc510863f4cdeb0b2757676111bb
https://github.com/llvm/llvm-project/commit/073de3b80375bc510863f4cdeb0b2757676111bb
Author: Juan Manuel Martinez Caamaño <jmartinezcaamao at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
Log Message:
-----------
[SPIRV] Rename `selectSelectDefaultArgs` to `selectBoolToInt` (#184120)
The function is used to extend a `bool` (vector or scalar) into `1/-1`
for `true` and `0` for `false` (vector or scalar).
There is no obvious "default" argument for a select operation, so the
original name is confusing.
This patch:
* Renames this function to better signal its intention,
* makes the boolean argument explicit in the function (instead of
implicit through the first register operand of the instruction),
* rename `I` to `InsertAt`.
Commit: 5c274078422435b1c666d99375e958d30c4b77a6
https://github.com/llvm/llvm-project/commit/5c274078422435b1c666d99375e958d30c4b77a6
Author: Tarun Thammisetty <thammisettytarun at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/VirtualCallChecker.cpp
A clang/test/Analysis/Inputs/virtualcall-system-header.h
M clang/test/Analysis/virtualcall.cpp
Log Message:
-----------
[analyzer] Suppress optin.cplusplus.VirtualCall warnings in system headers (#184183)
Fixes #184178
The optin.cplusplus.VirtualCall checker reports warnings for virtual
method calls during construction/destruction even when the call site is
in a system header (included via -isystem). Users cannot fix such code
and must resort to NOLINT suppressions.
Add a system header check in checkPreCall before emitting the report,
consistent with how other checkers (e.g. MallocChecker) handle this.
Commit: 11c11ec2e9fd825f625fd7fcb8318e72fe1b9e4a
https://github.com/llvm/llvm-project/commit/11c11ec2e9fd825f625fd7fcb8318e72fe1b9e4a
Author: Benjamin Luke <benjamin.luke at sony.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Lex/Lexer.cpp
A clang/test/Preprocessor/miopt-peek-restore-header-guard.cpp
M clang/unittests/Lex/LexerTest.cpp
Log Message:
-----------
[clang][Lex] Preserve MultipleIncludeOpt state in Lexer::peekNextPPToken (#183425)
Fixes https://github.com/llvm/llvm-project/issues/180155.
This is a duplicate of https://github.com/llvm/llvm-project/pull/180700
except that I also added some tests, fine to go with either PR, but we
should add the tests.
peekNextPPToken lexed a token and mutated MIOpt, which could clear the
controlling-macro state for main files in C++20 modules mode.
Save/restore MIOpt in Lexer::peekNextPPToken.
Add regression coverage in
LexerTest.MainFileHeaderGuardedWithCPlusPlusModules that checks to make
sure the controlling macro is properly set in C++20 mode.
Add source level lit test in miopt-peek-restore-header-guard.cpp that
checks to make sure that the warnings that depend on the MIOpt state
machine are emitted in C++20 mode.
Commit: 50653e5a0d1db1b7a9451cb98fb1b56224449d72
https://github.com/llvm/llvm-project/commit/50653e5a0d1db1b7a9451cb98fb1b56224449d72
Author: Sayan Saha <sayans at mathworks.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/test/Dialect/Tosa/canonicalize.mlir
Log Message:
-----------
[tosa] : Enhance tosa.slice folding for dynamic dims. (#184615)
Source IR:
```
func.func @main(%arg0: tensor<?x112x64x112xf32>) -> tensor<?x113x65x112xf32> {
%0 = tosa.const_shape {values = dense<[0, 0, 1, 1, 1, 1, 0, 0]> : tensor<8xindex>} : () -> !tosa.shape<8>
%1 = "tosa.const"() <{values = dense<0.000000e+00> : tensor<1xf32>}> : () -> tensor<1xf32>
%2 = tosa.pad %arg0, %0, %1 : (tensor<?x112x64x112xf32>, !tosa.shape<8>, tensor<1xf32>) -> tensor<?x114x66x112xf32>
%3 = tosa.const_shape {values = dense<0> : tensor<4xindex>} : () -> !tosa.shape<4>
%4 = tosa.const_shape {values = dense<[-1, 113, 65, 112]> : tensor<4xindex>} : () -> !tosa.shape<4>
%5 = tosa.slice %2, %3, %4 : (tensor<?x114x66x112xf32>, !tosa.shape<4>, !tosa.shape<4>) -> tensor<?x113x65x112xf32>
return %5 : tensor<?x113x65x112xf32>
}
```
when canonicalized produces
```
$> mlir-opt --canonicalize
func.func @main(%arg0: tensor<?x112x64x112xf32>) -> tensor<?x113x65x112xf32> {
%0 = tosa.const_shape {values = dense<0> : tensor<4xindex>} : () -> !tosa.shape<4>
%1 = tosa.const_shape {values = dense<[-1, 113, 65, 112]> : tensor<4xindex>} : () -> !tosa.shape<4>
%2 = "tosa.const"() <{values = dense<0.000000e+00> : tensor<1xf32>}> : () -> tensor<1xf32>
%3 = tosa.const_shape {values = dense<[0, 0, 1, 0, 1, 0, 0, 0]> : tensor<8xindex>} : () -> !tosa.shape<8>
%4 = tosa.pad %arg0, %3, %2 : (tensor<?x112x64x112xf32>, !tosa.shape<8>, tensor<1xf32>) -> tensor<?x113x65x112xf32>
%5 = tosa.slice %4, %0, %1 : (tensor<?x113x65x112xf32>, !tosa.shape<4>, !tosa.shape<4>) -> tensor<?x113x65x112xf32>
return %5 : tensor<?x113x65x112xf32>
}
```
because of the `PadSliceOptimization`. Note that the `tosa.slice` op
after the optimization is essentially a no-op. This change, enhances the
folder to fold such `tosa.slice` ops. After this change canonicalization
produces
```
func.func @main(%arg0: tensor<?x112x64x112xf32>) -> tensor<?x113x65x112xf32> {
%0 = "tosa.const"() <{values = dense<0.000000e+00> : tensor<1xf32>}> : () -> tensor<1xf32>
%1 = tosa.const_shape {values = dense<[0, 0, 1, 0, 1, 0, 0, 0]> : tensor<8xindex>} : () -> !tosa.shape<8>
%2 = tosa.pad %arg0, %1, %0 : (tensor<?x112x64x112xf32>, !tosa.shape<8>, tensor<1xf32>) -> tensor<?x113x65x112xf32>
return %2 : tensor<?x113x65x112xf32>
}
```
Commit: c370f5af6c8d337216b1f86589ab3e48d1c5a598
https://github.com/llvm/llvm-project/commit/c370f5af6c8d337216b1f86589ab3e48d1c5a598
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
Log Message:
-----------
[VPlan] Preserve IsSingleScalar for hoisted predicated load. (#184453)
The predicated loads may be single scalar (e.g. for VF = 1). We should
preserve IsSingleScalar when hoisting them. As all loops access the same
address, IsSingleScalar must match across all loads in the group.
This fixes an assertion when interleaving-only with hoisted loads.
Fixes https://github.com/llvm/llvm-project/issues/184372
PR: https://github.com/llvm/llvm-project/pull/184453
Commit: 56e0b6af1d3948fa2ed56149a02707adaa7a4074
https://github.com/llvm/llvm-project/commit/56e0b6af1d3948fa2ed56149a02707adaa7a4074
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M mlir/test/Dialect/Affine/SuperVectorize/vectorize_unsupported.mlir
M mlir/test/lib/Dialect/Affine/TestVectorizationUtils.cpp
Log Message:
-----------
[mlir][affine] Fix crash in vectorizeAffineLoopNest test utility for reduction loops (#184617)
The test utility function `testVecAffineLoopNest` called
`isLoopParallel` with a `reductions` output parameter, which populates
reduction descriptors when the loop performs a reduction. However, these
descriptors were never added to `strategy.reductionLoops` before calling
`vectorizeAffineLoopNest`. When the vectorizer then processed a loop
with `iter_args`, it found no reduction descriptors in the strategy and
hit an assertion failure.
Fix by registering the reduction loop descriptors in the strategy before
vectorization, matching what the production vectorizer code already does
correctly.
Fixes #128334
Commit: c9ca768c88cc2bec4240b8710e6d173e7be278e4
https://github.com/llvm/llvm-project/commit/c9ca768c88cc2bec4240b8710e6d173e7be278e4
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M mlir/lib/Dialect/Shape/IR/Shape.cpp
M mlir/test/Dialect/Shape/invalid.mlir
Log Message:
-----------
[mlir][shape] Fix crash when shape.lib array references undefined symbol (#184613)
In verifyOperationAttribute(), the single-symbol path for shape.lib used
SymbolTable::lookupSymbolIn() followed by an explicit null check. The
array path at line 196-197 used dyn_cast<FunctionLibraryOp>() directly
on the lookup result, which asserts when the symbol is not found (null
pointer).
Fix: use dyn_cast_or_null<> instead of dyn_cast<> so that a missing
symbol falls through to the existing "does not refer to
FunctionLibraryOp" error diagnostic instead of asserting.
Fixes #159653
Commit: 33be2d0e7ab2c8874f53df8cbbda07381020b1c4
https://github.com/llvm/llvm-project/commit/33be2d0e7ab2c8874f53df8cbbda07381020b1c4
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/clmul-fixed.ll
M llvm/test/CodeGen/AArch64/clmul.ll
Log Message:
-----------
[AArch64] Update clmul tests after #184403 (#184611)
This was likely a mid-air collision with #183282. Update the tests to
match the current state of HEAD.
Commit: c123642824fdc9e1f2b6fda849b5cde113372229
https://github.com/llvm/llvm-project/commit/c123642824fdc9e1f2b6fda849b5cde113372229
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M .github/workflows/containers/github-action-ci/Dockerfile
Log Message:
-----------
[CI] Install binutils-dev in pre-merge container (#184608)
This is to get the plugin-api.h file, to allow running tests for the
gold plugin.
Commit: e5a6a0f10856b14ea0956b40305632fbbfea6f16
https://github.com/llvm/llvm-project/commit/e5a6a0f10856b14ea0956b40305632fbbfea6f16
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
A llvm/test/CodeGen/SPIRV/global-var-no-functions.ll
M llvm/test/CodeGen/SPIRV/legalize-zero-size-arrays-global.ll
M llvm/test/CodeGen/SPIRV/legalize-zero-size-arrays-nested.ll
M llvm/test/CodeGen/SPIRV/legalize-zero-size-arrays-struct.ll
M llvm/test/CodeGen/SPIRV/legalize-zero-size-arrays-undef.ll
Log Message:
-----------
[SPIRV] Fix global emission for modules with no functions (#183833)
Right now we have a problem where if you have a LLVM module with globals
but no functions, a completely empty SPIR-V module is emitted.
This is because global emission is dependent on tracking intrinsic
functions being emitted in functions.
As a simple fix, just insert a service function, which the backend is
already set up to not actually emit, if there are no real functions.
The current use case of the service function is for function pointers. I
don't think it's possible that we need to both generate a service
function for function pointers and for globals with no functions, so I
just added an error (not an assert) just in case if we do need it for
both cases.
Probably we should rework global handling in the future to work without
these workarounds, but this is a pretty fundamental issue so let's work
around it with this simple change for now.
This change exposed an existing bug:
We consider basic blocks with no successors as fall-through
Also, fix some existing tests. The symptom was:
We previously emitted an empty module, but not that we don't, we hit a
`spirv-val` error about invalid Function StorageClass for globals
because no `addrspace` was specified. Set the `addrspace` to `1`
(`CrossWorkgroup`) in those tests.
Closes: https://github.com/llvm/llvm-project/issues/182899
---------
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: b28ec5ad18080d40f62de0eb5a07c9ebb7649451
https://github.com/llvm/llvm-project/commit/b28ec5ad18080d40f62de0eb5a07c9ebb7649451
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/Func/IR/FuncOps.td
M mlir/lib/Dialect/Func/IR/FuncOps.cpp
M mlir/test/Dialect/Func/invalid.mlir
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestOps.td
Log Message:
-----------
[mlir][Func] Fix FuncOp verifier ordering via hasRegionVerifier (#184612)
FuncOp::verify() iterated over all blocks and called
getMutableSuccessorOperands() on any RegionBranchTerminatorOpInterface
terminator to check return types. This ran during the entrance phase of
verification — before child ops had been verified — so a malformed
terminator whose getMutableSuccessorOperands() assumed invariants
established by its own verify() could crash instead of emitting a clean
diagnostic.
Fix by switching to hasRegionVerifier=1: rename verify() →
verifyRegions() so the return-type checks run in the exit phase, after
all nested ops have already been verified.
To demonstrate the bug and guard against regression, add
TestCrashingReturnOp to the test dialect. The op implements
RegionBranchTerminatorOpInterface and report_fatal_errors in
getMutableSuccessorOperands() when its 'valid' unit-attr is absent,
reproducing the class of crash described above. The accompanying lit
test confirms a clean diagnostic is emitted rather than a crash.
Commit: ded64d2417d4394ae47d69653a5798a3a36dd9c7
https://github.com/llvm/llvm-project/commit/ded64d2417d4394ae47d69653a5798a3a36dd9c7
Author: Mircea Trofin <mtrofin at google.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/include/llvm/Support/GenericDomTreeConstruction.h
M llvm/unittests/Analysis/DomTreeUpdaterTest.cpp
Log Message:
-----------
[DTU] fix dominator tree update eliding reachable nodes (#177683)
The initial CFG looks like this:
After inlining, it looks like this:
It should be sufficient to add and remove the edges shown in the test, i.e.:
- add: `bb3->bb1.i` and `bb3->bb2.i`
- remove: `bb3->bb4`, `bb3->bb5` and `bb5->bb8`
New nodes, like `bb5.body`, get discovered when adding bb3->bb2.i. See the "StepByStep" variant of the test). Without the fix in this patch, however, `bb5.body` gets elided when the deleted edges get taken into account, and `DT` is left invalid.
Commit: a3eb13b5bfd1f216afcc128f9452bbb72daba0d6
https://github.com/llvm/llvm-project/commit/a3eb13b5bfd1f216afcc128f9452bbb72daba0d6
Author: Takashi Idobe <idobetakashi at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
A llvm/test/CodeGen/X86/mulx64-no-implicit-copy.ll
Log Message:
-----------
[X86] remove unnecessary movs when %rdx is an input to mulx (#184462)
Closes: https://github.com/llvm/llvm-project/issues/174912
When generating a `mulx` instruction for a widening multiplication, even
if one input is placed in %rdx, LLVM won't place it in the implicit
first slot, instead it'll generate two movs before calling mulx to swap
the registers, which are unnecessary. GCC already has this optimization
(as shown in the issue) so this puts the two compilers closer to each
other on that front.
Co-authored-by: Aiden Grossman <aidengrossman at google.com>
Commit: 247a9bfc26ad1f062c52f7b4625ec0e0710a6424
https://github.com/llvm/llvm-project/commit/247a9bfc26ad1f062c52f7b4625ec0e0710a6424
Author: Krzysztof Drewniak <krzysdrewniak at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M mlir/lib/Dialect/AMDGPU/Transforms/FoldMemRefsOps.cpp
M mlir/test/Dialect/AMDGPU/amdgpu-fold-memrefs.mlir
Log Message:
-----------
[mlir][AMDGPU] Add folders for memref aliases to TDM base creation (#184567)
The TDM base creation (amdgpu.make_tdm_base and
amdgpu.make_gather_tdm_base) take references to a
`%memref[%i0, %i1,, ...]` for the starting point of the tiles in
global/shared memory that the TDM descriptor refers to. Memory alias ops
can be safely folded into these operations, since these two memref
operands are just pointers to a scalar starting pint and don't have
semantics that depend on the memref layout (except to the extent that it
defines a location in memory).
While I'm here, I've cleaned up a few things, like the incorrect file
header and fixed the tests to not use integer address spaces.
Co-authored-by: Claude Opus 4.6 <noreply at anthropic.com>
Commit: f55080da988a68da6736407b34eafd00817b7143
https://github.com/llvm/llvm-project/commit/f55080da988a68da6736407b34eafd00817b7143
Author: Akash Banerjee <akash.banerjee at amd.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
A flang/test/Lower/OpenMP/implicit-map-pointer-no-default-mapper.f90
M flang/test/Lower/OpenMP/target-data-skip-mapper-calls.f90
Log Message:
-----------
[flang][OpenMP] Avoid implicit default mapper on pointer captures (#184382)
This change fixes incorrect implicit declare mapper behavior in Flang
OpenMP lowering.
Issue:
Implicit default mappers were being attached/generated for pointer-based
implicit captures, and also on data-motion directives. That could
trigger recursive component mapping that overlaps/conflicts with
explicit user mappings, causing runtime mapping failures.
Fix:
- Skip implicit default mapper generation for implicit pointer captures
(keep support for allocatables).
- Do not auto-attach implicit mappers on target enter data, target exit
data, or target update.
- Apply the same pointer guard in the implicit target-capture lowering
path.
Commit: e8e8d30b229a77d86e97c49a0680ddb7fdf77a14
https://github.com/llvm/llvm-project/commit/e8e8d30b229a77d86e97c49a0680ddb7fdf77a14
Author: Alexey Karyakin <akaryaki at qti.qualcomm.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/lib/Headers/hvx_hexagon_protos.h
A clang/test/Headers/hexagon-hvx-ieee-headers.c
Log Message:
-----------
[Hexagon] Use __HVX_IEEE_FP__ to guard protos that need -mhvx-ieee-fp (#184422)
Hexagon clang recently started to define __HVX_IEEE_FP__ when the
-mhvx-ieee-fp option is specified. Guard the intrinsic macros for
instructions that should only be available with -mhvx-ieee-fp with
__HVX_IEEE_FP__.
Additionally, the following NFC changes are included:
- NFC: Remove guards around HVX v60 intrinsic macros
Hexagon v60 is the oldest Hexagon version that supports HVX so these
guards were redundant. Presence of HVX is guarded separately, once
per the whole file.
- Remove comments from closing guards (HVX protos)
These comments served very limited function as they only guard
one macro. Also, they were incorrect. Instead of fixing remove them.
This will also reduce by the factor of two the amount of changes
when guarding conditions change.
Commit: 53aa77092ea72b85bec0c8bb1ba11ed1f2f2eefe
https://github.com/llvm/llvm-project/commit/53aa77092ea72b85bec0c8bb1ba11ed1f2f2eefe
Author: Daniel Chen <cdchen at ca.ibm.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M flang/tools/f18/CMakeLists.txt
Log Message:
-----------
[flang] Fix distribution build of Fortran builtin/intrinsic modules. (#184204)
Currently, `-DLLVM_DISTRIBUTION_COMPONENTS="flang-module-interfaces"`
doesn't work. It failed to build the Fortran builtin/intrinsic modules
as distribution build, `install-distribution`.
This PR is to fix that.
Commit: a40e83b29ce9b1642b0633c726032f1481d83bed
https://github.com/llvm/llvm-project/commit/a40e83b29ce9b1642b0633c726032f1481d83bed
Author: Kseniya Tikhomirova <kseniya.tikhomirova at intel.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M libsycl/docs/index.rst
A libsycl/include/sycl/__impl/async_handler.hpp
A libsycl/include/sycl/__impl/detail/default_async_handler.hpp
A libsycl/include/sycl/__impl/property_list.hpp
A libsycl/include/sycl/__impl/queue.hpp
M libsycl/include/sycl/sycl.hpp
M libsycl/src/CMakeLists.txt
A libsycl/src/detail/queue_impl.cpp
A libsycl/src/detail/queue_impl.hpp
A libsycl/src/queue.cpp
Log Message:
-----------
[libsycl] Add sycl::queue stub (#184110)
Part 2 of changes needed for USM alloc/dealloc impl.
This is part of the SYCL support upstreaming effort. The relevant RFCs
can be found here:
https://discourse.llvm.org/t/rfc-add-full-support-for-the-sycl-programming-model/74080
https://discourse.llvm.org/t/rfc-sycl-runtime-upstreaming/74479
---------
Signed-off-by: Tikhomirova, Kseniya <kseniya.tikhomirova at intel.com>
Commit: 8486d893bd7960ed6f0be8d2fa18cd96fb329a09
https://github.com/llvm/llvm-project/commit/8486d893bd7960ed6f0be8d2fa18cd96fb329a09
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Log Message:
-----------
[SelectionDAG] Fix -Wunused-variable after #179318 (#184623)
```
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:3572:26: error: unused variable 'NanEnc' [-Werror,-Wunused-variable]
3572 | const fltNanEncoding NanEnc = SrcSem.nanEncoding;
| ^~~~~~
```
Simply inline the definition of the variable given it is not used
anywhere else and the assignment is a simple copy.
Commit: 7b72b5fde414fd7d41653a07ddb87f80038009aa
https://github.com/llvm/llvm-project/commit/7b72b5fde414fd7d41653a07ddb87f80038009aa
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
Log Message:
-----------
[bazel] Fix building lldb without libedit (#184535)
We were always trying to compile the libedit file even if it wasn't used
because we were missing this conditional from cmake:
https://github.com/llvm/llvm-project/blob/630b9570d199dca19dc85834f583bc8590a21876/lldb/source/Host/CMakeLists.txt#L57-L61
Commit: 613a5c555ebffd7f32ad48de7253e8c25fe627a4
https://github.com/llvm/llvm-project/commit/613a5c555ebffd7f32ad48de7253e8c25fe627a4
Author: Erick Ochoa Lopez <erick.ochoalopez at amd.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/Vector/TransformOps/VectorTransformOps.td
M mlir/include/mlir/Dialect/Vector/Transforms/LoweringPatterns.h
M mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp
M mlir/lib/Dialect/Vector/Transforms/LowerVectorMultiReduction.cpp
M mlir/test/Dialect/LLVM/transform-e2e.mlir
M mlir/test/Dialect/Vector/transform-vector.mlir
R mlir/test/Dialect/Vector/vector-multi-reduction-reorder-and-expand.mlir
A mlir/test/Dialect/Vector/vector-multi-reduction-reorder.mlir
M mlir/test/Dialect/Vector/vector-multi-reduction-unrolling.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/reduce_1d.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/reduce_2d.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/test-matmul-masked-vec.mlir
M mlir/test/python/dialects/transform_vector_ext.py
Log Message:
-----------
[mlir][vector] Replace OneDimMultiReductionToTwoDim with OneDimMultiReductionToReduction (#184241)
The `OneDimMultiReductionToTwoDim` pattern had some issues. For the
input program:
```mlir
func.func @rank1_multi_reduction(%arg0: vector<8xf32>, %acc: f32) -> f32 {
%0 = vector.multi_reduction <add>, %arg0, %acc [0] : vector<8xf32> to f32
return %0 : f32
}
```
* when lowering using the inner-parallel strategy, the compiler would
essentially produce scalar code:
```mlir
func.func @rank1_multi_reduction(%arg0: vector<8xf32>, %arg1: f32) -> f32 {
%0 = vector.shape_cast %arg0 : vector<8xf32> to vector<1x8xf32>
%1 = vector.broadcast %arg1 : f32 to vector<1xf32>
%2 = vector.transpose %0, [1, 0] : vector<1x8xf32> to vector<8x1xf32>
%3 = vector.extract %2[0] : vector<1xf32> from vector<8x1xf32>
%4 = arith.addf %3, %1 : vector<1xf32>
%5 = vector.extract %2[1] : vector<1xf32> from vector<8x1xf32>
%6 = arith.addf %5, %4 : vector<1xf32>
... (repeats for all 8 elements) ...
%17 = vector.extract %2[7] : vector<1xf32> from vector<8x1xf32>
%18 = arith.addf %17, %16 : vector<1xf32>
%19 = vector.extract %18[0] : f32 from vector<1xf32>
return %19 : f32
}
```
* when lowering using the inner-reduction strategy, the compiler would
first unnecessarily transform it into a 2-D multi_reduction operation
<1x8xf32> and then extract an <8xf32> vector and apply reduction. The
canonicalization and folding would lead to the following final result:
```mlir
func.func @rank1_multi_reduction(%arg0: vector<8xf32>, %arg1: f32) -> f32 {
%0 = vector.reduction <add>, %arg0, %arg1 : vector<8xf32> into f32
return %0 : f32
}
```
Now, after this change:
* when lowering the compiler now produces for both strategies in one
step.
```
func.func @rank1_multi_reduction(%arg0: vector<8xf32>, %arg1: f32) -> f32 {
%0 = vector.reduction <add>, %arg0, %arg1 : vector<8xf32> into f32
return %0 : f32
}
```
This pattern is also useful for an ongoing refactoring that is happening
in the multi_reduction patterns. It is the only pattern that increases
multi_reduction in rank and would lead to an infinite loop when
attempting to reach a fixed point once we generalize other unrolling
patterns.
Assisted-by: Claude
Commit: 39d5aea6df9094c560a98f88231d258885285a6c
https://github.com/llvm/llvm-project/commit/39d5aea6df9094c560a98f88231d258885285a6c
Author: Delaram Talaashrafi <dtalaashrafi at nvidia.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsLoop.h
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsLoop.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsLoopTest.cpp
Log Message:
-----------
[OpenACC] Replace terminators with scf.yield in wrapMultiBlockRegionWithSCFExecuteRegion (#184458)
When wrapping a multi-block region in `scf.execute_region`, replace
`func::ReturnOp` (if flag `convertFuncReturn` is set) and `acc::YieldOp`
in all the blocks with `scf.yield` so the region has a valid SCF
terminator.
Commit: 8f8590e691fe772b321004118ae92f5230c8a94d
https://github.com/llvm/llvm-project/commit/8f8590e691fe772b321004118ae92f5230c8a94d
Author: Xing Xue <xingxue at outlook.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/lib/Driver/ToolChains/AIX.cpp
Log Message:
-----------
[OpenMP][AIX] Add libpthreads for -fopenmp (#184629)
The compiler uses TLS for OpenMP thread‑private data, which results in
references to symbols such as `__tls_get_addr` in `libpthreads`.
Therefore, this PR adds `libpthreads` to the link command when
`-fopenmp` is specified.
Commit: 4b3a9246a0867e45dfd0ab10aeff68e78ebdce8c
https://github.com/llvm/llvm-project/commit/4b3a9246a0867e45dfd0ab10aeff68e78ebdce8c
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
Log Message:
-----------
[bazel] Fix more parse_headers cases in lldb (#184534)
CI doesn't have a toolchain that supports this so we don't validate this
there, but locally this fixes some issues if you're using a toolchain
that does. Mostly since lldb has a bunch of circular deps we just have
to disable it for the header only targets we create to avoid those
circular deps.
Commit: 668d09b2846d9794b35daa2744bf6d4c66c5ec42
https://github.com/llvm/llvm-project/commit/668d09b2846d9794b35daa2744bf6d4c66c5ec42
Author: Qiongsi Wu <qiongsiwu at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/lib/Frontend/CompilerInstance.cpp
A clang/test/Modules/Inputs/pch-config-macros/include/Mod1.h
A clang/test/Modules/Inputs/pch-config-macros/include/module.modulemap
A clang/test/Modules/pch-config-macros.c
Log Message:
-----------
[clang][Modules] Fixing unexpected warnings triggered by a PCH and a module with config macros (#177078)
When a PCH is compiled with macro definitions on the command line, such
as `-DCONFIG1`, an unexpected warning can occur if the macro definitions
happen to belong to an imported module's config macros. The warning may
look like the following:
```
definition of configuration macro 'CONFIG1' has no effect on the import of 'Mod1'; pass '-DCONFIG1=...' on the command line to configure the module
```
while `-DCONFIG1` is clearly on the command line when `clang` compiles
the source that uses the PCH and the module.
The reason this can happen is a combination of two things:
1. The logic that checks for config macros is not aware of any command
line macros passed through the PCH
([here](https://github.com/llvm/llvm-project/blob/7976ac990000a58a7474269a3ca95e16aed8c35b/clang/lib/Frontend/CompilerInstance.cpp#L1562)).
2. `clang` _replaces_ the predefined macros on the command line with the
predefined macros from the PCH, which does not include any builtins
([here](https://github.com/llvm/llvm-project/blob/7976ac990000a58a7474269a3ca95e16aed8c35b/clang/lib/Frontend/CompilerInstance.cpp#L679)).
This PR teaches the preprocessor to recognize the command line macro
definitions passed transitively through the PCH, so that the error check
does not miss these definitions by mistake. The config macro itself
works fine, and it is only the error check that needs fixing.
rdar://95261458
Commit: 77f1480f7ef1af79e3db57be899e73abd1c59a9f
https://github.com/llvm/llvm-project/commit/77f1480f7ef1af79e3db57be899e73abd1c59a9f
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
Log Message:
-----------
[SPIRV] Fix return value of runOnModule for SPIRVPrepareFunctions (#184636)
We need to return `true` if the module is changed by the pass, and we
forgot to do that in this new case.
This fixes a buildbot
[fail](https://lab.llvm.org/buildbot/#/builders/187/builds/17475).
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: 18226e7e2eb8ceeb8a25fb218798f7c9cdbded9d
https://github.com/llvm/llvm-project/commit/18226e7e2eb8ceeb8a25fb218798f7c9cdbded9d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
M llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
Log Message:
-----------
[RISCV] Lower i8/i16/i32 scalable vector ISD::CLMUL/CLMULH with Zvbc32e. (#184465)
Commit: a14f9f822f4813a803eb21797fe90b6367683bcb
https://github.com/llvm/llvm-project/commit/a14f9f822f4813a803eb21797fe90b6367683bcb
Author: Charitha Saumya <136391709+charithaintc at users.noreply.github.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/test/Dialect/XeGPU/subgroup-distribute-unit.mlir
M mlir/test/Dialect/XeGPU/subgroup-distribute.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops-rr.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops.mlir
Log Message:
-----------
[mlir][xegpu] Add support for accessing the default order of a layout. (#184451)
Currently, `getOrder` returns null if the user does not provide an
`order` in xegpu layout. This behavior is undesirable when coupled with
utility functions that work on top of layouts (like `isTransposeOf`).
This PR introduce a `getEffectiveOrder` which always returns the true
order, even if user decides to omit it.
Commit: b0b583475a03bbdb34dff0f3783d7c28713de582
https://github.com/llvm/llvm-project/commit/b0b583475a03bbdb34dff0f3783d7c28713de582
Author: Mir Immad <mirimmad17 at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/X86/known-pow2.ll
Log Message:
-----------
[DAG] Improved handling of ISD::ROTL and ISD::ROTR in isKnownToBeAPowerOfTwo (#182744)
Fixes #181642
Commit: b9f1199581e746152a019a104d22f87ce41f46e1
https://github.com/llvm/llvm-project/commit/b9f1199581e746152a019a104d22f87ce41f46e1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-aggregates.ll
Log Message:
-----------
InstCombine: Support extractvalue in SimplifyDemandedFPClass (#184171)
Previously this only handled extractvalue of frexp.
Commit: 9cd054b0bb3e25ae8eaaa5bdc9d73234cc9b906a
https://github.com/llvm/llvm-project/commit/9cd054b0bb3e25ae8eaaa5bdc9d73234cc9b906a
Author: Lukacma <Marian.Lukac at arm.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/CodeGen/AArch64/arm64-int-neon.ll
M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
M llvm/test/CodeGen/AArch64/arm64-vqadd.ll
Log Message:
-----------
[AArch64] Add lowering for misc NEON intrinsics (#183050)
This patch adds custom lowering for the following NEON intrinsics to
enable better codegen for convert and load/store operations:
- suqadd
- usqadd
- abs
- sqabs
- sqneg
Commit: 9105d9c24949d8cf9b740cb874027351e7230e70
https://github.com/llvm/llvm-project/commit/9105d9c24949d8cf9b740cb874027351e7230e70
Author: Brian Cain <brian.cain at oss.qualcomm.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M lld/ELF/Arch/Hexagon.cpp
A lld/test/ELF/hexagon-duplex-relocs.s
Log Message:
-----------
[lld][Hexagon] Fix findMaskR8 missing duplex support (#183936)
findMaskR8() lacked an isDuplex() check, unlike findMaskR6(),
findMaskR11(), and findMaskR16() which all handle duplex instructions.
When the assembler generates R_HEX_8_X on a duplex SA1_addi instruction
(e.g. `{ r0 = add(r0, ##target); memw(r1+#0) = r2 }`), the wrong mask
0x00001fe0 placed relocation bits at [12:5] instead of [25:20],
corrupting the low sub-instruction (e.g. memw became memb).
Add the isDuplex() check returning 0x03f00000, and add a comprehensive
test covering all duplex instruction x relocation type combinations
across findMaskR6, findMaskR8, findMaskR11, and findMaskR16.
Commit: 3028604556636ad151e0ce57048d19a914179dc8
https://github.com/llvm/llvm-project/commit/3028604556636ad151e0ce57048d19a914179dc8
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
[bazel] Add target for `clang-nvlink-wrapper` (#184644)
Commit: c2db12daa171e8f055ba0fb84cd8fd7b434f75b0
https://github.com/llvm/llvm-project/commit/c2db12daa171e8f055ba0fb84cd8fd7b434f75b0
Author: Sean Fertile <sd.fertile at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/MC/XCOFFObjectWriter.cpp
A llvm/test/CodeGen/PowerPC/aix-reloc-sorting.ll
Log Message:
-----------
[AIX] Sort relocations in XCOFF object writer. (#180807)
Some relocations (like R_REF) are emitted to an offset 0 within the CSECT. If other relocations have already been emitted then the relocations are not in increasing order and the linker will emit an error. Sort the relocations before emitting to fix the problem.
Commit: b80248a0ea35df17ef6f4a2a9df59a0aceb89c79
https://github.com/llvm/llvm-project/commit/b80248a0ea35df17ef6f4a2a9df59a0aceb89c79
Author: Erick Velez <erickvelez7 at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang-tools-extra/clang-doc/CMakeLists.txt
M clang-tools-extra/clang-doc/Generators.cpp
M clang-tools-extra/clang-doc/Generators.h
M clang-tools-extra/clang-doc/JSONGenerator.cpp
A clang-tools-extra/clang-doc/MDMustacheGenerator.cpp
M clang-tools-extra/clang-doc/Representation.cpp
M clang-tools-extra/clang-doc/Representation.h
A clang-tools-extra/clang-doc/assets/md/all-files-template.mustache
A clang-tools-extra/clang-doc/assets/md/class-template.mustache
A clang-tools-extra/clang-doc/assets/md/comments-partial.mustache
A clang-tools-extra/clang-doc/assets/md/index-template.mustache
A clang-tools-extra/clang-doc/assets/md/namespace-template.mustache
M clang-tools-extra/clang-doc/support/Utils.cpp
M clang-tools-extra/clang-doc/support/Utils.h
M clang-tools-extra/clang-doc/tool/CMakeLists.txt
M clang-tools-extra/clang-doc/tool/ClangDocMain.cpp
M clang-tools-extra/test/clang-doc/basic-project.mustache.test
M clang-tools-extra/test/clang-doc/builtin_types.cpp
M clang-tools-extra/test/clang-doc/comments-in-macros.cpp
M clang-tools-extra/test/clang-doc/enum.cpp
M clang-tools-extra/test/clang-doc/index.cpp
M clang-tools-extra/test/clang-doc/json/class.cpp
M clang-tools-extra/test/clang-doc/json/namespace.cpp
M clang-tools-extra/test/clang-doc/namespace.cpp
M clang-tools-extra/test/clang-doc/templates.cpp
M clang-tools-extra/unittests/clang-doc/ClangDocTest.cpp
M clang-tools-extra/unittests/clang-doc/HTMLGeneratorTest.cpp
M clang-tools-extra/unittests/clang-doc/JSONGeneratorTest.cpp
Log Message:
-----------
[clang-doc] Add a Mustache Markdown generator (#177221)
Adds a Markdown generator that uses Mustache templates. This patch adds
the templates themselves and implements changes to the JSONGenerator to
allow for the creation of specific files needed by the MD tests like
`all-files.json`.
This backend should be considered experimental. It satisfies all the
same tests that the current MD backend is tested against, but those
don't seem to provide full coverage for all functionality inside that
backend. It also doesn't output everything provided by JSON. It doesn't
use the MD unittests because the Mustache templates must currently be
written to files.
Commit: 56a53550d317ee2345b48374a9fab239ad75a4df
https://github.com/llvm/llvm-project/commit/56a53550d317ee2345b48374a9fab239ad75a4df
Author: Shivam Kunwar <75530356+phyBrackets at users.noreply.github.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/lib/CodeGen/CGDebugInfo.cpp
A clang/test/DebugInfo/CXX/debug-info-constexpr-array.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
A llvm/test/DebugInfo/X86/debug-info-constexpr-array.ll
Log Message:
-----------
[DebugInfo] Emit DW_AT_const_value for constexpr array static members (#182442)
Clang does not emit a `DW_AT_const_value` in DWARF, while GCC does. This
patch fixes this issue through handling Array `APValues` and respective
handling in the backend through `ConstantDataSequential`
Fixes #165220
Commit: 937bf9cef69fb79038e135d28bf8d8365720cee5
https://github.com/llvm/llvm-project/commit/937bf9cef69fb79038e135d28bf8d8365720cee5
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/bolt/BUILD.bazel
Log Message:
-----------
[bazel] Fix parse_headers in bolt (#184648)
Commit: ff0220d236dedccb8011873e9b92071fbfa74a0e
https://github.com/llvm/llvm-project/commit/ff0220d236dedccb8011873e9b92071fbfa74a0e
Author: khaki3 <47756807+khaki3 at users.noreply.github.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M flang/docs/OpenACC.md
M flang/lib/Semantics/check-acc-structure.cpp
M flang/lib/Semantics/check-acc-structure.h
M flang/test/Semantics/OpenACC/acc-cache-validity.f90
Log Message:
-----------
[flang][acc] Allow orphaned acc cache directive (#184448)
While the spec allows the cache directive at the top of a loop body, the
directive has also been utilized at the top of an acc routine. This PR
removes the semantic check that rejects the cache directive outside of a
loop, allowing orphaned `!$acc cache` similar to CIR.
The OpenACC.md deviation document is updated to note this extension.
Commit: d9d6b16cc622dcbf39e8c2ff549704166040b455
https://github.com/llvm/llvm-project/commit/d9d6b16cc622dcbf39e8c2ff549704166040b455
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/Attributor/nofpclass.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-aggregates.ll
Log Message:
-----------
ValueTracking: Handle ConstantDataSequential in computeKnownFPClass (#184191)
Commit: 2b3e30d4c4705dfb21931188540d0c3aa901a7bb
https://github.com/llvm/llvm-project/commit/2b3e30d4c4705dfb21931188540d0c3aa901a7bb
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/test/CodeGen/AArch64/sme-streaming-checkvl.ll
M llvm/test/CodeGen/AMDGPU/iglp-no-clobber.ll
A llvm/test/CodeGen/AMDGPU/machine-sink-fence.ll
M llvm/test/CodeGen/AMDGPU/misched-remat-revert.ll
M llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
Log Message:
-----------
[CodeGen] Treat hasOrderedMemoryRef as implying arbitrary loads or stores (#182000)
This prevents MachineSink from sinking loads past fences (or any other instruction marked as hasSideEffects).
Fixes: #181708
Commit: 2c95b8d5185b064780515bf3d7c89486ee086056
https://github.com/llvm/llvm-project/commit/2c95b8d5185b064780515bf3d7c89486ee086056
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Log Message:
-----------
AMDGPU: Clean up print handling of AMDGPUTargetID (#184643)
Provide print to raw_ostream method and use it where applicable.
Commit: fbc3a312d69d120d0e594eb8a32bd50222e855cb
https://github.com/llvm/llvm-project/commit/fbc3a312d69d120d0e594eb8a32bd50222e855cb
Author: Charitha Saumya <136391709+charithaintc at users.noreply.github.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
Log Message:
-----------
[mlir][xevm] Remove unnecessary attach target pass. (#184432)
Commit: 0baf5a0496a50ffa9f47b76087cb66980a1f713e
https://github.com/llvm/llvm-project/commit/0baf5a0496a50ffa9f47b76087cb66980a1f713e
Author: Sam Clegg <sbc at chromium.org>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M libunwind/src/Unwind-wasm.c
Log Message:
-----------
Revert "Silence -Wunused-parameter warnings in Unwind-wasm.c" (#175776)
Reverts llvm/llvm-project#125412
See the discussion in #125412 for why this is necessary. The summary is
that:
- Eliding arguments is the C23 extension, but libunwind builds its C
files with `-std=c99`, so this change broke the build.
- `-Wno-unused-parameter` is part of the build for libunwind, so the
codebase does allow them.
Commit: df52bb4c32e2dde40e096813ec83cc0c8a271a10
https://github.com/llvm/llvm-project/commit/df52bb4c32e2dde40e096813ec83cc0c8a271a10
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
Log Message:
-----------
[LoopUnrollPass] Don't use clang specific syntax in optimization remarks (#182430)
Commit: 9dc65372aa6101bd72be80ca0901cb8dd780d01f
https://github.com/llvm/llvm-project/commit/9dc65372aa6101bd72be80ca0901cb8dd780d01f
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang-tools-extra/clang-tidy/misc/ConstCorrectnessCheck.cpp
M clang-tools-extra/docs/clang-tidy/checks/misc/const-correctness.rst
M clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-parameters.cpp
Log Message:
-----------
[clang-tidy] Don't report unnamed params for misc-const-correctness (#184388)
Previously misc-const-correctness warned about non-const unnamed
parameters; but this commit excludes them because these warnings are not
actually useful. An unnamed parameter cannot be referenced at all, so
marking them as 'const' doesn't add additional information.
Also the diagnostic messages look awkward without a name.
Fixes #184330
Commit: 64c0f624cd0717c4fdcc94c5d8557173359935a6
https://github.com/llvm/llvm-project/commit/64c0f624cd0717c4fdcc94c5d8557173359935a6
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M lldb/source/Core/PluginManager.cpp
Log Message:
-----------
[lldb] Make the PluginManager thread safe (#184452)
In #184273, John pointed out that the PluginManager is currently not
thread safe. While we don't currently provide any guarantees, it seems
desirable to be able to interact safely with the PluginManager from
different threads. For example, we allow dynamically loading plugins
from the command interpreter, which in theory could be coming from
different threads.
Commit: a7914aecb2db16274ae07d36ae07178707eac89b
https://github.com/llvm/llvm-project/commit/a7914aecb2db16274ae07d36ae07178707eac89b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/MC/RISCV/rv32p-valid.s
M llvm/test/MC/RISCV/rv64p-valid.s
Log Message:
-----------
[RISCV] Allow unsigned immediates for pli.h, pli.dh, pli.w (#184554)
Allow unsigned immediates that look like like simm10 when only
considering the lower 16 or 32 bits. For pli.dh and pli.dh this
[652024,65535]. For pli.w, this is [4294966784,4294967295].
Since we're only inserting 16 or 32 bits, it makes sense to me that only
those 16 or 32 bits matter. This is similar to how we allow `li a0,
0xffffffff` on RV32.
Commit: 2032960b5de1893ca0027102130188664f94bb02
https://github.com/llvm/llvm-project/commit/2032960b5de1893ca0027102130188664f94bb02
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M flang/test/Lower/Intrinsics/atan2d.f90
M flang/test/Lower/Intrinsics/atan2pi.f90
M flang/test/Lower/Intrinsics/atand.f90
M flang/test/Lower/Intrinsics/atanpi.f90
M flang/test/Lower/Intrinsics/bessel_jn.f90
Log Message:
-----------
[flang][NFC] Converted five tests from old lowering to new lowering (part 24) (#184538)
Tests converted from test/Lower/Intrinsics: atan2d.f90, atan2pi.f90,
atand.f90, atanpi.f90, bessel_jn.f90
Commit: 75b2ea57d5f4a5ae0de1b3ca1ca7eec464811b45
https://github.com/llvm/llvm-project/commit/75b2ea57d5f4a5ae0de1b3ca1ca7eec464811b45
Author: Prajwal P J <prajwaljalwadi at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Analysis/Analyses/UnsafeBufferUsage.h
M clang/include/clang/Analysis/Analyses/UnsafeBufferUsageGadgets.def
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
A clang/test/SemaCXX/warn-unsafe-buffer-usage-string-view.cpp
Log Message:
-----------
[Clang][UnsafeBufferUsage] Warn about two-arg string_view constructors. (#180471)
"This patch extends the unsafe buffer usage warning to cover
std::string_view constructors that take a pointer and size, similar to
the existing check for std::span.
The warning message has been updated to be generic ('container
construction' instead of 'span construction') and existing tests have
been updated to match.
Fixes #166644."
Commit: 34541e5a5400b18d5c75c43f3c0f43cf820117dc
https://github.com/llvm/llvm-project/commit/34541e5a5400b18d5c75c43f3c0f43cf820117dc
Author: Joshua Batista <jbatista at microsoft.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h
M clang/lib/Sema/SemaHLSL.cpp
A clang/test/CodeGenHLSL/builtins/WaveActiveAllEqual.hlsl
A clang/test/SemaHLSL/BuiltIns/WaveActiveAllEqual-errors.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll
A llvm/test/CodeGen/DirectX/WaveActiveAllEqual.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveAllEqual.ll
Log Message:
-----------
[HLSL] Add WaveActiveAllEqual functions (#183634)
This PR adds the WaveActiveAllEqual function to HLSL.
It also adds extra macro logic to CGHLSLBuiltins so that you can specify
a different intrinsic name for the SPIRV intrinsic.
Fixes https://github.com/llvm/llvm-project/issues/99162
Commit: 20902f0b721ba6cf2fb134362d27144bd8584d53
https://github.com/llvm/llvm-project/commit/20902f0b721ba6cf2fb134362d27144bd8584d53
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
A llvm/test/Transforms/Attributor/nofpclass-bitcast.ll
Log Message:
-----------
ValueTracking: Teach computeKnownFPClass to look at bitcast + integer max (#184073)
The returned class will still be one of the bitpatterns.
This pattern is used in rocm device libraries in assorted functions,
e.g.,
https://github.com/ROCm/llvm-project/blob/amd-staging/amd/device-libs/ocml/src/rlen3F.cl#L20
I believe it is blocking the eliminationg of finite checks in some of
the more complex functions.
Commit: a212ebd471b103e26f9746715b1abb47e5ee27b7
https://github.com/llvm/llvm-project/commit/a212ebd471b103e26f9746715b1abb47e5ee27b7
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/include/llvm/Transforms/IPO/Attributor.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/Attributor/nofpclass.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-aggregates.ll
Log Message:
-----------
ValueTracking: Handle constant structs in computeKnownFPClass (#184192)
Also fix attributor not bothering to deal with structs.
Commit: d62fbb6a96645c7c0e450bd8fe198e47c44e2ae3
https://github.com/llvm/llvm-project/commit/d62fbb6a96645c7c0e450bd8fe198e47c44e2ae3
Author: Steven Perron <stevenperron at google.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const.ll
A llvm/test/CodeGen/SPIRV/pointers/fun-ptr-to-itself.ll
Log Message:
-----------
[SPIRV] Update the global registry when expanding function pointer (#183873)
We do not update the global registry when expanding a G_GLOBAL_VALUE for
a function pointer. Then during pointer validation, we can get a
garbage value from the global registry.
Commit: 6e1aee4276bbd6f84b34ce449a3c88d2013ca5e4
https://github.com/llvm/llvm-project/commit/6e1aee4276bbd6f84b34ce449a3c88d2013ca5e4
Author: Vigneshwar Jayakumar <vigneshwar.jayakumar at amd.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
A llvm/test/CodeGen/AMDGPU/bfe-i8-i16.ll
M llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
Log Message:
-----------
[AMDGPU] Select v_bfe_u32 for i8/i16 (and (srl x, c), mask) (#182446)
Combine i8 and i16 (and (srl x, c), mask) instructions to v_bfe_32. This optimization is skipped true_i16 targets.
resolves issue #179494
Commit: 63074da25d16376d4a5b27661d891623bf797fd3
https://github.com/llvm/llvm-project/commit/63074da25d16376d4a5b27661d891623bf797fd3
Author: Vladislav Dzhidzhoev <vdzhidzhoev at accesssoftek.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M lld/test/wasm/debuginfo.test
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
M llvm/test/CodeGen/X86/dbg-distringtype-uint.ll
M llvm/test/DebugInfo/AArch64/DW_AT_APPLE_enum_kind.ll
M llvm/test/DebugInfo/AMDGPU/variable-locations.ll
M llvm/test/DebugInfo/Generic/cross-cu-linkonce-distinct.ll
M llvm/test/DebugInfo/Generic/debug-names-linkage-name.ll
M llvm/test/DebugInfo/Generic/dwarf5-debug-info-static-member.ll
M llvm/test/DebugInfo/Generic/inlined-static-var.ll
M llvm/test/DebugInfo/Generic/namespace.ll
M llvm/test/DebugInfo/MSP430/global-var.ll
M llvm/test/DebugInfo/NVPTX/debug-addr-class.ll
M llvm/test/DebugInfo/PowerPC/strict-dwarf.ll
M llvm/test/DebugInfo/WebAssembly/tls_pic_globals.ll
M llvm/test/DebugInfo/X86/2011-09-26-GlobalVarContext.ll
M llvm/test/DebugInfo/X86/DW_AT_calling-convention.ll
M llvm/test/DebugInfo/X86/align_cpp11.ll
M llvm/test/DebugInfo/X86/align_objc.ll
M llvm/test/DebugInfo/X86/arange-and-stub.ll
M llvm/test/DebugInfo/X86/containing-type-extension-rust.ll
M llvm/test/DebugInfo/X86/debug-info-access.ll
M llvm/test/DebugInfo/X86/debug-info-static-member.ll
M llvm/test/DebugInfo/X86/debug-names-dwarf64.ll
M llvm/test/DebugInfo/X86/dwarf-aranges.ll
M llvm/test/DebugInfo/X86/dwarf-linkage-names.ll
M llvm/test/DebugInfo/X86/dwarfdump-DIImportedEntity_elements.ll
M llvm/test/DebugInfo/X86/generate-odr-hash.ll
M llvm/test/DebugInfo/X86/gnu-public-names.ll
M llvm/test/DebugInfo/X86/linkage-name.ll
M llvm/test/DebugInfo/X86/namelist1.ll
M llvm/test/DebugInfo/X86/prototyped.ll
M llvm/test/DebugInfo/X86/ref_addr_relocation.ll
M llvm/test/DebugInfo/X86/string-offsets-multiple-cus.ll
M llvm/test/DebugInfo/X86/string-offsets-table.ll
M llvm/test/DebugInfo/X86/template.ll
M llvm/test/DebugInfo/X86/tls.ll
M llvm/test/DebugInfo/X86/tu-to-non-tu.ll
M llvm/test/DebugInfo/X86/vla-global.ll
M llvm/test/DebugInfo/attr-btf_tag.ll
M llvm/test/MC/WebAssembly/debug-info.ll
M llvm/test/MC/WebAssembly/debug-info64.ll
M llvm/test/MC/WebAssembly/dwarfdump.ll
M llvm/test/MC/WebAssembly/dwarfdump64.ll
M llvm/test/tools/llvm-debuginfo-analyzer/DWARF/crash-thread-local-storage.test
Log Message:
-----------
[DebugInfo][DwarfDebug] Move emission of globals from beginModule() to endModule() (5/7) (#184219)
RFC
https://discourse.llvm.org/t/rfc-dwarfdebug-fix-and-improve-handling-imported-entities-types-and-static-local-in-subprogram-and-lexical-block-scopes/68544
This patch moves the emission of global variables from
`DwarfDebug::beginModule()` to `DwarfDebug::endModule()`.
It has the following effects:
1. The order of debug entities in the resulting DWARF changes.
2. Currently, if a DISubprogram requires emission of both concrete
out-of-line and inlined subprogram DIEs, and such a subprogram contains
a static local variable, the DIE for the variable is emitted into the
concrete out-of-line subprogram DIE. As a result, the variable is not
available in debugger when breaking at the inlined function instance.
It happens because static locals are emitted in
`DwarfDebug::beginModule()`, but abstract DIEs for functions that are
not completely inlined away are created only later during
`DwarfDebug::endFunctionImpl()` calls.
With this patch, DIEs for static local variables of subprograms that
have both inlined and the concrete out-of-line instances are placed into
abstract subprogram DIEs. They become visible in debugger when breaking
at concrete out-of-line and inlined function instances.
`llvm/test/DebugInfo/Generic/inlined-static-var.ll` illustrates that.
3. It will allow to simplify abstract subprogram DIEs creation by
reverting https://github.com/llvm/llvm-project/pull/159104 later.
This is needed to simplify DWARF emission in a context of proper support
of function-local static variables which comes in the next patch
(https://reviews.llvm.org/D144008), making all function-local entities
handled in `DwarfDebug::endModuleImpl()`.
Authored-by: Kristina Bessonova <kbessonova at accesssoftek.com>
Co-authored-by: David Blaikie <dblaikie at gmail.com>
Co-authored-by: Vladislav Dzhidzhoev <vdzhidzhoev at accesssoftek.com>
Commit: 56ed7485b75e66ee47eae08ecc3b3cb705b2a4e9
https://github.com/llvm/llvm-project/commit/56ed7485b75e66ee47eae08ecc3b3cb705b2a4e9
Author: Amr Hesham <amr96 at programmer.net>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
Log Message:
-----------
[CIR][NFC] Remove unnecessary call to clangCmpToCIRCmp (#184217)
Remove unnecessary call to clangCmpToCIRCmp and use the result from the
previous call L1165
Commit: 149e62c29bf86b045ec8a9941c68ed2f13099b92
https://github.com/llvm/llvm-project/commit/149e62c29bf86b045ec8a9941c68ed2f13099b92
Author: Erick Velez <erickvelez7 at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang-tools-extra/test/clang-doc/namespace.cpp
Log Message:
-----------
[clang-doc] Add DAG directive to MD "All files" test (#184671)
It seems like the order of the all-files.md output might be different on
local machines, so make the check directives `-DAG` for now.
Commit: bb78a0a47083b55147176e878a2363a41c0cd3cc
https://github.com/llvm/llvm-project/commit/bb78a0a47083b55147176e878a2363a41c0cd3cc
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/test/CIR/CodeGen/var-arg-aggregate.c
M clang/test/CIR/CodeGen/var_arg.c
Log Message:
-----------
[CIR] Fix __builtin_va_start handling (#184654)
We were attempting to capture a `count` argument for __builtin_va_start
but the builtin doesn't actually have that as a defined argument. This
change removes the errant handling.
Commit: ade43a54d4419b60eda48cb0ebe84df836893bf6
https://github.com/llvm/llvm-project/commit/ade43a54d4419b60eda48cb0ebe84df836893bf6
Author: Derek Schuff <dschuff at chromium.org>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
M llvm/lib/Target/WebAssembly/WebAssembly.td
M llvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td
M llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
M llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h
M llvm/test/CodeGen/WebAssembly/atomic-fence.mir
A llvm/test/MC/WebAssembly/atomics-orderings-errors.s
A llvm/test/MC/WebAssembly/atomics-orderings.s
Log Message:
-----------
[WebAssembly] MC support for acquire-release atomics (#183656)
Initial support for acquire-release atomics, specified as part of
https://github.com/WebAssembly/shared-everything-threads
This adds an ordering operand to atomic loads, stores, RMWs,
wait/notify,
and fences. It currently defaults to 0 and ISel is not updated yet, so
atomics produced by the compiler will still always be seqcst.
Asm parsing and printing, binary emission and disassembly are all
updated. Binary emission will always use the old encoding because the
encoding is smaller, and to get backwards compatibility for free.
Commit: f986523c5937bd32e1d14a4af6ff5db95c69065c
https://github.com/llvm/llvm-project/commit/f986523c5937bd32e1d14a4af6ff5db95c69065c
Author: Amr Hesham <amr96 at programmer.net>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/test/CIR/CodeGen/complex.cpp
Log Message:
-----------
[CIR] Fix Codegen for Complex & Scalar comparisons (#184006)
Fix Codegen for emitting comparisons between Complex & Scalar
Commit: 28b840815c2285edb232ac0d6ca6f70af987f4c2
https://github.com/llvm/llvm-project/commit/28b840815c2285edb232ac0d6ca6f70af987f4c2
Author: Sarah Spall <sarahspall at microsoft.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/CodeGenHLSL/group_shared.hlsl
M clang/test/ParserHLSL/group_shared.hlsl
M clang/test/ParserHLSL/group_shared_202x.hlsl
M clang/test/SemaHLSL/Language/ImpCastAddrSpace.hlsl
Log Message:
-----------
[HLSL] groupshared variables should be implicitly extern and should not be initialized (#184459)
Makes groupshared variables have extern storage class which prevents
them from being initialized if no initializer is provided. If one is
provided as below:
```
groupshared uint A = 1;
```
A warning, which is an error by default, is produced that says the
initializer is ignored and the variable is NOT initialized.
Closes #183602
Commit: 5c08616df765da3b225880f7fed824040100ec6d
https://github.com/llvm/llvm-project/commit/5c08616df765da3b225880f7fed824040100ec6d
Author: Manuel Dun <manueldun at users.noreply.github.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/X86/known-pow2.ll
Log Message:
-----------
[DAG] isKnownToBeAPowerOfTwo - Power of 2 value is known to be power of 2 after BSWAP/BITREVERSE (#182207)
This is my first pr specifically for llvm
Fixes #181657
Allows the isKnownToBeAPowerOfTwo function to handle BSWAP and
BITREVERSE dag operations.
Commit: 585928482419bb66686ced6931320f1abb72a167
https://github.com/llvm/llvm-project/commit/585928482419bb66686ced6931320f1abb72a167
Author: Teresa Johnson <tejohnson at google.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemProfUse.cpp
M llvm/test/Transforms/PGOProfile/memprof-dump-matched-call-sites.ll
Log Message:
-----------
[MemProf] Add stack IDs to MemProfUse optimization remarks (#184670)
This makes the remarks more equivalent for analysis to what we emit to
stderr under -memprof-print-match-info.
Commit: 933e5368ba02ccb2c09eec1a7159bf3b647ee3ef
https://github.com/llvm/llvm-project/commit/933e5368ba02ccb2c09eec1a7159bf3b647ee3ef
Author: Vladislav Dzhidzhoev <vdzhidzhoev at accesssoftek.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/test/DebugInfo/Generic/cross-cu-linkonce-distinct.ll
Log Message:
-----------
[DebugInfo] Don't specify target triple for cross-cu-linkonce-distinct.ll (#184685)
Fixes buildbot failures after #184219.
Target triple line was added to this test in https://reviews.llvm.org/D144007, but it's needless.
Commit: f26ff8d86fd8e0e6754e60e4363ee156e856b3f1
https://github.com/llvm/llvm-project/commit/f26ff8d86fd8e0e6754e60e4363ee156e856b3f1
Author: cmtice <cmtice at google.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
A lldb/test/API/linux/linker-symbols/Makefile
A lldb/test/API/linux/linker-symbols/TestLinkerSymbols.py
A lldb/test/API/linux/linker-symbols/linker.script
A lldb/test/API/linux/linker-symbols/main.cpp
Log Message:
-----------
[LLDB] Allow symbols added by linker scripts to be examined. (#184679)
Symbols added by linker scripts do not have debug information or types,
but they do have addresses. Sometimes users need to see the addresses of
these symbols. Currently these symbols end up being assigned
'eSymbolTypeInvalid', so any attempt to look at them fails. This fixes
that issue.
Commit: d8e86a5cc0d5f0775faf5fc039a0c27e16dbdd61
https://github.com/llvm/llvm-project/commit/d8e86a5cc0d5f0775faf5fc039a0c27e16dbdd61
Author: Roy Shi <royitaqi at users.noreply.github.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/docs/CommandGuide/dsymutil.rst
A llvm/test/tools/dsymutil/AArch64/allow-disallow.test
A llvm/test/tools/dsymutil/Inputs/allow-disallow/a.out.arm64
A llvm/test/tools/dsymutil/Inputs/allow-disallow/empty.yaml
A llvm/test/tools/dsymutil/Inputs/allow-disallow/one.yaml
A llvm/test/tools/dsymutil/Inputs/allow-disallow/two.yaml
A llvm/test/tools/dsymutil/Inputs/private/tmp/allow-disallow/1.o
A llvm/test/tools/dsymutil/Inputs/private/tmp/allow-disallow/2.o
A llvm/test/tools/dsymutil/Inputs/private/tmp/allow-disallow/3.o
M llvm/test/tools/dsymutil/cmdline.test
M llvm/tools/dsymutil/DebugMap.cpp
M llvm/tools/dsymutil/DebugMap.h
M llvm/tools/dsymutil/MachODebugMapParser.cpp
M llvm/tools/dsymutil/Options.td
M llvm/tools/dsymutil/dsymutil.cpp
M llvm/tools/dsymutil/dsymutil.h
Log Message:
-----------
[dsymutil] Add option to filter debug map objects by allow/disallow-list (#182083)
# Motivation
When using `dsymutil` to generate dSYM for large binaries, sometimes we
want to keep only some of the object files. This has the benefits of
reduced dSYM size and improved performance of LLDB and other tools which
consume the dSYM.
The current way to achieve this is to use YAML input (the `dsymutil -y`
option). However, it doesn't really solve the problem:
1. The whole debug map has to be parsed somewhere else first, before
filtered down to the wanted parts.
2. Said info is written then read by `dsymutil`. The I/O is redundant.
# Change
This patch propose a new way, by adding new options (`dsymutil --allow
<path>` and `--disallow <path>`), which will only process object files
that pass the allow/disallow list.
Important details:
* The input file is YAML. See test files for format.
* Currently, only object files are filtered. The design allows to extend
the filtering to other aspects of the debug map in the future (e.g.
functions).
* If `--oso-prepend-path` is specified, it applies to the entries in the
input file. I.e. Entries in the input file should exact match that of
N_OSO entries.
Commit: 90c6e6374b9555279d6c31016bd7f4a8ee1861b4
https://github.com/llvm/llvm-project/commit/90c6e6374b9555279d6c31016bd7f4a8ee1861b4
Author: Berkay Sahin <berkaysahindev at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang-tools-extra/clang-tidy/readability/ElseAfterReturnCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/readability/else-after-return.cpp
Log Message:
-----------
[clang-tidy] Fix readability-else-after-return for if statements appear in unbraced switch case labels (#181878)
Fixes #160033.
Commit: ec15263cb898c2055f003810848ba590b6e8b42b
https://github.com/llvm/llvm-project/commit/ec15263cb898c2055f003810848ba590b6e8b42b
Author: Sam Clegg <sbc at chromium.org>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
R lld/test/wasm/Inputs/weak-alias.ll
A lld/test/wasm/Inputs/weak-alias.s
R lld/test/wasm/weak-alias-overide.ll
A lld/test/wasm/weak-alias-overide.s
R lld/test/wasm/weak-alias.ll
A lld/test/wasm/weak-alias.s
Log Message:
-----------
[lld][WebAssembly] Convert weak-alias tests to assembly. NFC (#184667)
This actually both improves and simplifies the `Inputs/weak_alias`. With
the `.ll` version we ended up using memory and `__stack_pointer` and
locals, but LLVM ended up generated `call` rather than `call_indirect`
for the `call_alias_ptr` and `call_direct_ptr`. With the assembly tests
we can ensure the usage of `call_indirect` while avoiding all the other
stuff.
Commit: ca0d100e79ef8c5c0a000375ce7652368617ad58
https://github.com/llvm/llvm-project/commit/ca0d100e79ef8c5c0a000375ce7652368617ad58
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Use VPlan::getZero to improve code (NFC) (#184591)
Commit: 954e5e7aa2e23d315a13fc052807d6600b182341
https://github.com/llvm/llvm-project/commit/954e5e7aa2e23d315a13fc052807d6600b182341
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
A clang/test/CIR/CodeGen/replace-global.cpp
Log Message:
-----------
[CIR] Upstream global variable replacement (#184686)
This change upstreams the CIR implementation of global variable
replacement. When we get a call to get or create a global variable using
a type that does not match the previous type for a variable of the same
name, we need to replace the old definition with the new one. In classic
codegen that was as simple as replaceAllUses+eraseFromParent, but in CIR
because we have typed pointers, we need to visit the uses and update
them with bitcasts to reflect the new type.
Commit: 9d1b6214fc0c2ec9794f61a562ed27d914df412d
https://github.com/llvm/llvm-project/commit/9d1b6214fc0c2ec9794f61a562ed27d914df412d
Author: Paul Kirth <paulkirth at google.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang-tools-extra/clang-doc/JSONGenerator.cpp
M clang-tools-extra/clang-doc/MDGenerator.cpp
M clang-tools-extra/clang-doc/Representation.cpp
M clang-tools-extra/clang-doc/Representation.h
M clang-tools-extra/test/clang-doc/namespace.cpp
Log Message:
-----------
[clang-doc] Sort index and avoid non-determinism (#184675)
Consolidate logic to get sorted children from StringMap.
Using the new API makes it more natural to not miss cases
where we missed sorting the children directly.
This also allows us to remove -DAG checks from tests and have
deterministic ordering.
Commit: 271458331747c595881c3768ca7439bd2f3d572c
https://github.com/llvm/llvm-project/commit/271458331747c595881c3768ca7439bd2f3d572c
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/split-vectorize-phi-user.ll
Log Message:
-----------
[SLP]Do not consider split vectorize nodes as vector phi nodes
Split vectorize nodes should not be considered as vector PHI nodes, when
trying to find the insertion point for the postpotned nodes.
Fixes #184585
Commit: 5a88dffc40d2ae422127deb75412b8f4dff20d8b
https://github.com/llvm/llvm-project/commit/5a88dffc40d2ae422127deb75412b8f4dff20d8b
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/test/CodeGen/AArch64/cpu-supports-target.c
M clang/test/CodeGen/AArch64/cpu-supports.c
M clang/test/CodeGen/AArch64/fmv-detection.c
M clang/test/CodeGen/AArch64/fmv-explicit-priority.c
M clang/test/CodeGen/AArch64/fmv-mix-explicit-implicit-default.c
M clang/test/CodeGen/AArch64/fmv-resolver-emission.c
M clang/test/CodeGen/AArch64/fmv-unreachable-version.c
M clang/test/CodeGen/AArch64/ls64.c
M clang/test/CodeGen/AArch64/mixed-target-attributes.c
M clang/test/CodeGen/AArch64/targetattr.c
M clang/test/CodeGen/LoongArch/targetattr-la32.c
M clang/test/CodeGen/LoongArch/targetattr-la64.c
M clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-00.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-01.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-03b.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-04.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-05.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-06.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-07.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-08.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-08b.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-09.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-09b.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-11.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-12.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-13.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-14.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-15.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-16.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-17.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-17b.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-18.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-19.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-20.cpp
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-21.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-22.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-23.c
M clang/test/CodeGen/amdgpu-abi-version.c
M clang/test/CodeGen/amdgpu-address-spaces.cpp
M clang/test/CodeGen/arm-metadata.c
M clang/test/CodeGen/asm-goto2.c
M clang/test/CodeGen/attr-target-clones-aarch64.c
M clang/test/CodeGen/attr-target-clones-riscv.c
M clang/test/CodeGen/attr-target-version-riscv.c
M clang/test/CodeGen/catch-implicit-integer-sign-changes-incdec.c
M clang/test/CodeGen/linux-kernel-struct-union-initializer.c
M clang/test/CodeGen/linux-kernel-struct-union-initializer2.c
M clang/test/CodeGen/memcpy-inline-builtin.c
M clang/test/CodeGen/nvptx_attributes.c
M clang/test/CodeGen/ptrauth-module-flags.c
M clang/test/CodeGen/sanitize-metadata-ignorelist.c
M clang/test/CodeGen/sanitize-metadata-nosanitize.c
M clang/test/CodeGen/sanitize-type-globals.cpp
M clang/test/CodeGen/stack-protector-guard.c
M clang/test/CodeGen/ubsan-function-sugared.cpp
M clang/test/CodeGen/ubsan-function.cpp
M clang/test/CodeGen/wasm-fp16.c
M clang/test/CodeGen/wchar-size.c
M clang/test/CodeGenCUDA/convergent.cu
M clang/test/CodeGenCXX/attr-target-clones-aarch64.cpp
M clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
M clang/test/CodeGenCXX/attr-target-version-riscv.cpp
M clang/test/CodeGenCXX/attr-target-version.cpp
M clang/test/CodeGenCXX/builtin-invoke.cpp
M clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
M clang/test/CodeGenCXX/fmv-namespace.cpp
M clang/test/CodeGenCXX/pfp-memcpy.cpp
M clang/test/CodeGenHIP/default-attributes.hip
M clang/test/CodeGenHIP/hip_weak_alias.cpp
M clang/test/CodeGenHIP/sanitize-undefined-null.hip
M clang/test/CodeGenOpenCL/amdgpu-cluster-dims.cl
M clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gws-insts.cl
M clang/test/CodeGenOpenCL/cl20-device-side-enqueue-attributes.cl
M clang/test/CodeGenSYCL/function-attrs.cpp
M clang/test/DebugInfo/CXX/ms-novtable.cpp
M clang/test/OpenMP/amdgcn_target_global_constructor.cpp
M clang/test/OpenMP/amdgcn_weak_alias.c
M clang/test/OpenMP/amdgcn_weak_alias.cpp
M clang/test/OpenMP/irbuilder_safelen.cpp
M clang/test/OpenMP/irbuilder_safelen_order_concurrent.cpp
M clang/test/OpenMP/irbuilder_simd_aligned.cpp
M clang/test/OpenMP/irbuilder_simdlen.cpp
M clang/test/OpenMP/irbuilder_simdlen_safelen.cpp
M clang/test/OpenMP/nvptx_weak_alias.c
M clang/test/OpenMP/tile_codegen_tile_for.cpp
M clang/test/utils/update_cc_test_checks/Inputs/annotations.c.expected
M clang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.generated.all.expected
M clang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.generated.expected
M clang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.no-generated.all.expected
M clang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.no-generated.expected
M clang/test/utils/update_cc_test_checks/Inputs/resolve-tmp-conflict.cpp.expected
M clang/test/utils/update_cc_test_checks/check-globals.test
M llvm/include/llvm/TargetParser/Triple.h
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/test/Transforms/InstCombine/wcslen-4.ll
M llvm/unittests/TargetParser/TripleTest.cpp
Log Message:
-----------
[Clang] Only define `wchar_size` module flag if non-standard (#184668)
Summary:
This PR simply changes the behavior of the `wchar_size` flag. Currently,
we emit this in all cases for all targets. This causes problems during
LLVM-IR linking, specifically because this would vary between Linux and
Windows in unintuitive ways. Now we have an llvm::Triple helper to
determine the size from the known values. The module flag will only be
emitted if these do not match (indicating a non-standard environment).
In addition to fixing AMDGCN bitcode linking, this also means we don't
need to bloat *every* IR module compiled by clang with this flag. The
changed tests reflects this, one less unnecessary piece of metadata.
Commit: 2be726dd8e22a328ea664c8e624eb541b173605c
https://github.com/llvm/llvm-project/commit/2be726dd8e22a328ea664c8e624eb541b173605c
Author: Vladislav Dzhidzhoev <vdzhidzhoev at accesssoftek.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/test/DebugInfo/Generic/dwarf5-debug-info-static-member.ll
Log Message:
-----------
[DebugInfo] Don't match wrong NULL in CHECK lines of dwarf5-debug-info-static-member.ll (#184694)
Fixes failure on clang-ppc64le-rhel buildbot
(https://lab.llvm.org/buildbot/#/builders/145/builds/13080) after
#184219.
On ppc64le, children are not produced for DW_TAG_subprogram "main" in
this test. Therefore, dwarfdump doesn't print NULL after this tag. On
other platforms (AArch64/X86), DW_TAG_subprogram has DW_TAG_variable
"instance_C", which should not be matched by the check lines.
Loosened the check lines (turned CHECK-NEXT into CHECK) to make them
work for all mentioned platforms.
Commit: cd6228983142ef5bf8bf7b5ca45ada749ff91cb0
https://github.com/llvm/llvm-project/commit/cd6228983142ef5bf8bf7b5ca45ada749ff91cb0
Author: Weiwen He <60433849+he-weiwen at users.noreply.github.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/X86/known-never-zero.ll
Log Message:
-----------
[DAG] isKnownNeverZero - add ISD::ADD/SUB DemandedElts handling and tests (#183958)
Closes #183043
Commit: 3a16cbe787885511d75d97f5da6af90858a8c184
https://github.com/llvm/llvm-project/commit/3a16cbe787885511d75d97f5da6af90858a8c184
Author: cmtice <cmtice at google.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M lldb/test/API/linux/linker-symbols/TestLinkerSymbols.py
Log Message:
-----------
[LLDB] Skip linker symbols test on Windows and MacOS. (#184690)
The test was only intended to run on linux.
Currently it's failing on the lldb-x86_64-win builder:
https://lab.llvm.org/buildbot/#/builders/211/builds/6741
Commit: f4a20a00d72901153100064da2bdbf134778d001
https://github.com/llvm/llvm-project/commit/f4a20a00d72901153100064da2bdbf134778d001
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/test/CIR/CodeGen/complex-compound-assignment.cpp
M clang/test/CIR/CodeGen/complex-mul-div.cpp
M clang/test/CIR/CodeGen/optsize-func-attr.cpp
Log Message:
-----------
[CIR][NFCI] Fixup some test regressions due to OGCG changes (#184699)
Discovered during CI in a different patch, 3 tests started failing for
unknown reasons due to some very mild changes to the IR, but only in
'classic' codgen parts of the tests. These tests were overly specific
for no good reason, so this patch just fixes that.
Commit: 521c2e14957a20bd0f13595cd4262443d841a3a4
https://github.com/llvm/llvm-project/commit/521c2e14957a20bd0f13595cd4262443d841a3a4
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M lldb/unittests/Host/SocketTest.cpp
M lldb/unittests/Interpreter/TestCompletion.cpp
M llvm/include/llvm/Support/FileSystem.h
M llvm/lib/Support/Path.cpp
M llvm/unittests/ExecutionEngine/Orc/LibraryResolverTest.cpp
M llvm/unittests/Support/Path.cpp
M llvm/unittests/Support/raw_socket_stream_test.cpp
Log Message:
-----------
[llvm][Support] Make createUniquePath require at least one wildcard marker (#184688)
The API was a bit easy to accidentally mis-use, as it silently accepted
Model strings without any randomness marker characters (`%`), which
results in a unique path that's not at all unique. To avoid this
foot-gun, we now assert that the model contains at least one, and update
all the broken usages accordingly.
rdar://170349565
Commit: 8c2d6cbc663962f3314b122dc511e0c1ff5e065e
https://github.com/llvm/llvm-project/commit/8c2d6cbc663962f3314b122dc511e0c1ff5e065e
Author: Jason Molenda <jmolenda at apple.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
M lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h
Log Message:
-----------
[lldb] Fix the AArch64 CPSR reg defn to list generic reg
My change to remove an incorrect DWARF register number for
CPSR unintentionally dropped the LLDB_REGNUM_GENERIC_FLAGS
generic reg type in the definitions of cpsr.
We need to have a macro (DEFINE_MISC_REGS) for status/control
registers that have no DWARF/eh_frame and no generic reg num.
I added a new macro, DEFINE_GPR_CPSR, for cpsr which is unique
in having no DWARF/eh_frame numbers but does have a generic
flags reg number.
Commit: cee0703cea3bb5cbf8ce9588de854f8b5417d9cc
https://github.com/llvm/llvm-project/commit/cee0703cea3bb5cbf8ce9588de854f8b5417d9cc
Author: John Harrison <harjohn at google.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
R lldb/test/API/python_api/block/TestBlocks.py
A lldb/test/API/python_api/block/TestFrameBlocks.py
M lldb/test/API/python_api/block/fn.c
M lldb/test/API/python_api/block/main.c
Log Message:
-----------
[lldb] Fixing the python_api/block tests. (#184647)
Renaming the file to be unique and updating the symbols for Windows.
Commit: 537f3d3a7588d226b86590f97c4401107585e1ce
https://github.com/llvm/llvm-project/commit/537f3d3a7588d226b86590f97c4401107585e1ce
Author: Jakob Koschel <jakobkoschel at google.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/CodeGen/SafeStack.cpp
A llvm/test/CodeGen/AArch64/safestack_scalar.ll
Log Message:
-----------
[SafeStack] Fix crashing with scalable TypeSizes (#180547)
On e.g. aarch64 the TypeSize of scalar types can have a size that is not
known at compile time.
Currently when safestack occurs those it simply crashes as described in
https://github.com/llvm/llvm-project/issues/175868.
Since we cannot verify the size at compile time we simply consider the
access to be unsafe (in regards to safestack).
Reproducer:
```
#include <arm_sve.h>
int main() {
svint32_t vec = svindex_s32(0, 1);
svint32_t res = svadd_s32_z(svptrue_b32(), vec, vec);
int32_t buffer[1024];
svst1_s32(svptrue_b32(), buffer, res);
return 0;
}
```
Commit: 18b648c9f8cfc62c5560565abd702ee1460adccd
https://github.com/llvm/llvm-project/commit/18b648c9f8cfc62c5560565abd702ee1460adccd
Author: Wenju He <wenju.he at intel.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M libclc/CMakeLists.txt
M libclc/clc/lib/generic/async/clc_prefetch.inc
M libclc/clc/lib/generic/math/clc_cosh.inc
M libclc/clc/lib/generic/math/clc_erfc.cl
M libclc/clc/lib/generic/math/clc_expm1.inc
M libclc/clc/lib/generic/math/clc_fmod.cl
M libclc/clc/lib/generic/math/clc_sincos_helpers_fp64.inc
M libclc/clc/lib/generic/workitem/clc_get_sub_group_id.cl
M libclc/clc/lib/ptx-nvidiacl/mem_fence/clc_mem_fence.cl
M libclc/clc/lib/ptx-nvidiacl/synchronization/clc_work_group_barrier.cl
M libclc/opencl/lib/generic/async/wait_group_events.cl
Log Message:
-----------
[libclc][NFC] Add -Wall -Wextra to build flags and fix build warnings (#184549)
Co-authored-by: Copilot <175728472+Copilot at users.noreply.github.com>
Commit: 576c244dc91421a6ac96c14f9bc4cc0975009433
https://github.com/llvm/llvm-project/commit/576c244dc91421a6ac96c14f9bc4cc0975009433
Author: jimingham <jingham at apple.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
A lldb/test/API/functionalities/breakpoint/breakpoint_conditions/crashing_condition/Makefile
A lldb/test/API/functionalities/breakpoint/breakpoint_conditions/crashing_condition/TestCrashingCondition.py
A lldb/test/API/functionalities/breakpoint/breakpoint_conditions/crashing_condition/main.c
Log Message:
-----------
Add a test for handling a crashing breakpoint condition (#184247)
I was working on something and broke the handling of breakpoint
conditions that crash. In fixing that I noticed that there wasn't a test
for this scenario, so this PR adds one.
---------
Co-authored-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: bfe349ccf4b4c8694824dafedb8c9ef78bf80725
https://github.com/llvm/llvm-project/commit/bfe349ccf4b4c8694824dafedb8c9ef78bf80725
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
M llvm/test/CodeGen/AMDGPU/vgpr-setreg-mode-swar.mir
Log Message:
-----------
[AMDGPU] Optimize S_SETREG_IMM32_B32 piggybacking by treating it as a mode scope boundary (#184703)
When `handleSetregMode` encounters an `S_SETREG_IMM32_B32` with `Size <=
12`, the instruction's `imm32[12:19]` bits are "free" for VGPR MSB
piggybacking. Previously, the old mode was eagerly written into these
bits, but the `Rewritten` guard in `setMode` would then block subsequent
piggybacking when the next VGPR instruction needed a different mode,
causing an unnecessary `S_SET_VGPR_MSB` to be emitted.
Model the `S_SETREG_IMM32_B32` as the boundary of the old mode's control
range: reset `CurrentMode` and clear `bits[12:19]` to zero. This lets
the next `setMode` call freely piggyback the required mode without
triggering `Rewritten`.
Commit: 442757579ee4999de8d6f05513de07022f918037
https://github.com/llvm/llvm-project/commit/442757579ee4999de8d6f05513de07022f918037
Author: Emmanuel Antonio <emmanuelac at google.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M llvm/tools/dsymutil/DebugMap.h
Log Message:
-----------
[dsymutil] Add DebugMapObjectFilter destructor (#184701)
Fixes #182083.
Commit: 6b7a3b311a8675f4b82e22d8420e24c7f1612fdc
https://github.com/llvm/llvm-project/commit/6b7a3b311a8675f4b82e22d8420e24c7f1612fdc
Author: Victor Chernyakin <chernyakin.victor.j at outlook.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang-tools-extra/clang-tidy/performance/FasterStringFindCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/performance/faster-string-find.rst
M clang-tools-extra/test/clang-tidy/checkers/performance/faster-string-find.cpp
Log Message:
-----------
[clang-tidy] Teach `performance-faster-string-find` about `operator+=` (#182697)
This is a followup to #182633. Like in that PR, `operator+=` doesn't fit
with the check name, but the same optimization is applicable to it:
https://en.cppreference.com/w/cpp/string/basic_string/operator+=.html
Commit: 61d8e5ca791f55753d5aebbd6175dc8c5d6b54ef
https://github.com/llvm/llvm-project/commit/61d8e5ca791f55753d5aebbd6175dc8c5d6b54ef
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp
M mlir/test/Dialect/Affine/SuperVectorize/vector_utils.mlir
Log Message:
-----------
[MLIR][Vector] Fix crash in operatesOnSuperVectorsOf on rank-mismatched shaped (#183967)
The `operatesOnSuperVectorsOf` function in VectorUtils.cpp contained an
assertion that fired when a `vector.transfer` operation's vector type
had a different rank (or non-divisible shape) from the sub-vector type
supplied by the caller:
assert((ratio || \!mustDivide) &&
"vector.transfer operation in which super-vector size is not an"
" integer multiple of sub-vector size");
This assertion was incorrect because the function's callers (e.g., the
affine super-vectorizer) legitimately pass transfer ops whose vector
type doesn't match the requested sub-vector shape. In those cases the
correct answer is simply that the op does not operate on a super-vector
of that sub-vector type, so `operatesOnSuperVectorsOf` should return
`false`.
Remove the assert return `false` when `computeShapeRatio` produces no
result, and remove the now-unused `mustDivide` variable.
Fixes #149327
Fixes #131096
Commit: d07ab183b6695a6262c251d24bb86d4b977aff3d
https://github.com/llvm/llvm-project/commit/d07ab183b6695a6262c251d24bb86d4b977aff3d
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M mlir/lib/IR/Verifier.cpp
M mlir/unittests/IR/CMakeLists.txt
A mlir/unittests/IR/VerifierTest.cpp
Log Message:
-----------
[mlir] Add cross-context checks to the IR verifier (#184627)
Detect IR where result types, operand types, or discardable attribute
values come from a different MLIRContext than the operation itself.
Mixing contexts is a latent use-after-free hazard when one context is
destroyed before the other; the verifier now reports a clear error
instead of silently allowing the invalid IR through.
Three new unit tests in MLIRIRTests cover each scenario.
Fix #61569
Commit: c32caeec8158d634bb71ab8911a6031248b9fc47
https://github.com/llvm/llvm-project/commit/c32caeec8158d634bb71ab8911a6031248b9fc47
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
M mlir/test/Conversion/ConvertToSPIRV/func-signature-vector-unroll.mlir
Log Message:
-----------
[mlir][spirv] Fix crash in FuncOpVectorUnroll for dynamic-shaped tensor args (#184626)
FuncOpVectorUnroll::matchAndRewrite iterates over all function arguments
and creates a zero-constant placeholder for any non-vector argument via
rewriter.getZeroAttr(type). For dynamically-shaped tensor types such as
tensor<?x2xi8>, getZeroAttr ultimately calls
DenseIntOrFPElementsAttr::getRaw which asserts that the type has a
static shape.
Add an early pre-check that returns failure() for any non-vector
argument with a dynamically-shaped type. This must be done before any IR
modifications are made, since returning failure() after inlining the
function body would leave the IR in an inconsistent state.
Fixes #148369
Commit: 90ba731c496b9ccf7fd3954756f5d096add3d0b5
https://github.com/llvm/llvm-project/commit/90ba731c496b9ccf7fd3954756f5d096add3d0b5
Author: Twice <twice at apache.org>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M mlir/python/mlir/dialects/ext.py
Log Message:
-----------
[MLIR][Python] Add `replace` parameter to `Dialect.load` (#184604)
In this PR, `replace` keyword parameter is added to `Dialect.load(..)`
in `mlir.dialects.ext`. It's to replace existing registered
operations/types/attrs.
Commit: f0142833b6a542618a19ec9f9836b51c051945cf
https://github.com/llvm/llvm-project/commit/f0142833b6a542618a19ec9f9836b51c051945cf
Author: Twice <twice at apache.org>
Date: 2026-03-05 (Thu, 05 Mar 2026)
Changed paths:
M mlir/lib/Bindings/Python/Rewrite.cpp
Log Message:
-----------
[MLIR][Python] Move operation/dialect name retrieving as a util function (#184605)
We have a common pattern that retrieve an operation name or dialect name
from a `type` or `str` in the rewrite nanobind module, so better to make
it a common util function.
---------
Co-authored-by: Rolf Morel <rolfmorel at gmail.com>
Commit: 6653187e22d154287555ef7586a6288ea962eac7
https://github.com/llvm/llvm-project/commit/6653187e22d154287555ef7586a6288ea962eac7
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M .github/workflows/containers/github-action-ci-tooling/Dockerfile
M .github/workflows/containers/github-action-ci-windows/Dockerfile
M .github/workflows/containers/github-action-ci/Dockerfile
M .github/workflows/spirv-tests.yml
M clang-tools-extra/Maintainers.rst
M clang-tools-extra/clang-doc/CMakeLists.txt
M clang-tools-extra/clang-doc/Generators.cpp
M clang-tools-extra/clang-doc/Generators.h
M clang-tools-extra/clang-doc/JSONGenerator.cpp
M clang-tools-extra/clang-doc/MDGenerator.cpp
A clang-tools-extra/clang-doc/MDMustacheGenerator.cpp
M clang-tools-extra/clang-doc/Representation.cpp
M clang-tools-extra/clang-doc/Representation.h
M clang-tools-extra/clang-doc/YAMLGenerator.cpp
A clang-tools-extra/clang-doc/assets/md/all-files-template.mustache
A clang-tools-extra/clang-doc/assets/md/class-template.mustache
A clang-tools-extra/clang-doc/assets/md/comments-partial.mustache
A clang-tools-extra/clang-doc/assets/md/index-template.mustache
A clang-tools-extra/clang-doc/assets/md/namespace-template.mustache
A clang-tools-extra/clang-doc/benchmarks/CMakeLists.txt
A clang-tools-extra/clang-doc/benchmarks/ClangDocBenchmark.cpp
M clang-tools-extra/clang-doc/support/Utils.cpp
M clang-tools-extra/clang-doc/support/Utils.h
M clang-tools-extra/clang-doc/tool/CMakeLists.txt
M clang-tools-extra/clang-doc/tool/ClangDocMain.cpp
M clang-tools-extra/clang-tidy/bugprone/StdNamespaceModificationCheck.cpp
M clang-tools-extra/clang-tidy/misc/ConstCorrectnessCheck.cpp
M clang-tools-extra/clang-tidy/performance/FasterStringFindCheck.cpp
M clang-tools-extra/clang-tidy/readability/ElseAfterReturnCheck.cpp
M clang-tools-extra/clang-tidy/readability/RedundantPreprocessorCheck.cpp
M clang-tools-extra/clang-tidy/readability/RedundantTypenameCheck.cpp
M clang-tools-extra/clangd/Preamble.cpp
M clang-tools-extra/clangd/XRefs.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/const-correctness.rst
M clang-tools-extra/docs/clang-tidy/checks/performance/faster-string-find.rst
M clang-tools-extra/test/clang-doc/basic-project.mustache.test
M clang-tools-extra/test/clang-doc/builtin_types.cpp
M clang-tools-extra/test/clang-doc/comments-in-macros.cpp
M clang-tools-extra/test/clang-doc/enum.cpp
M clang-tools-extra/test/clang-doc/index.cpp
M clang-tools-extra/test/clang-doc/json/class.cpp
M clang-tools-extra/test/clang-doc/json/namespace.cpp
M clang-tools-extra/test/clang-doc/namespace.cpp
M clang-tools-extra/test/clang-doc/templates.cpp
M clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/system-header-simulation.h
A clang-tools-extra/test/clang-tidy/checkers/bugprone/implicit-widening-of-multiplication-result-options.cpp
A clang-tools-extra/test/clang-tidy/checkers/bugprone/not-null-terminated-result-no-safe-functions.c
A clang-tools-extra/test/clang-tidy/checkers/bugprone/signed-char-misuse-no-comparison.cpp
A clang-tools-extra/test/clang-tidy/checkers/bugprone/sizeof-expression-disable-options.cpp
M clang-tools-extra/test/clang-tidy/checkers/bugprone/std-namespace-modification.cpp
A clang-tools-extra/test/clang-tidy/checkers/bugprone/string-constructor-options.cpp
A clang-tools-extra/test/clang-tidy/checkers/bugprone/suspicious-missing-comma-options.cpp
A clang-tools-extra/test/clang-tidy/checkers/bugprone/suspicious-string-compare-custom-functions.cpp
A clang-tools-extra/test/clang-tidy/checkers/bugprone/suspicious-stringview-data-usage-options.cpp
A clang-tools-extra/test/clang-tidy/checkers/bugprone/unused-return-value-checked-return-types.cpp
M clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-parameters.cpp
M clang-tools-extra/test/clang-tidy/checkers/performance/faster-string-find.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/else-after-return.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/redundant-preprocessor.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/redundant-typename.cpp
M clang-tools-extra/unittests/clang-doc/ClangDocTest.cpp
M clang-tools-extra/unittests/clang-doc/GeneratorTest.cpp
M clang-tools-extra/unittests/clang-doc/HTMLGeneratorTest.cpp
M clang-tools-extra/unittests/clang-doc/JSONGeneratorTest.cpp
M clang/docs/ReleaseNotes.rst
M clang/include/clang/APINotes/APINotesReader.h
M clang/include/clang/AST/ASTMutationListener.h
A clang/include/clang/AST/pch.h
M clang/include/clang/Analysis/Analyses/LifetimeSafety/LifetimeAnnotations.h
M clang/include/clang/Analysis/Analyses/UnsafeBufferUsage.h
M clang/include/clang/Analysis/Analyses/UnsafeBufferUsageGadgets.def
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsAMDGPU.td
M clang/include/clang/Basic/BuiltinsAMDGPUDocs.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/LangOptions.h
M clang/include/clang/Basic/OpenCLExtensions.def
M clang/include/clang/Basic/TargetCXXABI.h
M clang/include/clang/CIR/Dialect/Builder/CIRBaseBuilder.h
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Dialect/IR/CIRTypeConstraints.td
M clang/include/clang/CIR/Dialect/Passes.h
M clang/include/clang/CIR/Dialect/Passes.td
M clang/include/clang/CIR/Interfaces/CIROpInterfaces.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Options/Options.td
M clang/include/clang/Serialization/ASTWriter.h
M clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/RangedConstraintManager.h
M clang/lib/APINotes/APINotesManager.cpp
M clang/lib/APINotes/APINotesReader.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/EvalEmitter.cpp
M clang/lib/AST/ByteCode/InterpBuiltin.cpp
M clang/lib/AST/ByteCode/Program.cpp
M clang/lib/AST/ByteCode/Record.cpp
M clang/lib/AST/CMakeLists.txt
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/Randstruct.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/lib/Analysis/LifetimeSafety/LifetimeAnnotations.cpp
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/lib/Basic/FileManager.cpp
M clang/lib/Basic/Targets/AVR.cpp
M clang/lib/Basic/Targets/OSTargets.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenOpenACCRecipe.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.h
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/Transforms/CMakeLists.txt
A clang/lib/CIR/Dialect/Transforms/EHABILowering.cpp
M clang/lib/CIR/Dialect/Transforms/FlattenCFG.cpp
M clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerItaniumCXXABI.cpp
M clang/lib/CIR/Lowering/CIRPasses.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.h
M clang/lib/CodeGen/CGAtomic.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CGHLSLRuntime.h
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/lib/CodeGen/ModuleBuilder.cpp
M clang/lib/Driver/CreateASTUnitFromArgs.cpp
M clang/lib/Driver/Distro.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/OffloadBundler.cpp
M clang/lib/Driver/ToolChains/AIX.cpp
M clang/lib/Driver/ToolChains/Arch/X86.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Frontend/MultiplexConsumer.cpp
M clang/lib/Frontend/VerifyDiagnosticConsumer.cpp
M clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
A clang/lib/Headers/.clang-format-ignore
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/amdhsa_abi.h
M clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h
M clang/lib/Headers/hvx_hexagon_protos.h
M clang/lib/Interpreter/IncrementalParser.cpp
M clang/lib/Lex/Lexer.cpp
M clang/lib/Lex/LiteralSupport.cpp
M clang/lib/Lex/PPExpressions.cpp
M clang/lib/Options/DriverOptions.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Sema/AnalysisBasedWarnings.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaCoroutine.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/Sema/SemaOpenACCClauseAppertainment.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Serialization/ASTCommon.h
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/StaticAnalyzer/Checkers/ErrnoModeling.cpp
M clang/lib/StaticAnalyzer/Checkers/IvarInvalidationChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/VirtualCallChecker.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineCXX.cpp
M clang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp
M clang/lib/Tooling/DependencyScanningTool.cpp
A clang/test/Analysis/Inputs/virtualcall-system-header.h
M clang/test/Analysis/missing-z3-nocrash.c
M clang/test/Analysis/virtualcall.cpp
M clang/test/CIR/CodeGen/assign-operator.cpp
M clang/test/CIR/CodeGen/atomic-thread-fence.c
M clang/test/CIR/CodeGen/atomic.c
M clang/test/CIR/CodeGen/basic.c
M clang/test/CIR/CodeGen/basic.cpp
M clang/test/CIR/CodeGen/binop.cpp
A clang/test/CIR/CodeGen/bitfield-assignment-loc.c
M clang/test/CIR/CodeGen/bitfields.c
A clang/test/CIR/CodeGen/c89-implicit-int.c
M clang/test/CIR/CodeGen/complex-compound-assignment.cpp
M clang/test/CIR/CodeGen/complex-mul-div.cpp
M clang/test/CIR/CodeGen/complex.cpp
M clang/test/CIR/CodeGen/compound_assign.cpp
A clang/test/CIR/CodeGen/expressions.cpp
A clang/test/CIR/CodeGen/gnu-ptr-math.c
M clang/test/CIR/CodeGen/if.cpp
M clang/test/CIR/CodeGen/integer-overflow.c
M clang/test/CIR/CodeGen/lambda.cpp
M clang/test/CIR/CodeGen/namespace.cpp
M clang/test/CIR/CodeGen/new.cpp
M clang/test/CIR/CodeGen/no-odr-use.cpp
M clang/test/CIR/CodeGen/non-type-template-param.cpp
M clang/test/CIR/CodeGen/opaque.cpp
M clang/test/CIR/CodeGen/optsize-func-attr.cpp
M clang/test/CIR/CodeGen/pointer-to-data-member-cast.cpp
M clang/test/CIR/CodeGen/pointer-to-member-func-cast.cpp
M clang/test/CIR/CodeGen/pointer-to-member-func-cmp.cpp
M clang/test/CIR/CodeGen/pointer-to-member-func.cpp
A clang/test/CIR/CodeGen/replace-global.cpp
M clang/test/CIR/CodeGen/requires-expr.cpp
M clang/test/CIR/CodeGen/size-of-vla.cpp
M clang/test/CIR/CodeGen/struct-init.cpp
M clang/test/CIR/CodeGen/switch_flat_op.cpp
M clang/test/CIR/CodeGen/ternary.cpp
M clang/test/CIR/CodeGen/throws.cpp
M clang/test/CIR/CodeGen/try-catch-tmp.cpp
M clang/test/CIR/CodeGen/try-catch.cpp
M clang/test/CIR/CodeGen/var-arg-aggregate.c
M clang/test/CIR/CodeGen/var_arg.c
M clang/test/CIR/CodeGen/variable-decomposition.cpp
M clang/test/CIR/CodeGen/vector-ext-element.cpp
M clang/test/CIR/CodeGen/vector-ext.cpp
M clang/test/CIR/CodeGen/vector.cpp
M clang/test/CIR/CodeGen/vla.c
M clang/test/CIR/CodeGenBuiltins/AArch64/acle_sve_len.c
M clang/test/CIR/CodeGenBuiltins/X86/avx10_2_512bf16-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/avx10_2bf16-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/avx2-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/avx512bw-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/avx512dq-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/avx512fp16-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/avx512vldq-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/cmp-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/sse2-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/sse41-builtins.c
A clang/test/CIR/CodeGenBuiltins/builtin-isinf-sign.c
A clang/test/CIR/CodeGenCUDA/kernel-args.cu
A clang/test/CIR/CodeGenCXX/vtable-pure-deleted-funcs.cpp
M clang/test/CIR/CodeGenOpenACC/atomic-capture.cpp
M clang/test/CIR/CodeGenOpenACC/atomic-update.cpp
M clang/test/CIR/CodeGenOpenACC/atomic-write.cpp
M clang/test/CIR/CodeGenOpenACC/combined-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/combined-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-default-ops.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-float.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-int.cpp
M clang/test/CIR/CodeGenOpenACC/combined-reduction-clause-outline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/combined.cpp
M clang/test/CIR/CodeGenOpenACC/compute-firstprivate-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.c
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-default-ops.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-float.c
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-float.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-int.c
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-int.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-outline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-unsigned-int.c
M clang/test/CIR/CodeGenOpenACC/firstprivate-clause-recipes.cpp
M clang/test/CIR/CodeGenOpenACC/loop-private-clause.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-default-ops.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-float.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-inline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-int.cpp
M clang/test/CIR/CodeGenOpenACC/loop-reduction-clause-outline-ops.cpp
M clang/test/CIR/CodeGenOpenACC/loop.cpp
M clang/test/CIR/CodeGenOpenACC/private-clause-array-recipes-CtorDtor.cpp
M clang/test/CIR/CodeGenOpenACC/private-clause-pointer-array-recipes-CtorDtor.cpp
M clang/test/CIR/CodeGenOpenACC/private-clause-pointer-array-recipes-NoOps.cpp
M clang/test/CIR/CodeGenOpenACC/private-clause-pointer-array-recipes-int.cpp
M clang/test/CIR/CodeGenOpenACC/private-clause-pointer-recipes-CtorDtor.cpp
M clang/test/CIR/CodeGenOpenACC/private-clause-pointer-recipes-NoOps.cpp
M clang/test/CIR/CodeGenOpenACC/private-clause-pointer-recipes-int.cpp
M clang/test/CIR/CodeGenOpenACC/reduction-clause-recipes.cpp
M clang/test/CIR/CodeGenOpenMP/omp-llvmir.c
M clang/test/CIR/CodeGenOpenMP/parallel.c
M clang/test/CIR/IR/throw.cir
M clang/test/CIR/IR/vector.cir
M clang/test/CIR/Lowering/binop-bool.cir
M clang/test/CIR/Lowering/binop-fp.cir
M clang/test/CIR/Lowering/binop-signed-int.cir
M clang/test/CIR/Lowering/binop-unsigned-int.cir
A clang/test/CIR/Transforms/eh-abi-lowering-itanium.cir
M clang/test/CIR/Transforms/flatten-try-op.cir
M clang/test/CIR/Transforms/switch.cir
M clang/test/CodeGen/AArch64/cpu-supports-target.c
M clang/test/CodeGen/AArch64/cpu-supports.c
M clang/test/CodeGen/AArch64/fmv-detection.c
M clang/test/CodeGen/AArch64/fmv-explicit-priority.c
M clang/test/CodeGen/AArch64/fmv-mix-explicit-implicit-default.c
M clang/test/CodeGen/AArch64/fmv-resolver-emission.c
M clang/test/CodeGen/AArch64/fmv-unreachable-version.c
M clang/test/CodeGen/AArch64/ls64.c
M clang/test/CodeGen/AArch64/mixed-target-attributes.c
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
M clang/test/CodeGen/AArch64/targetattr.c
M clang/test/CodeGen/LoongArch/targetattr-la32.c
M clang/test/CodeGen/LoongArch/targetattr-la64.c
M clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-00.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-01.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-03b.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-04.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-05.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-06.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-07.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-08.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-08b.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-09.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-09b.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-11.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-12.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-13.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-14.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-15.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-16.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-17.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-17b.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-18.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-19.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-20.cpp
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-21.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-22.c
M clang/test/CodeGen/SystemZ/vec-abi-gnuattr-23.c
M clang/test/CodeGen/amdgpu-abi-version.c
M clang/test/CodeGen/amdgpu-address-spaces.cpp
M clang/test/CodeGen/arm-metadata.c
M clang/test/CodeGen/asm-goto2.c
M clang/test/CodeGen/atomic-arm64.c
M clang/test/CodeGen/atomic-ops.c
M clang/test/CodeGen/attr-target-clones-aarch64.c
M clang/test/CodeGen/attr-target-clones-riscv.c
M clang/test/CodeGen/attr-target-version-riscv.c
M clang/test/CodeGen/big-atomic-ops.c
M clang/test/CodeGen/catch-implicit-integer-sign-changes-incdec.c
M clang/test/CodeGen/linux-kernel-struct-union-initializer.c
M clang/test/CodeGen/linux-kernel-struct-union-initializer2.c
M clang/test/CodeGen/memcpy-inline-builtin.c
M clang/test/CodeGen/nvptx_attributes.c
M clang/test/CodeGen/ptrauth-module-flags.c
M clang/test/CodeGen/sanitize-metadata-ignorelist.c
M clang/test/CodeGen/sanitize-metadata-nosanitize.c
M clang/test/CodeGen/sanitize-type-globals.cpp
M clang/test/CodeGen/stack-protector-guard.c
M clang/test/CodeGen/ubsan-function-sugared.cpp
M clang/test/CodeGen/ubsan-function.cpp
M clang/test/CodeGen/wasm-fp16.c
M clang/test/CodeGen/wchar-size.c
M clang/test/CodeGenCUDA/convergent.cu
M clang/test/CodeGenCXX/attr-target-clones-aarch64.cpp
M clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
M clang/test/CodeGenCXX/attr-target-version-riscv.cpp
M clang/test/CodeGenCXX/attr-target-version.cpp
M clang/test/CodeGenCXX/builtin-invoke.cpp
M clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
M clang/test/CodeGenCXX/fmv-namespace.cpp
M clang/test/CodeGenCXX/pfp-member-pointer-offsetof.cpp
M clang/test/CodeGenCXX/pfp-memcpy.cpp
A clang/test/CodeGenCoroutines/coro-gro3.cpp
M clang/test/CodeGenHIP/default-attributes.hip
M clang/test/CodeGenHIP/hip_weak_alias.cpp
M clang/test/CodeGenHIP/sanitize-undefined-null.hip
A clang/test/CodeGenHLSL/builtins/WaveActiveAllEqual.hlsl
M clang/test/CodeGenHLSL/group_shared.hlsl
M clang/test/CodeGenOpenCL/amdgpu-cluster-dims.cl
M clang/test/CodeGenOpenCL/amdgpu-enqueue-kernel.cl
M clang/test/CodeGenOpenCL/amdgpu-ieee.cl
M clang/test/CodeGenOpenCL/atomic-ops.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-tensor-load-store.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gws-insts.cl
M clang/test/CodeGenOpenCL/cl20-device-side-enqueue-attributes.cl
M clang/test/CodeGenSYCL/function-attrs.cpp
A clang/test/DebugInfo/CXX/debug-info-constexpr-array.cpp
M clang/test/DebugInfo/CXX/ms-novtable.cpp
M clang/test/Driver/hip-save-temps.hip
M clang/test/Driver/hip-spirv-backend-bindings.c
M clang/test/Driver/hip-spirv-backend-phases.c
M clang/test/Driver/hip-toolchain-no-rdc.hip
M clang/test/Driver/spirv-amd-toolchain.c
A clang/test/Driver/x86_64-fixed-r-register.c
A clang/test/Headers/amdhsa_abi.cl
A clang/test/Headers/hexagon-hvx-ieee-headers.c
A clang/test/Interpreter/verify-diagnostics.cpp
A clang/test/Modules/Inputs/pch-config-macros/include/Mod1.h
A clang/test/Modules/Inputs/pch-config-macros/include/module.modulemap
A clang/test/Modules/demote-var-def.cpp
A clang/test/Modules/module-init-forcelly-loaded-module.cpp
A clang/test/Modules/pch-config-macros.c
A clang/test/Modules/pr149404-02.cppm
A clang/test/Modules/pr172241.cppm
A clang/test/Modules/var-inst-def.cppm
M clang/test/OpenMP/amdgcn_target_global_constructor.cpp
M clang/test/OpenMP/amdgcn_weak_alias.c
M clang/test/OpenMP/amdgcn_weak_alias.cpp
A clang/test/OpenMP/for_range_loop_codegen.cpp
M clang/test/OpenMP/irbuilder_safelen.cpp
M clang/test/OpenMP/irbuilder_safelen_order_concurrent.cpp
M clang/test/OpenMP/irbuilder_simd_aligned.cpp
M clang/test/OpenMP/irbuilder_simdlen.cpp
M clang/test/OpenMP/irbuilder_simdlen_safelen.cpp
M clang/test/OpenMP/nvptx_weak_alias.c
M clang/test/OpenMP/parallel_for_codegen.cpp
M clang/test/OpenMP/target_indirect_codegen.cpp
A clang/test/OpenMP/target_vtable_omp_indirect_call_lookup.cpp
M clang/test/OpenMP/tile_codegen_tile_for.cpp
M clang/test/ParserHLSL/group_shared.hlsl
M clang/test/ParserHLSL/group_shared_202x.hlsl
A clang/test/Preprocessor/miopt-peek-restore-header-guard.cpp
M clang/test/Preprocessor/predefined-win-macros.c
M clang/test/Sema/Inputs/lifetime-analysis.h
M clang/test/Sema/atomic-ops.c
M clang/test/Sema/scoped-atomic-ops.c
M clang/test/Sema/warn-lifetime-analysis-nocfg.cpp
M clang/test/Sema/warn-lifetime-safety-invalidations.cpp
A clang/test/SemaCXX/attr-exclude_from_explicit_instantiation.ignore-dllattr.cpp
A clang/test/SemaCXX/warn-unsafe-buffer-usage-string-view.cpp
A clang/test/SemaHLSL/BuiltIns/WaveActiveAllEqual-errors.hlsl
M clang/test/SemaHLSL/Language/ImpCastAddrSpace.hlsl
M clang/test/SemaOpenCL/extension-version.cl
M clang/test/SemaTemplate/concepts.cpp
M clang/test/lit.cfg.py
M clang/test/utils/update_cc_test_checks/Inputs/annotations.c.expected
M clang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.generated.all.expected
M clang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.generated.expected
M clang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.no-generated.all.expected
M clang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.no-generated.expected
M clang/test/utils/update_cc_test_checks/Inputs/resolve-tmp-conflict.cpp.expected
M clang/test/utils/update_cc_test_checks/check-globals.test
M clang/tools/cir-opt/cir-opt.cpp
M clang/tools/clang-sycl-linker/ClangSYCLLinker.cpp
M clang/unittests/Lex/LexerTest.cpp
M clang/utils/hmaptool/CMakeLists.txt
M compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h
M compiler-rt/test/cfi/icall/bad-signature.c
M compiler-rt/test/lsan/TestCases/create_thread_leak.cpp
M flang-rt/CMakeLists.txt
M flang/docs/OpenACC.md
M flang/include/flang/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.h
M flang/lib/Lower/OpenMP/ClauseProcessor.cpp
M flang/lib/Lower/OpenMP/DataSharingProcessor.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.cpp
M flang/lib/Optimizer/OpenACC/Support/RegisterOpenACCExtensions.cpp
M flang/lib/Parser/prescan.cpp
M flang/lib/Parser/prescan.h
M flang/lib/Semantics/canonicalize-acc.cpp
M flang/lib/Semantics/check-acc-structure.cpp
M flang/lib/Semantics/check-acc-structure.h
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Lower/Intrinsics/adjustr.f90
M flang/test/Lower/Intrinsics/all.f90
M flang/test/Lower/Intrinsics/any.f90
M flang/test/Lower/Intrinsics/asinpi.f90
M flang/test/Lower/Intrinsics/associated.f90
M flang/test/Lower/Intrinsics/atan2d.f90
M flang/test/Lower/Intrinsics/atan2pi.f90
M flang/test/Lower/Intrinsics/atand.f90
M flang/test/Lower/Intrinsics/atanpi.f90
M flang/test/Lower/Intrinsics/bessel_jn.f90
M flang/test/Lower/OpenMP/composite_simd_linear.f90
M flang/test/Lower/OpenMP/distribute-parallel-do-simd.f90
M flang/test/Lower/OpenMP/distribute-simd.f90
A flang/test/Lower/OpenMP/implicit-map-pointer-no-default-mapper.f90
M flang/test/Lower/OpenMP/loop-pointer-variable.f90
M flang/test/Lower/OpenMP/ordered-simd.f90
M flang/test/Lower/OpenMP/target-data-skip-mapper-calls.f90
M flang/test/Lower/OpenMP/wsloop-simd.f90
A flang/test/Parser/not-sentinel.f90
M flang/test/Semantics/OpenACC/acc-cache-validity.f90
M flang/test/Semantics/OpenACC/acc-canonicalization-validity.f90
M flang/test/Semantics/OpenMP/resolve05.f90
A flang/test/Transforms/OpenACC/acc-recipe-materialization-firstprivate-derived.fir
A flang/test/Transforms/OpenACC/acc-recipe-materialization-firstprivate.fir
A flang/test/Transforms/OpenACC/acc-recipe-materialization-kernel-private.fir
A flang/test/Transforms/OpenACC/acc-recipe-materialization-parallel.fir
A flang/test/Transforms/OpenACC/acc-recipe-materialization-private.fir
A flang/test/Transforms/OpenACC/acc-recipe-materialization-reduction.fir
M flang/tools/f18/CMakeLists.txt
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/config/baremetal/aarch64/entrypoints.txt
M libc/config/baremetal/arm/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/config/linux/x86_64/headers.txt
M libc/hdr/types/CMakeLists.txt
A libc/hdr/types/key_t.h
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-macros/CMakeLists.txt
M libc/include/llvm-libc-macros/linux/CMakeLists.txt
A libc/include/llvm-libc-macros/linux/sys-ipc-macros.h
A libc/include/llvm-libc-macros/sys-ipc-macros.h
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/key_t.h
A libc/include/llvm-libc-types/struct_ipc_perm.h
A libc/include/sys/ipc.yaml
M libc/include/sys/types.yaml
M libc/src/__support/GPU/allocator.cpp
M libc/src/stdio/baremetal/CMakeLists.txt
A libc/src/stdio/baremetal/fflush.cpp
A libc/src/stdio/baremetal/file_internal.cpp
M libc/src/stdio/baremetal/file_internal.h
M libc/src/stdio/baremetal/getc.cpp
A libc/src/stdio/baremetal/ungetc.cpp
M libc/src/stdio/baremetal/vfscanf_internal.h
M libc/src/sys/CMakeLists.txt
A libc/src/sys/ipc/CMakeLists.txt
A libc/src/sys/ipc/ftok.h
A libc/src/sys/ipc/linux/CMakeLists.txt
A libc/src/sys/ipc/linux/ftok.cpp
A libc/src/sys/ipc/linux/kernel_statx.h
M libc/test/include/CMakeLists.txt
M libc/test/integration/CMakeLists.txt
M libc/test/src/sys/CMakeLists.txt
A libc/test/src/sys/ipc/CMakeLists.txt
A libc/test/src/sys/ipc/linux/CMakeLists.txt
A libc/test/src/sys/ipc/linux/ftok_test.cpp
M libc/utils/libctest/format.py
M libclc/CMakeLists.txt
M libclc/clc/lib/amdgcn/workitem/clc_get_global_offset.cl
M libclc/clc/lib/amdgcn/workitem/clc_get_work_dim.cl
M libclc/clc/lib/generic/async/clc_prefetch.inc
M libclc/clc/lib/generic/math/clc_cosh.inc
M libclc/clc/lib/generic/math/clc_erfc.cl
M libclc/clc/lib/generic/math/clc_expm1.inc
M libclc/clc/lib/generic/math/clc_fmod.cl
M libclc/clc/lib/generic/math/clc_sincos_helpers_fp64.inc
M libclc/clc/lib/generic/workitem/clc_get_sub_group_id.cl
M libclc/clc/lib/ptx-nvidiacl/mem_fence/clc_mem_fence.cl
M libclc/clc/lib/ptx-nvidiacl/synchronization/clc_work_group_barrier.cl
M libclc/cmake/modules/AddLibclc.cmake
M libclc/opencl/lib/generic/async/wait_group_events.cl
M libcxx/include/string
M libcxx/test/benchmarks/numeric/gcd.bench.cpp
M libcxx/test/benchmarks/streams/getline.bench.cpp
M libcxx/test/benchmarks/streams/ofstream.bench.cpp
M libcxx/test/std/strings/basic.string/string.cons/constexpr_initialization_stress.pass.cpp
M libcxx/utils/libcxx/test/dsl.py
M libsycl/docs/index.rst
A libsycl/include/sycl/__impl/async_handler.hpp
A libsycl/include/sycl/__impl/detail/default_async_handler.hpp
A libsycl/include/sycl/__impl/property_list.hpp
A libsycl/include/sycl/__impl/queue.hpp
M libsycl/include/sycl/sycl.hpp
M libsycl/src/CMakeLists.txt
A libsycl/src/detail/queue_impl.cpp
A libsycl/src/detail/queue_impl.hpp
A libsycl/src/queue.cpp
M libunwind/src/Unwind-wasm.c
M lld/COFF/Driver.cpp
M lld/ELF/Arch/ARM.cpp
M lld/ELF/Arch/Hexagon.cpp
M lld/ELF/Arch/LoongArch.cpp
M lld/ELF/Arch/Mips.cpp
M lld/ELF/Arch/PPC.cpp
M lld/ELF/Arch/PPC64.cpp
M lld/ELF/Arch/X86.cpp
M lld/ELF/Arch/X86_64.cpp
M lld/ELF/Config.h
M lld/ELF/InputSection.cpp
M lld/ELF/Relocations.cpp
M lld/ELF/Relocations.h
M lld/ELF/SyntheticSections.cpp
M lld/ELF/SyntheticSections.h
M lld/ELF/Target.h
A lld/test/ELF/hexagon-duplex-relocs.s
R lld/test/wasm/Inputs/archive1.ll
A lld/test/wasm/Inputs/archive1.s
R lld/test/wasm/Inputs/archive2.ll
A lld/test/wasm/Inputs/archive2.s
R lld/test/wasm/Inputs/archive3.ll
A lld/test/wasm/Inputs/archive3.s
R lld/test/wasm/Inputs/weak-alias.ll
A lld/test/wasm/Inputs/weak-alias.s
M lld/test/wasm/archive-export.test
R lld/test/wasm/archive.ll
A lld/test/wasm/archive.s
M lld/test/wasm/debuginfo.test
R lld/test/wasm/weak-alias-overide.ll
A lld/test/wasm/weak-alias-overide.s
R lld/test/wasm/weak-alias.ll
A lld/test/wasm/weak-alias.s
M lld/wasm/OutputSections.cpp
M lldb/docs/dil-expr-lang.ebnf
M lldb/examples/python/formatter_bytecode.py
M lldb/include/lldb/API/SBBlock.h
M lldb/include/lldb/Core/Debugger.h
M lldb/include/lldb/Host/LZMA.h
M lldb/include/lldb/Target/Process.h
M lldb/include/lldb/Utility/LLDBLog.h
M lldb/include/lldb/ValueObject/DILAST.h
M lldb/include/lldb/ValueObject/DILEval.h
M lldb/source/API/SBBlock.cpp
M lldb/source/Commands/CommandObjectApropos.cpp
M lldb/source/Commands/CommandObjectBreakpointCommand.cpp
M lldb/source/Commands/CommandObjectPlatform.cpp
M lldb/source/Commands/CommandObjectSource.cpp
M lldb/source/Commands/CommandObjectType.cpp
M lldb/source/Commands/CommandObjectVersion.cpp
M lldb/source/Commands/CommandObjectWatchpoint.cpp
M lldb/source/Commands/CommandObjectWatchpointCommand.cpp
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/PluginManager.cpp
M lldb/source/Initialization/SystemInitializerCommon.cpp
M lldb/source/Plugins/ABI/AArch64/ABIAArch64.cpp
M lldb/source/Plugins/LanguageRuntime/CPlusPlus/ItaniumABI/ItaniumABILanguageRuntime.cpp
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
M lldb/source/Plugins/Process/FreeBSD-Kernel-Core/ProcessFreeBSDKernelCore.cpp
M lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.cpp
M lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDPLog.cpp
M lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDPLog.h
M lldb/source/Plugins/Process/POSIX/ProcessPOSIXLog.cpp
M lldb/source/Plugins/Process/POSIX/ProcessPOSIXLog.h
M lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm64.cpp
M lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
M lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessWindowsLog.cpp
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemoteLog.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemoteLog.h
M lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp
M lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp
M lldb/source/Plugins/Process/minidump/RegisterContextMinidump_ARM64.cpp
M lldb/source/Plugins/Process/scripted/ScriptedProcess.cpp
M lldb/source/Plugins/Process/wasm/ProcessWasm.cpp
M lldb/source/Plugins/RegisterTypeBuilder/RegisterTypeBuilderClang.cpp
M lldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.cpp
M lldb/source/Plugins/ScriptInterpreter/None/ScriptInterpreterNone.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Utility/ARM64_DWARF_Registers.h
M lldb/source/Utility/ARM64_ehframe_Registers.h
M lldb/source/Utility/LLDBLog.cpp
M lldb/source/ValueObject/DILAST.cpp
M lldb/source/ValueObject/DILEval.cpp
M lldb/source/ValueObject/DILParser.cpp
M lldb/test/API/commands/frame/var-dil/basics/BitFieldExtraction/TestFrameVarDILBitFieldExtraction.py
M lldb/test/API/commands/frame/var-dil/expr/Arithmetic/TestFrameVarDILArithmetic.py
M lldb/test/API/commands/frame/var-dil/expr/Arithmetic/main.cpp
A lldb/test/API/functionalities/breakpoint/breakpoint_conditions/crashing_condition/Makefile
A lldb/test/API/functionalities/breakpoint/breakpoint_conditions/crashing_condition/TestCrashingCondition.py
A lldb/test/API/functionalities/breakpoint/breakpoint_conditions/crashing_condition/main.c
M lldb/test/API/lang/cpp/template/TestTemplateArgs.py
A lldb/test/API/linux/linker-symbols/Makefile
A lldb/test/API/linux/linker-symbols/TestLinkerSymbols.py
A lldb/test/API/linux/linker-symbols/linker.script
A lldb/test/API/linux/linker-symbols/main.cpp
A lldb/test/API/python_api/block/Makefile
A lldb/test/API/python_api/block/TestFrameBlocks.py
A lldb/test/API/python_api/block/fn.c
A lldb/test/API/python_api/block/main.c
M lldb/test/API/python_api/event/TestEvents.py
M lldb/test/API/python_api/type/TestTypeList.py
M lldb/unittests/DAP/TestBase.cpp
M lldb/unittests/DAP/TestBase.h
M lldb/unittests/DAP/VariablesTest.cpp
M lldb/unittests/Host/SocketTest.cpp
M lldb/unittests/Interpreter/TestCompletion.cpp
M lldb/unittests/Target/CMakeLists.txt
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/CommandGuide/dsymutil.rst
M llvm/docs/DirectX/DXILResources.rst
M llvm/docs/LangRef.rst
M llvm/docs/NVPTXUsage.rst
M llvm/include/llvm/ADT/APFloat.h
M llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h
M llvm/include/llvm/Analysis/DependenceAnalysis.h
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/RuntimeLibcallUtil.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/MC/MCAssembler.h
M llvm/include/llvm/Support/FileSystem.h
M llvm/include/llvm/Support/GenericDomTreeConstruction.h
M llvm/include/llvm/TableGen/CodeGenHelpers.h
M llvm/include/llvm/TargetParser/Triple.h
M llvm/include/llvm/Transforms/IPO/Attributor.h
M llvm/lib/Analysis/CmpInstAnalysis.cpp
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/DXILResource.cpp
M llvm/lib/Analysis/DependenceAnalysis.cpp
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Analysis/InlineCost.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CAS/OnDiskCommon.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
M llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/RegisterClassInfo.cpp
M llvm/lib/CodeGen/SafeStack.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/LibraryScanner.cpp
M llvm/lib/IR/ConstantRange.cpp
M llvm/lib/IR/RuntimeLibcalls.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/LTO/LTO.cpp
M llvm/lib/MC/MCAssembler.cpp
M llvm/lib/MC/MCParser/AsmParser.cpp
M llvm/lib/MC/MCParser/MasmParser.cpp
M llvm/lib/MC/XCOFFObjectWriter.cpp
M llvm/lib/Support/APFixedPoint.cpp
M llvm/lib/Support/APFloat.cpp
M llvm/lib/Support/Path.cpp
M llvm/lib/Target/AArch64/AArch64.h
M llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrAtomics.td
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
A llvm/lib/Target/AArch64/AArch64PassRegistry.def
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h
M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCKernelDescriptor.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/MIMGInstructions.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.cpp
M llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.cpp
M llvm/lib/Target/ARM/ARMAsmPrinter.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMCallLowering.cpp
M llvm/lib/Target/ARM/ARMFrameLowering.cpp
M llvm/lib/Target/ARM/ARMInstrThumb2.td
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILResourceAccess.cpp
M llvm/lib/Target/DirectX/DXILShaderFlags.cpp
M llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp
M llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp
M llvm/lib/Target/M68k/GISel/M68kCallLowering.h
M llvm/lib/Target/Mips/MipsCallLowering.cpp
M llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
M llvm/lib/Target/PowerPC/GISel/PPCCallLowering.h
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
M llvm/lib/Target/RISCV/RISCVMoveMerger.cpp
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/lib/Target/RISCV/RISCVSchedAndes45.td
M llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
M llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVBaseInfo.h
M llvm/lib/Target/SPIRV/SPIRVAPI.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVCombinerHelper.cpp
M llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
M llvm/lib/Target/SPIRV/SPIRVCommandLine.h
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
M llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
M llvm/lib/Target/SPIRV/SPIRVSubtarget.h
M llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
M llvm/lib/Target/WebAssembly/WebAssembly.td
M llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td
M llvm/lib/Target/WebAssembly/WebAssemblyInstrCall.td
M llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td
M llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h
M llvm/lib/Target/X86/GISel/X86CallLowering.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/X86/X86Subtarget.cpp
M llvm/lib/Target/X86/X86Subtarget.h
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/MemProfUse.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/lib/Transforms/Scalar/NewGVN.cpp
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
M llvm/lib/Transforms/Utils/SplitModuleByCategory.cpp
M llvm/lib/Transforms/Utils/VNCoercion.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanCFG.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Analysis/DDG/print-dot-ddg.ll
A llvm/test/Analysis/DXILResource/buffer-frombinding-unbounded.ll
M llvm/test/Analysis/DependenceAnalysis/Banerjee.ll
M llvm/test/Analysis/DependenceAnalysis/BasePtrBug.ll
M llvm/test/Analysis/DependenceAnalysis/Constraints.ll
M llvm/test/Analysis/DependenceAnalysis/DADelin.ll
M llvm/test/Analysis/DependenceAnalysis/DifferentOffsets.ll
M llvm/test/Analysis/DependenceAnalysis/ExactRDIV.ll
M llvm/test/Analysis/DependenceAnalysis/FlipFlopBaseAddress.ll
M llvm/test/Analysis/DependenceAnalysis/MIVCheckConst.ll
M llvm/test/Analysis/DependenceAnalysis/MismatchingNestLevels.ll
M llvm/test/Analysis/DependenceAnalysis/NonAffineExpr.ll
M llvm/test/Analysis/DependenceAnalysis/PR21585.ll
M llvm/test/Analysis/DependenceAnalysis/PR51512.ll
M llvm/test/Analysis/DependenceAnalysis/Preliminary.ll
M llvm/test/Analysis/DependenceAnalysis/Propagating.ll
M llvm/test/Analysis/DependenceAnalysis/SimpleSIVNoValidityCheck.ll
M llvm/test/Analysis/DependenceAnalysis/SimpleSIVNoValidityCheckFixedSize.ll
M llvm/test/Analysis/DependenceAnalysis/StrongSIV.ll
M llvm/test/Analysis/DependenceAnalysis/SymbolicRDIV.ll
M llvm/test/Analysis/DependenceAnalysis/SymbolicSIV.ll
M llvm/test/Analysis/DependenceAnalysis/UsefulGEP.ll
M llvm/test/Analysis/DependenceAnalysis/WeakCrossingSIV.ll
M llvm/test/Analysis/DependenceAnalysis/WeakZeroDstSIV.ll
M llvm/test/Analysis/DependenceAnalysis/WeakZeroSrcSIV.ll
M llvm/test/Analysis/DependenceAnalysis/ZIV.ll
M llvm/test/Analysis/DependenceAnalysis/becount-couldnotcompute.ll
M llvm/test/Analysis/DependenceAnalysis/compute-absolute-value.ll
M llvm/test/Analysis/DependenceAnalysis/exact-rdiv-addrec-wrap.ll
M llvm/test/Analysis/DependenceAnalysis/exact-siv-addrec-wrap.ll
M llvm/test/Analysis/DependenceAnalysis/exact-siv-overflow.ll
M llvm/test/Analysis/DependenceAnalysis/gcd-miv-overflow.ll
M llvm/test/Analysis/DependenceAnalysis/infer_affine_domain_ovlf.ll
M llvm/test/Analysis/DependenceAnalysis/lcssa.ll
M llvm/test/Analysis/DependenceAnalysis/monotonicity-cast.ll
M llvm/test/Analysis/DependenceAnalysis/monotonicity-invariant.ll
M llvm/test/Analysis/DependenceAnalysis/rdiv-large-btc.ll
M llvm/test/Analysis/DependenceAnalysis/rdiv-minor-algebra.ll
M llvm/test/Analysis/DependenceAnalysis/run-specific-dependence-test.ll
M llvm/test/Analysis/DependenceAnalysis/same-sd-for-diff-becount-type-loops.ll
M llvm/test/Analysis/DependenceAnalysis/strong-siv-large-btc.ll
M llvm/test/Analysis/DependenceAnalysis/strong-siv-overflow.ll
M llvm/test/Analysis/DependenceAnalysis/symbolic-rdiv-addrec-wrap.ll
M llvm/test/Analysis/DependenceAnalysis/symbolic-rdiv-overflow.ll
M llvm/test/Analysis/DependenceAnalysis/weak-crossing-siv-addrec-wrap.ll
M llvm/test/Analysis/DependenceAnalysis/weak-crossing-siv-large-btc.ll
M llvm/test/Analysis/DependenceAnalysis/weak-crossing-siv-overflow.ll
M llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-large-btc.ll
M llvm/test/Analysis/DependenceAnalysis/weak-zero-siv-overflow.ll
A llvm/test/Analysis/DependenceAnalysis/weak_zero_siv_parametric_coeff.ll
A llvm/test/Analysis/DependenceAnalysis/weak_zero_siv_parametric_const.ll
M llvm/test/Analysis/DependenceAnalysis/zero-coefficient.ll
M llvm/test/CodeGen/AArch64/aarch64-addv.ll
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/aarch64-pmull2.ll
M llvm/test/CodeGen/AArch64/aarch64-scal-to-vec-bitcast-insert.ll
M llvm/test/CodeGen/AArch64/arm64-cvt-simd-intrinsics.ll
M llvm/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll
M llvm/test/CodeGen/AArch64/arm64-fmax-safe.ll
M llvm/test/CodeGen/AArch64/arm64-int-neon.ll
M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
M llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll
M llvm/test/CodeGen/AArch64/arm64-neon-v8.1a.ll
M llvm/test/CodeGen/AArch64/arm64-vcvt.ll
M llvm/test/CodeGen/AArch64/arm64-vqadd.ll
M llvm/test/CodeGen/AArch64/arm64-vshift.ll
M llvm/test/CodeGen/AArch64/avoid-pre-trunc.ll
M llvm/test/CodeGen/AArch64/bitcast-extend.ll
M llvm/test/CodeGen/AArch64/bitcnt-i256.ll
M llvm/test/CodeGen/AArch64/clmul-fixed.ll
M llvm/test/CodeGen/AArch64/clmul-scalable.ll
M llvm/test/CodeGen/AArch64/clmul.ll
M llvm/test/CodeGen/AArch64/combine-sdiv.ll
M llvm/test/CodeGen/AArch64/concat-vector-add-combine.ll
M llvm/test/CodeGen/AArch64/ctpop.ll
A llvm/test/CodeGen/AArch64/dso_local_equivalent.ll
A llvm/test/CodeGen/AArch64/extend_vecreduce_add.ll
M llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
M llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
M llvm/test/CodeGen/AArch64/fsh.ll
A llvm/test/CodeGen/AArch64/neon-extractbitcast-mir.ll
M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
A llvm/test/CodeGen/AArch64/safestack_scalar.ll
M llvm/test/CodeGen/AArch64/select-bitcast.ll
M llvm/test/CodeGen/AArch64/sext.ll
M llvm/test/CodeGen/AArch64/sme-streaming-checkvl.ll
M llvm/test/CodeGen/AArch64/srem-vec-crash.ll
M llvm/test/CodeGen/AArch64/stp-opt-with-renaming-ld3.mir
M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
M llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll
M llvm/test/CodeGen/AArch64/sve-fixed-vector-lrint.ll
M llvm/test/CodeGen/AArch64/veclib-llvm.pow.ll
M llvm/test/CodeGen/AArch64/vector-llrint.ll
M llvm/test/CodeGen/AArch64/vector-lrint.ll
M llvm/test/CodeGen/AArch64/zext.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-ignore-copies-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-acos.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-acosh.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-acospi.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-asin.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-asinh.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-asinpi.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-atan.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-atanh.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-atanpi.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cbrt.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cos.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cosh.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-cospi.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-erf.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-erfc.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-exp.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-exp10.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-exp2.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-expm1.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-log.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-log10.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-log2.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-rsqrt.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sin.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sinh.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sinpi.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-sqrt.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tan.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tanh.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tanpi.ll
A llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-tdo-tgamma.ll
M llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-default.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll
A llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp-on.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll
A llvm/test/CodeGen/AMDGPU/arbitrary-fp-to-float.ll
M llvm/test/CodeGen/AMDGPU/ashr64_reduce.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-vgpr-limit.ll
A llvm/test/CodeGen/AMDGPU/bfe-i8-i16.ll
M llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
M llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll
R llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill-xfail.ll
A llvm/test/CodeGen/AMDGPU/call-args-inreg-no-sgpr-for-csrspill.ll
M llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
M llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir
M llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
M llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll
M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/hazards-gfx950.mir
M llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll
M llvm/test/CodeGen/AMDGPU/iglp-no-clobber.ll
M llvm/test/CodeGen/AMDGPU/implicit-arg-block-count.ll
M llvm/test/CodeGen/AMDGPU/implicit-arg-v5-opt.ll
M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.16x16x128.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tensor.load.store.ll
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
M llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
M llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
A llvm/test/CodeGen/AMDGPU/machine-sink-fence.ll
M llvm/test/CodeGen/AMDGPU/mai-hazards.mir
M llvm/test/CodeGen/AMDGPU/misched-remat-revert.ll
M llvm/test/CodeGen/AMDGPU/no-limit-coalesce.mir
M llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-no-fold-exec-copy.mir
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
M llvm/test/CodeGen/AMDGPU/reg-coalescer-subreg-liveness.mir
M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
M llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
M llvm/test/CodeGen/AMDGPU/sdag-print-divergence.ll
M llvm/test/CodeGen/AMDGPU/shl64_reduce.ll
M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
M llvm/test/CodeGen/AMDGPU/srl64_reduce.ll
M llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
M llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
M llvm/test/CodeGen/AMDGPU/vgpr-setreg-mode-swar.mir
M llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll
M llvm/test/CodeGen/ARM/fminmax-folds.ll
M llvm/test/CodeGen/ARM/pow.ll
M llvm/test/CodeGen/ARM/vminmaxnm-safe.ll
A llvm/test/CodeGen/DirectX/ResourceAccess/handle-cases.ll
A llvm/test/CodeGen/DirectX/ResourceAccess/handle-to-index.ll
A llvm/test/CodeGen/DirectX/ResourceAccess/non-unique.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll
A llvm/test/CodeGen/DirectX/WaveActiveAllEqual.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
A llvm/test/CodeGen/MIR/Generic/machine-function-empty-name-no-ir-section.mir
A llvm/test/CodeGen/MIR/Generic/machine-function-empty-name-no-matching-ir.mir
A llvm/test/CodeGen/MIR/Generic/machine-function-empty-name.mir
A llvm/test/CodeGen/NVPTX/arbitrary-fp-to-float.ll
A llvm/test/CodeGen/PowerPC/aix-reloc-sorting.ll
M llvm/test/CodeGen/PowerPC/clmul-vector.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vadd.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vfadd.ll
M llvm/test/CodeGen/RISCV/copysign-casts.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-mem.ll
M llvm/test/CodeGen/RISCV/double-select-fcmp.ll
M llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
M llvm/test/CodeGen/RISCV/opt-w-instrs.mir
M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
M llvm/test/CodeGen/RISCV/rv64p.ll
M llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
M llvm/test/CodeGen/RISCV/rvv/clmul-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/clmulh-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-clmul.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
M llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
M llvm/test/CodeGen/RISCV/rvv/nontemporal-vp-scalable.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vabd.ll
M llvm/test/CodeGen/RISCV/rvv/vabdu.ll
M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt.ll
M llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
M llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-service-func.ll
A llvm/test/CodeGen/SPIRV/global-var-no-functions.ll
A llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveAllEqual.ll
M llvm/test/CodeGen/SPIRV/legalize-zero-size-arrays-global.ll
M llvm/test/CodeGen/SPIRV/legalize-zero-size-arrays-nested.ll
M llvm/test/CodeGen/SPIRV/legalize-zero-size-arrays-struct.ll
M llvm/test/CodeGen/SPIRV/legalize-zero-size-arrays-undef.ll
A llvm/test/CodeGen/SPIRV/pointers/fun-ptr-to-itself.ll
M llvm/test/CodeGen/SPIRV/pointers/fun-with-aggregate-arg-in-const-init.ll
M llvm/test/CodeGen/SPIRV/transcoding/OpExtInst_vector_promotion_bug.ll
A llvm/test/CodeGen/SPIRV/user-function-with-builtin-name.ll
M llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
A llvm/test/CodeGen/Thumb2/pacbti-m-bxaut.ll
M llvm/test/CodeGen/WebAssembly/atomic-fence.mir
M llvm/test/CodeGen/WebAssembly/call-pic.ll
M llvm/test/CodeGen/WebAssembly/call.ll
M llvm/test/CodeGen/WebAssembly/function-bitcasts.ll
M llvm/test/CodeGen/WebAssembly/load-ext.ll
M llvm/test/CodeGen/WebAssembly/multivalue.ll
M llvm/test/CodeGen/WebAssembly/reg-stackify.ll
A llvm/test/CodeGen/WebAssembly/simd-memcmp.ll
M llvm/test/CodeGen/WebAssembly/swiftcc.ll
M llvm/test/CodeGen/WebAssembly/tailcall.ll
M llvm/test/CodeGen/X86/AMX/amx-low-intrinsics-no-amx-bitcast.ll
M llvm/test/CodeGen/X86/AMX/amx-low-intrinsics.ll
A llvm/test/CodeGen/X86/arbitrary-fp-convert-error.ll
A llvm/test/CodeGen/X86/arbitrary-fp-to-float.ll
M llvm/test/CodeGen/X86/clmul-vector-256.ll
M llvm/test/CodeGen/X86/clmul-vector-512.ll
M llvm/test/CodeGen/X86/clmul-vector.ll
M llvm/test/CodeGen/X86/combine-fcopysign.ll
M llvm/test/CodeGen/X86/dbg-distringtype-uint.ll
M llvm/test/CodeGen/X86/fmaxnum.ll
M llvm/test/CodeGen/X86/fminnum.ll
A llvm/test/CodeGen/X86/funnel-shift-i256.ll
M llvm/test/CodeGen/X86/known-never-zero.ll
M llvm/test/CodeGen/X86/known-pow2.ll
A llvm/test/CodeGen/X86/mulx64-no-implicit-copy.ll
A llvm/test/CodeGen/X86/reserveRreg.ll
M llvm/test/CodeGen/X86/shift-i256.ll
A llvm/test/CodeGen/X86/veclib-llvm.sincos.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll
M llvm/test/DebugInfo/AArch64/DW_AT_APPLE_enum_kind.ll
M llvm/test/DebugInfo/AMDGPU/variable-locations.ll
M llvm/test/DebugInfo/Generic/cross-cu-linkonce-distinct.ll
M llvm/test/DebugInfo/Generic/debug-names-linkage-name.ll
M llvm/test/DebugInfo/Generic/dwarf5-debug-info-static-member.ll
M llvm/test/DebugInfo/Generic/inlined-static-var.ll
M llvm/test/DebugInfo/Generic/namespace.ll
M llvm/test/DebugInfo/MSP430/global-var.ll
M llvm/test/DebugInfo/NVPTX/debug-addr-class.ll
M llvm/test/DebugInfo/PowerPC/strict-dwarf.ll
M llvm/test/DebugInfo/WebAssembly/tls_pic_globals.ll
M llvm/test/DebugInfo/X86/2011-09-26-GlobalVarContext.ll
M llvm/test/DebugInfo/X86/DW_AT_calling-convention.ll
M llvm/test/DebugInfo/X86/align_cpp11.ll
M llvm/test/DebugInfo/X86/align_objc.ll
M llvm/test/DebugInfo/X86/arange-and-stub.ll
M llvm/test/DebugInfo/X86/containing-type-extension-rust.ll
M llvm/test/DebugInfo/X86/debug-info-access.ll
A llvm/test/DebugInfo/X86/debug-info-constexpr-array.ll
M llvm/test/DebugInfo/X86/debug-info-static-member.ll
M llvm/test/DebugInfo/X86/debug-names-dwarf64.ll
M llvm/test/DebugInfo/X86/dwarf-aranges.ll
M llvm/test/DebugInfo/X86/dwarf-linkage-names.ll
M llvm/test/DebugInfo/X86/dwarfdump-DIImportedEntity_elements.ll
M llvm/test/DebugInfo/X86/generate-odr-hash.ll
M llvm/test/DebugInfo/X86/gnu-public-names.ll
M llvm/test/DebugInfo/X86/linkage-name.ll
M llvm/test/DebugInfo/X86/namelist1.ll
M llvm/test/DebugInfo/X86/prototyped.ll
M llvm/test/DebugInfo/X86/ref_addr_relocation.ll
M llvm/test/DebugInfo/X86/string-offsets-multiple-cus.ll
M llvm/test/DebugInfo/X86/string-offsets-table.ll
M llvm/test/DebugInfo/X86/template.ll
M llvm/test/DebugInfo/X86/tls.ll
M llvm/test/DebugInfo/X86/tu-to-non-tu.ll
M llvm/test/DebugInfo/X86/vla-global.ll
M llvm/test/DebugInfo/attr-btf_tag.ll
M llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope.ll
M llvm/test/MC/AMDGPU/hsa-diag-v4.s
A llvm/test/MC/ELF/relax-branch-align.s
M llvm/test/MC/ELF/rtti-proxy-gotpcrel.ll
M llvm/test/MC/RISCV/rv32p-valid.s
M llvm/test/MC/RISCV/rv64p-valid.s
A llvm/test/MC/WebAssembly/atomics-orderings-errors.s
A llvm/test/MC/WebAssembly/atomics-orderings.s
M llvm/test/MC/WebAssembly/debug-info.ll
M llvm/test/MC/WebAssembly/debug-info64.ll
M llvm/test/MC/WebAssembly/dwarfdump.ll
M llvm/test/MC/WebAssembly/dwarfdump64.ll
A llvm/test/MC/X86/align-branch-convergence.s
A llvm/test/TableGen/ArtificialRegs.td
A llvm/test/Transforms/Attributor/nofpclass-bitcast.ll
M llvm/test/Transforms/Attributor/nofpclass.ll
M llvm/test/Transforms/DeadStoreElimination/noop-stores.ll
A llvm/test/Transforms/GVN/svcount-access.ll
M llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-dx10-clamp.ll
M llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-ieee.ll
A llvm/test/Transforms/InstCombine/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
M llvm/test/Transforms/InstCombine/binop-phi-operands.ll
M llvm/test/Transforms/InstCombine/fmul.ll
M llvm/test/Transforms/InstCombine/getelementptr.ll
M llvm/test/Transforms/InstCombine/icmp-binop.ll
M llvm/test/Transforms/InstCombine/or-select-zero-icmp.ll
M llvm/test/Transforms/InstCombine/recurrence.ll
M llvm/test/Transforms/InstCombine/select.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass-aggregates.ll
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
M llvm/test/Transforms/InstCombine/wcslen-4.ll
M llvm/test/Transforms/InstSimplify/ConstProp/min-max.ll
M llvm/test/Transforms/InstSimplify/fminmax-folds.ll
A llvm/test/Transforms/LoopVectorize/AArch64/early_exit_with_stores.ll
A llvm/test/Transforms/LoopVectorize/RISCV/early_exit_with_stores.ll
M llvm/test/Transforms/LoopVectorize/VPlan/conditional-scalar-assignment-vplan.ll
A llvm/test/Transforms/LoopVectorize/VPlan/early_exit_with_stores_vplan.ll
M llvm/test/Transforms/LoopVectorize/early_exit_store_legality.ll
A llvm/test/Transforms/LoopVectorize/early_exit_with_stores.ll
M llvm/test/Transforms/LoopVectorize/find-last.ll
M llvm/test/Transforms/LoopVectorize/if-pred-stores.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
A llvm/test/Transforms/LoopVectorize/tail-folding-masked-mem-opts.ll
M llvm/test/Transforms/PGOProfile/memprof-dump-matched-call-sites.ll
M llvm/test/Transforms/SLPVectorizer/X86/extracts-non-extendable.ll
M llvm/test/Transforms/SLPVectorizer/X86/non-load-reduced-as-part-of-bv.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
A llvm/test/Transforms/SLPVectorizer/X86/split-vectorize-phi-user.ll
M llvm/test/Transforms/SLPVectorizer/reduction-gather-non-scheduled-extracts.ll
M llvm/test/Transforms/Util/DeclareRuntimeLibcalls/armpl.ll
M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
A llvm/test/tools/dsymutil/AArch64/allow-disallow.test
A llvm/test/tools/dsymutil/Inputs/allow-disallow/a.out.arm64
A llvm/test/tools/dsymutil/Inputs/allow-disallow/empty.yaml
A llvm/test/tools/dsymutil/Inputs/allow-disallow/one.yaml
A llvm/test/tools/dsymutil/Inputs/allow-disallow/two.yaml
A llvm/test/tools/dsymutil/Inputs/private/tmp/allow-disallow/1.o
A llvm/test/tools/dsymutil/Inputs/private/tmp/allow-disallow/2.o
A llvm/test/tools/dsymutil/Inputs/private/tmp/allow-disallow/3.o
M llvm/test/tools/dsymutil/cmdline.test
M llvm/test/tools/llvm-debuginfo-analyzer/DWARF/crash-thread-local-storage.test
R llvm/test/tools/llvm-mca/AArch64/Apple/Inputs/basic-instructions.s
R llvm/test/tools/llvm-mca/AArch64/Apple/Inputs/neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Apple/M1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Apple/M1-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A57-basic-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Inputs/basic-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Inputs/bf16-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Inputs/complxnum-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Inputs/fp16fml-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Inputs/fptoint-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Inputs/i8mm-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Inputs/mte-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Inputs/neon-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Inputs/rcpc-immo-instructions.s
A llvm/test/tools/llvm-mca/AArch64/Inputs/sve-instructions.s
R llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/basic-instructions.s
R llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/bf16-instructions.s
R llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/complxnum-instructions.s
R llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/fp16fml-instructions.s
R llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/fptoint-instructions.s
R llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/i8mm-instructions.s
R llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/mte-instructions.s
R llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/neon-instructions.s
R llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/rcpc-immo-instructions.s
R llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/sve-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-bf16-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-complxnum-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-fp16fml-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-fptoint-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-i8mm-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-mte-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-rcpc-immo-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-bf16-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-complxnum-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-fp16fml-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-fptoint-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-i8mm-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-mte-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-rcpc-immo-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-bf16-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-complxnum-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-fp16fml-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-i8mm-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-rcpc-immo-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-bf16-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-complxnum-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-fp16fml-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-fptoint-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-i8mm-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-mte-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-rcpc-immo-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-sve-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-bf16-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-complxnum-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-fp16fml-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-fptoint-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-i8mm-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-mte-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-rcpc-immo-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-sve-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-bf16-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-complxnum-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-fp16fml-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-fptoint-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-i8mm-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-neon-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-rcpc-immo-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-sve-instructions.s
M llvm/test/tools/llvm-mca/RISCV/Andes45/rvv-reduction.s
M llvm/tools/dsymutil/DebugMap.cpp
M llvm/tools/dsymutil/DebugMap.h
M llvm/tools/dsymutil/MachODebugMapParser.cpp
M llvm/tools/dsymutil/Options.td
M llvm/tools/dsymutil/dsymutil.cpp
M llvm/tools/dsymutil/dsymutil.h
M llvm/tools/llvm-dwarfdump/Coverage.cpp
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/tools/llvm-split/llvm-split.cpp
M llvm/unittests/Analysis/DomTreeUpdaterTest.cpp
M llvm/unittests/Analysis/LoadsTest.cpp
M llvm/unittests/Analysis/ValueTrackingTest.cpp
M llvm/unittests/ExecutionEngine/Orc/LibraryResolverTest.cpp
M llvm/unittests/Support/Path.cpp
M llvm/unittests/Support/raw_socket_stream_test.cpp
M llvm/unittests/TargetParser/TripleTest.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.h
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/performance/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Analysis/Scalable/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/Analysis/Scalable/BUILD.gn
M llvm/utils/gn/secondary/clang/unittests/DependencyScanning/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/NVPTX/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/X86/AsmParser/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
M llvm/utils/lit/lit/LitConfig.py
M llvm/utils/lit/lit/TestRunner.py
M llvm/utils/lit/lit/display.py
M llvm/utils/lit/lit/llvm/config.py
M llvm/utils/lit/tests/lit.cfg
M llvm/utils/lit/tests/shtest-readfile.py
M llvm/utils/llvm-lit/llvm-lit.in
M mlir/CMakeLists.txt
M mlir/include/mlir-c/Dialect/Transform.h
M mlir/include/mlir-c/Rewrite.h
M mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/include/mlir/Dialect/Func/IR/FuncOps.td
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h
M mlir/include/mlir/Dialect/MPI/IR/MPIOps.td
M mlir/include/mlir/Dialect/Math/IR/MathOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCCGOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtilsLoop.h
M mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
M mlir/include/mlir/Dialect/Shard/IR/ShardOps.td
M mlir/include/mlir/Dialect/Shard/Transforms/Partition.h
M mlir/include/mlir/Dialect/Shard/Transforms/Passes.td
R mlir/include/mlir/Dialect/Shard/Transforms/Simplifications.h
A mlir/include/mlir/Dialect/Shard/Transforms/Simplify.h
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/Dialect/Vector/TransformOps/VectorTransformOps.td
M mlir/include/mlir/Dialect/Vector/Transforms/LoweringPatterns.h
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td
M mlir/include/mlir/Dialect/XeGPU/Transforms/Passes.td
M mlir/include/mlir/Dialect/XeGPU/Transforms/Transforms.h
M mlir/include/mlir/Dialect/XeGPU/uArch/IntelGpuXe2.h
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/include/mlir/IR/Operation.h
M mlir/include/mlir/IR/OperationSupport.h
M mlir/include/mlir/IR/Region.h
M mlir/lib/Bindings/Python/DialectTransform.cpp
M mlir/lib/Bindings/Python/Rewrite.cpp
M mlir/lib/Bindings/Python/Rewrite.h
M mlir/lib/CAPI/Dialect/Transform.cpp
M mlir/lib/CAPI/Transforms/Rewrite.cpp
M mlir/lib/Conversion/ArithToEmitC/ArithToEmitCPass.cpp
M mlir/lib/Conversion/FuncToEmitC/FuncToEmitCPass.cpp
M mlir/lib/Conversion/MPIToLLVM/CMakeLists.txt
M mlir/lib/Conversion/MPIToLLVM/MPIToLLVM.cpp
M mlir/lib/Conversion/SCFToEmitC/SCFToEmitC.cpp
M mlir/lib/Conversion/ShardToMPI/ShardToMPI.cpp
M mlir/lib/Conversion/VectorToXeGPU/VectorToXeGPU.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/FoldMemRefsOps.cpp
M mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp
M mlir/lib/Dialect/Func/IR/FuncOps.cpp
M mlir/lib/Dialect/GPU/Pipelines/GPUToXeVMPipeline.cpp
M mlir/lib/Dialect/IRDL/IR/IRDL.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
M mlir/lib/Dialect/LLVMIR/Transforms/InlinerInterfaceImpl.cpp
M mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/TilingInterfaceImpl.cpp
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/MPI/IR/MPIOps.cpp
M mlir/lib/Dialect/Math/IR/MathOps.cpp
M mlir/lib/Dialect/NVGPU/Transforms/OptimizeSharedMemory.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACCCG.cpp
A mlir/lib/Dialect/OpenACC/Transforms/ACCRecipeMaterialization.cpp
M mlir/lib/Dialect/OpenACC/Transforms/CMakeLists.txt
M mlir/lib/Dialect/OpenACC/Transforms/LegalizeDataValues.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtils.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtilsLoop.cpp
M mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
M mlir/lib/Dialect/Shape/IR/Shape.cpp
M mlir/lib/Dialect/Shard/IR/ShardOps.cpp
M mlir/lib/Dialect/Shard/Transforms/CMakeLists.txt
R mlir/lib/Dialect/Shard/Transforms/Simplifications.cpp
A mlir/lib/Dialect/Shard/Transforms/Simplify.cpp
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseSpaceCollapse.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenUtils.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenUtils.h
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp
M mlir/lib/Dialect/Vector/Transforms/LowerVectorMultiReduction.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorDistribute.cpp
M mlir/lib/Dialect/Vector/Utils/VectorUtils.cpp
M mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/CMakeLists.txt
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUBlocking.cpp
R mlir/lib/Dialect/XeGPU/Transforms/XeGPUFoldAliasOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSgToWiDistributeExperimental.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUUnroll.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUWgToSgDistribute.cpp
M mlir/lib/IR/OperationSupport.cpp
M mlir/lib/IR/Verifier.cpp
M mlir/python/mlir/dialects/ext.py
M mlir/test/Conversion/ArithToEmitC/arith-to-emitc-failed.mlir
M mlir/test/Conversion/ConvertToSPIRV/func-signature-vector-unroll.mlir
A mlir/test/Conversion/FuncToEmitC/func-to-emitc-failed.mlir
M mlir/test/Conversion/FuncToLLVM/func-memref-return.mlir
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm-32b.mlir
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
M mlir/test/Conversion/MPIToLLVM/mpitollvm.mlir
M mlir/test/Conversion/SCFToEmitC/scf-to-emitc-failed.mlir
M mlir/test/Conversion/ShardToMPI/convert-shard-to-mpi.mlir
M mlir/test/Conversion/VectorToXeGPU/store-to-xegpu.mlir
M mlir/test/Dialect/AMDGPU/amdgpu-fold-memrefs.mlir
M mlir/test/Dialect/Affine/SuperVectorize/vector_utils.mlir
M mlir/test/Dialect/Affine/SuperVectorize/vectorize_unsupported.mlir
M mlir/test/Dialect/Arith/canonicalize.mlir
M mlir/test/Dialect/Arith/invalid.mlir
M mlir/test/Dialect/ControlFlow/canonicalize.mlir
M mlir/test/Dialect/EmitC/invalid_types.mlir
M mlir/test/Dialect/Func/invalid.mlir
M mlir/test/Dialect/IRDL/invalid_names.irdl.mlir
M mlir/test/Dialect/LLVM/transform-e2e.mlir
M mlir/test/Dialect/LLVMIR/inlining.mlir
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/nvvm.mlir
M mlir/test/Dialect/LLVMIR/sroa.mlir
M mlir/test/Dialect/Linalg/data-layout-propagation.mlir
M mlir/test/Dialect/Linalg/invalid.mlir
A mlir/test/Dialect/Linalg/td/propagate-data-layout.mlir
M mlir/test/Dialect/Linalg/transform-lower-pack.mlir
M mlir/test/Dialect/Linalg/transform-tile-and-fuse-pack-unpack.mlir
M mlir/test/Dialect/MPI/mpiops.mlir
M mlir/test/Dialect/Math/canonicalize.mlir
M mlir/test/Dialect/NVGPU/invalid.mlir
M mlir/test/Dialect/NVGPU/optimize-shared-memory.mlir
A mlir/test/Dialect/OpenACC/acc-recipe-materialization-firstprivate.mlir
A mlir/test/Dialect/OpenACC/acc-recipe-materialization-kernel-private.mlir
A mlir/test/Dialect/OpenACC/acc-recipe-materialization-parallel.mlir
A mlir/test/Dialect/OpenACC/acc-recipe-materialization-private.mlir
A mlir/test/Dialect/OpenACC/acc-recipe-materialization-reduction.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
M mlir/test/Dialect/Shape/invalid.mlir
M mlir/test/Dialect/Shard/all-scatter-op-lowering.mlir
M mlir/test/Dialect/Shard/canonicalization.mlir
M mlir/test/Dialect/Shard/folding.mlir
M mlir/test/Dialect/Shard/invalid.mlir
M mlir/test/Dialect/Shard/ops.mlir
R mlir/test/Dialect/Shard/simplifications.mlir
A mlir/test/Dialect/Shard/simplify.mlir
A mlir/test/Dialect/SparseTensor/conversion_invalid.mlir
M mlir/test/Dialect/SparseTensor/invalid.mlir
M mlir/test/Dialect/SparseTensor/invalid_encoding.mlir
A mlir/test/Dialect/SparseTensor/sparse_foreach_rank0.mlir
M mlir/test/Dialect/SparseTensor/sparse_space_collapse.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/invalid.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
A mlir/test/Dialect/Vector/canonicalize/vector-to-elements.mlir
M mlir/test/Dialect/Vector/invalid.mlir
M mlir/test/Dialect/Vector/transform-vector.mlir
R mlir/test/Dialect/Vector/vector-multi-reduction-reorder-and-expand.mlir
A mlir/test/Dialect/Vector/vector-multi-reduction-reorder.mlir
M mlir/test/Dialect/Vector/vector-multi-reduction-unrolling.mlir
M mlir/test/Dialect/Vector/vector-warp-distribute.mlir
M mlir/test/Dialect/XeGPU/resolve-layout-conflicts.mlir
M mlir/test/Dialect/XeGPU/subgroup-distribute-unit.mlir
M mlir/test/Dialect/XeGPU/subgroup-distribute.mlir
M mlir/test/Dialect/XeGPU/xegpu-blocking.mlir
R mlir/test/Dialect/XeGPU/xegpu-fold-alias-ops.mlir
A mlir/test/Dialect/XeGPU/xegpu-propagate-layout-invalid.mlir
A mlir/test/Dialect/XeGPU/xegpu-subgroup-distribute-no-arch.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops-rr.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg-unify-ops.mlir
M mlir/test/Dialect/XeGPU/xegpu-wg-to-sg.mlir
M mlir/test/IR/operation-equality.mlir
M mlir/test/IR/test-region-branch-op-verifier.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/reduce_1d.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/ArmSVE/reduce_2d.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/pack-unpack-mmt4d.mlir
M mlir/test/Integration/Dialect/Linalg/CPU/test-matmul-masked-vec.mlir
M mlir/test/Interfaces/LoopLikeInterface/test-block-loop.mlir
M mlir/test/Interfaces/TilingInterface/lower-to-loops-using-interface.mlir
M mlir/test/Transforms/print-op-graph.mlir
M mlir/test/Transforms/test-dialect-conversion-pdll.mlir
M mlir/test/Transforms/test-legalizer.mlir
M mlir/test/Transforms/test-merge-blocks.mlir
M mlir/test/Transforms/test-pattern-selective-replacement.mlir
M mlir/test/lib/Dialect/Affine/TestVectorizationUtils.cpp
M mlir/test/lib/Dialect/Linalg/CMakeLists.txt
R mlir/test/lib/Dialect/Linalg/TestDataLayoutPropagation.cpp
M mlir/test/lib/Dialect/Shard/CMakeLists.txt
M mlir/test/lib/Dialect/Shard/TestReshardingPartition.cpp
R mlir/test/lib/Dialect/Shard/TestSimplifications.cpp
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestOps.td
M mlir/test/lib/IR/TestOperationEquals.cpp
M mlir/test/lib/Interfaces/LoopLikeInterface/TestBlockInLoop.cpp
A mlir/test/python/dialects/transform_pattern_descriptor_op_interface.py
M mlir/test/python/dialects/transform_vector_ext.py
M mlir/tools/mlir-opt/mlir-opt.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsLoopTest.cpp
M mlir/unittests/IR/CMakeLists.txt
A mlir/unittests/IR/VerifierTest.cpp
M offload/include/OpenMP/Mapping.h
M offload/libomptarget/OpenMP/Mapping.cpp
M offload/libomptarget/interface.cpp
M offload/libomptarget/omptarget.cpp
M offload/test/api/omp_indirect_call_table_manual.c
A offload/test/api/omp_indirect_func_array.c
A offload/test/api/omp_indirect_func_basic.c
A offload/test/api/omp_indirect_func_struct.c
A offload/test/api/omp_virtual_func.cpp
A offload/test/api/omp_virtual_func_multiple_inheritance_01.cpp
A offload/test/api/omp_virtual_func_multiple_inheritance_02.cpp
A offload/test/api/omp_virtual_func_reference.cpp
A offload/test/mapping/map_ordering_ptee_tgt_alloc_mapper_alloc_from_to.c
A offload/test/mapping/map_ordering_ptee_tgt_data_alloc_tgt_mapper_present_delete_from_to.c
A offload/test/mapping/map_ordering_tgt_alloc_from_to.c
A offload/test/mapping/map_ordering_tgt_alloc_present_tofrom.c
A offload/test/mapping/map_ordering_tgt_alloc_tofrom.c
A offload/test/mapping/map_ordering_tgt_data_alloc_from.c
A offload/test/mapping/map_ordering_tgt_data_alloc_to_from.c
A offload/test/mapping/map_ordering_tgt_data_alloc_tofrom.c
A offload/test/mapping/map_ordering_tgt_exit_data_always_always.c
A offload/test/mapping/map_ordering_tgt_exit_data_delete_from.c
A offload/test/mapping/map_ordering_tgt_exit_data_delete_from_assumedsize.c
A offload/test/mapping/map_ordering_tgt_exit_data_from_delete_assumedsize.c
A offload/test/mapping/map_ordering_tgt_exit_data_from_mapper_overlap.c
M third-party/benchmark/include/benchmark/benchmark.h
M utils/bazel/.bazelrc
M utils/bazel/llvm-project-overlay/bolt/BUILD.bazel
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
M utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/third-party/BUILD.bazel
M utils/bazel/third_party_build/zlib-ng.BUILD
Log Message:
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comment
Created using spr 1.3.7
Compare: https://github.com/llvm/llvm-project/compare/d39613a6dd05...6653187e22d1
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