[all-commits] [llvm/llvm-project] 34f1b8: [AArch64] Fold zero-high vector inserts in MI peep...

[Amina Chabane via All-commits]

  Branch: refs/heads/users/Amichaxx/vcombine_peephole
  Home:   https://github.com/llvm/llvm-project
  Commit: 34f1b86b51fa7e3c5f926ea9de4bc77ecb2c5619
      https://github.com/llvm/llvm-project/commit/34f1b86b51fa7e3c5f926ea9de4bc77ecb2c5619
  Author: Amichaxx <amina.chabane at arm.com>
  Date:   2026-03-04 (Wed, 04 Mar 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
    M llvm/test/CodeGen/AArch64/aarch64-addv.ll
    M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
    M llvm/test/CodeGen/AArch64/bitcast-extend.ll
    M llvm/test/CodeGen/AArch64/ctpop.ll
    M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
    M llvm/test/CodeGen/AArch64/neon-lowhalf128-optimisation.ll
    M llvm/test/CodeGen/AArch64/peephole-insvigpr.mir

  Log Message:
  -----------
  [AArch64] Fold zero-high vector inserts in MI peephole optimisation

Summary
This patch follows on from #178227.
The previous ISel fold lowers the 64-bit case to:
    fmov d0, x0
    fmov d0, d0
which is not ideal and could be fmov d0, x0.
A redundant copy comes from the INSERT_SUBREG/INSvi64lane.

This peephole detects <2 x i64> vectors made of a zeroed upper and low
lane produced by FMOVXDr/FMOVDr, then removes the redundant copy.

Further updated tests and added MIR tests.


  Commit: 2383919f428e77e4709424394ecc1c3afa99dbf2
      https://github.com/llvm/llvm-project/commit/2383919f428e77e4709424394ecc1c3afa99dbf2
  Author: Amichaxx <amina.chabane at arm.com>
  Date:   2026-03-04 (Wed, 04 Mar 2026)

  Changed paths:
    A llvm/test/CodeGen/AArch64/aarch64-neonvector-tensorflow-regression.ll

  Log Message:
  -----------
  Compile time regression test


  Commit: fb664ad79661fbae75e3029a0c5886e5e6d2a1f5
      https://github.com/llvm/llvm-project/commit/fb664ad79661fbae75e3029a0c5886e5e6d2a1f5
  Author: Amichaxx <amina.chabane at arm.com>
  Date:   2026-03-04 (Wed, 04 Mar 2026)

  Changed paths:
    M llvm/test/CodeGen/AArch64/aarch64-addv.ll
    R llvm/test/CodeGen/AArch64/aarch64-neonvector-tensorflow-regression.ll
    M llvm/test/CodeGen/AArch64/bitcast-extend.ll

  Log Message:
  -----------
  Update tests, remove regression test


Compare: https://github.com/llvm/llvm-project/compare/060ed4c0d655...fb664ad79661

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