[all-commits] [llvm/llvm-project] d0f50d: [AMDGPU] Remove DX10_CLAMP and IEEE bits from gfx1...
Mariusz Sikora via All-commits
all-commits at lists.llvm.org
Wed Mar 4 05:42:08 PST 2026
Branch: refs/heads/users/mariusz-sikora-at-amd/add-flat-offset-bits-feature
Home: https://github.com/llvm/llvm-project
Commit: d0f50d55746aa27e6467cb2bce66596da9da065b
https://github.com/llvm/llvm-project/commit/d0f50d55746aa27e6467cb2bce66596da9da065b
Author: Mirko Brkušanin <Mirko.Brkusanin at amd.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/test/CodeGenOpenCL/amdgpu-ieee.cl
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCKernelDescriptor.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.cpp
M llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.cpp
M llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-default.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll
A llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp-on.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll
M llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll
M llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
M llvm/test/MC/AMDGPU/hsa-diag-v4.s
M llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-dx10-clamp.ll
M llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-ieee.ll
Log Message:
-----------
[AMDGPU] Remove DX10_CLAMP and IEEE bits from gfx1170 (#182107)
Add `DX10ClampAndIEEEMode` feature and set it for every subtarget prior
to gfx1170
Commit: 943eb6fd958e8b130ee94f5c65b7d53ec3419acc
https://github.com/llvm/llvm-project/commit/943eb6fd958e8b130ee94f5c65b7d53ec3419acc
Author: Graham Hunter <graham.hunter at arm.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/test/Transforms/LoopVectorize/find-last.ll
Log Message:
-----------
[LV] Use make_early_inc_range in handleFindLastReductions (#184340)
Fixes #182152
Commit: ee92ac2343f6e0ff787bbe660c9a9293caa5269c
https://github.com/llvm/llvm-project/commit/ee92ac2343f6e0ff787bbe660c9a9293caa5269c
Author: Jueon Park <79134656+JueonPark at users.noreply.github.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M mlir/lib/Dialect/NVGPU/Transforms/OptimizeSharedMemory.cpp
M mlir/test/Dialect/NVGPU/optimize-shared-memory.mlir
Log Message:
-----------
[mlir][nvgpu] Fix crash in optimize-shared-memory pass with vector element types (#179111)
The `--nvgpu-optimize-shared-memory` pass crashed when processing
memrefs with vector element types (e.g., `memref<16x1xvector<16xf16>,
3>`). This occurred because getElementTypeBitWidth() calls
getIntOrFloatBitWidth(), which asserts the element type must be an
integer or float.
Thus, this PR adds an early-exit guard to return failure() when the
memref's element type is not a scalar int or float.
I wasn't sure if we should support vector types (by multiplying element
bit width by vector length) or just reject them. For now, I've
implemented it to return failure on non-scalar types.
Fixes #177823
Co-authored-by: rebel-jueonpark <jueonpark at rebellions.ai>
Commit: 7f044944e43eab4f5f52664a9022b1cc083ab258
https://github.com/llvm/llvm-project/commit/7f044944e43eab4f5f52664a9022b1cc083ab258
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/test/Dialect/Arith/canonicalize.mlir
M mlir/test/Dialect/Arith/invalid.mlir
M mlir/test/Dialect/Vector/invalid.mlir
Log Message:
-----------
[MLIR][Arith][Vector] Reject i0 integer type in arith and vector ops (#183589)
Add ODS type constraints that exclude zero-bitwidth integers (i0) from
operations in the arith and vector dialects. i0 has no meaningful
arithmetic representation and operations on it can trigger undefined
behavior (e.g. bitwidth calculations assuming non-zero width).
Changes:
- Add `AnyNonZeroBitwidthSignlessInteger` (as a `ConfinedType` over
`AnySignlessInteger`) and `AnyNonZeroBitwidthSignlessIntegerOrIndex`
to CommonTypeConstraints.td.
- Introduce `Arith_SignlessIntegerOrIndexLike` in ArithOps.td that wraps
`AnyNonZeroBitwidthSignlessIntegerOrIndex` via
`TypeOrValueSemanticsContainer`, and update
`SignlessFixedWidthIntegerLike`
to use `AnyNonZeroBitwidthSignlessInteger`. Replace all uses of the
shared `SignlessIntegerOrIndexLike` in ArithOps.td with the new
dialect-local constraint.
- Update `IndexCastTypeConstraint` to use
`Arith_SignlessIntegerOrIndexLike`.
- Update `BitcastTypeConstraint` to exclude i0 by composing the already-
defined `SignlessFixedWidthIntegerLike` and `FloatLike` constraints,
keeping the definition compact (3 alternatives instead of 7).
- Add `AnyVectorOfNonI0Elem` and `AnyVectorOfNonZeroRankNonI0Elem` in
VectorOps.td and apply them to `vector.contract`, `vector.reduction`,
`vector.multi_reduction`, `vector.outerproduct`, `vector.bitcast`, and
`vector.scan`.
- Update arith/invalid.mlir with explicit i0 rejection tests covering
all
integer op families (binary ops, cast ops, extended-multiply ops, cmpi,
bitcast, index_cast, index_castui) for both scalar and vector<N> forms.
- Update vector/invalid.mlir with i0 rejection tests for all covered
ops.
- Remove the now-invalid i0 canonicalization tests from
arith/canonicalize.mlir.
Fixes #177822
Fixes #179266
Fixes #180463
Fixes #181532
See also
https://discourse.llvm.org/t/rfc-reject-i0-integer-type-in-arith-and-vector-ops/90011
Commit: 9c2829f2e1883a8634edf4008f1cbc5928c63eeb
https://github.com/llvm/llvm-project/commit/9c2829f2e1883a8634edf4008f1cbc5928c63eeb
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M mlir/lib/Dialect/Func/IR/FuncOps.cpp
M mlir/test/Dialect/Func/invalid.mlir
M mlir/test/IR/test-region-branch-op-verifier.mlir
Log Message:
-----------
[mlir][Func] Use getMutableSuccessorOperands() in FuncOp verifier (#184589)
When verifying return-like terminators, use
getMutableSuccessorOperands() instead of getNumOperands() so that only
the operands passed to the parent region are checked against the
function result types. This handles terminators that implement
RegionBranchTerminatorOpInterface and carry additional operands for
other successor regions (e.g. loop back-edges).
Add tests using test.loop_block_term, which has both an iter operand
(passed back to the region) and an exit operand (passed to the parent).
Commit: ee8184573f03fde4aa642d2f90254096477d9805
https://github.com/llvm/llvm-project/commit/ee8184573f03fde4aa642d2f90254096477d9805
Author: jeanPerier <jperier at nvidia.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M flang/lib/Lower/PFTBuilder.cpp
M flang/test/Lower/OpenMP/target.f90
M flang/test/Lower/do-while-to-scf-while.f90
M flang/test/Lower/loops.f90
M flang/test/Lower/mixed_loops.f90
M flang/test/Lower/pre-fir-tree02.f90
M flang/test/Lower/while_loop.f90
Log Message:
-----------
Revert "[flang] make lowering to scf.while default" (#184592)
Reverts llvm/llvm-project#184234
This is breaking SPEC and other tests.
Reproducer:
```
subroutine foo()
logical :: l1, l2
do while (l1())
if (l2()) then
call bar()
endif
enddo
end
```
The cause is a pass ordering issue between the SCFToControlFlowPass and
CfgConversionPass
[here](https://github.com/llvm/llvm-project/blob/d0f50d55746aa27e6467cb2bce66596da9da065b/flang/lib/Optimizer/Passes/Pipelines.cpp#L239-L240).
I think they need to be run simultaneously somehow because the both SCF
and FIR structured operations may contain each other, and none will be
happy to get block CFG generated inside their region by the pass
lowering the other.
Reverting while this is sorted out.
Commit: 0a1e39517b229592c9a36eb366b0f70b73f1b4f3
https://github.com/llvm/llvm-project/commit/0a1e39517b229592c9a36eb366b0f70b73f1b4f3
Author: Ella Ma <alansnape3058 at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/test/Analysis/missing-z3-nocrash.c
M clang/test/lit.cfg.py
Log Message:
-----------
[nfc][analyzer][test][z3] Replace "REQUIRES: no-z3" with "UNSUPPORTED: z3" (#184349)
Fixing D120325, continuing #183724
Lit feature "no-z3" is the opposite of "z3", requiring "no-z3" is the
same as unsupporting "z3".
Commit: 1f4074b771bea3e29c9efbbd3d22689e62773af1
https://github.com/llvm/llvm-project/commit/1f4074b771bea3e29c9efbbd3d22689e62773af1
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
M mlir/test/Dialect/LLVMIR/sroa.mlir
Log Message:
-----------
[mlir][llvm] Fix SROA crash on empty LLVM struct types (#184596)
When SROA runs on an alloca of an empty struct type (llvm.struct<()>),
it crashes with:
Assertion `\!subelementIndexMap->empty()' failed.
The root cause is in LLVMStructType::getSubelementIndexMap(): for an
empty struct (no body fields), the loop doesn't execute and an empty
DenseMap is returned as a non-null optional. Later, getTypeAtIndex()
asserts the map is non-empty, triggering the crash.
Fix this by returning std::nullopt for empty structs, indicating they
cannot be destructured. This is consistent with how LLVMArrayType
handles the zero-element case.
Fixes #108366
Commit: c2784e11cc4405cbc64d1928cbcabbbd0759777b
https://github.com/llvm/llvm-project/commit/c2784e11cc4405cbc64d1928cbcabbbd0759777b
Author: Phoebe Linck <phoebelinck at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Semantics/OpenMP/resolve05.f90
Log Message:
-----------
[Flang][OpenMP] DEFAULT(NONE) error checking on implicit references (#182214)
A variable with an unspecified data-sharing attribute under a
DEFAULT(NONE) clause only emits an error if the variable is explicitly
referenced in the body of the construct with DEFAULT(NONE).
Ex:
```
!$omp parallel default(none)
!$omp task
a = 1
!$omp end task
!$omp end parallel
end
```
gfortran will error with `‘a’ not specified in enclosing ‘parallel’` on
the above. flang doesn't error.
Fix moves the error check to `CreateImplicitSymbols` and checks the
variable for a violation in any of its enclosing contexts.
Commit: 095e1694d9c095ab6b1f515811ea968e6f8f712d
https://github.com/llvm/llvm-project/commit/095e1694d9c095ab6b1f515811ea968e6f8f712d
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/Randstruct.cpp
M clang/lib/Basic/FileManager.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/Driver/CreateASTUnitFromArgs.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/OffloadBundler.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Lex/LiteralSupport.cpp
M clang/lib/Lex/PPExpressions.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/StaticAnalyzer/Checkers/IvarInvalidationChecker.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineCXX.cpp
M clang/lib/Tooling/DependencyScanningTool.cpp
Log Message:
-----------
[clang] Turn misc copy-assign to move-assign (#184144)
That's an automated patch generated from clang-tidy
performance-use-std-move as a follow-up to #184136
Commit: 8bb41c929f3ab6687a8681c5376f9078e4646878
https://github.com/llvm/llvm-project/commit/8bb41c929f3ab6687a8681c5376f9078e4646878
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
Log Message:
-----------
AMDGPU: Fix copy of Triple (#184594)
Commit: 98ed41718b0f2dfafdb2e54ad7c34f14ebcfdbc3
https://github.com/llvm/llvm-project/commit/98ed41718b0f2dfafdb2e54ad7c34f14ebcfdbc3
Author: Graham Hunter <graham.hunter at arm.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/AArch64/early_exit_with_stores.ll
A llvm/test/Transforms/LoopVectorize/RISCV/early_exit_with_stores.ll
A llvm/test/Transforms/LoopVectorize/VPlan/early_exit_with_stores_vplan.ll
M llvm/test/Transforms/LoopVectorize/early_exit_store_legality.ll
A llvm/test/Transforms/LoopVectorize/early_exit_with_stores.ll
Log Message:
-----------
[LV] Transform tests for early-exit with stores (#183288)
Precommit of transform tests for #178454
Commit: 5cf09a68a63dde0158973682717b1a5f2c0d552c
https://github.com/llvm/llvm-project/commit/5cf09a68a63dde0158973682717b1a5f2c0d552c
Author: Matthew Devereau <matthew.devereau at arm.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/clmul-fixed.ll
M llvm/test/CodeGen/AArch64/clmul.ll
Log Message:
-----------
[AArch64][ISel] Use vector register for scalar CLMUL (#183282)
Even though there are only v8i8 and v1i64 variants for pmul/pmull, Using
them is faster than the current implementation for scalar CLMUL.
Commit: 0af2d43e06415ce1e8a5d49e864c3881048dd08b
https://github.com/llvm/llvm-project/commit/0af2d43e06415ce1e8a5d49e864c3881048dd08b
Author: Tomohiro Kashiwada <kikairoya at gmail.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaDeclAttr.cpp
A clang/test/SemaCXX/attr-exclude_from_explicit_instantiation.ignore-dllattr.cpp
Log Message:
-----------
[Clang] Warn if both of `dllexport`/`dllimport` and `exclude_from_explicit_instantiation` are specified (#183515)
The attributes `exclude_from_explicit_instantiation` and
`dllexport`/`dllimport` serve opposite purposes.
Therefore, if an entity has both attributes, drop one with a warning,
depending on the context of the declaration.
In a template context, the `exclude_from_explicit_instantiation`
attribute takes precedence over the `dllexport` or `dllimport`
attribute. Conversely, the `dllexport` and `dllimport` attributes are
prioritized, in a non-template context.
Commit: 6b64a9f7e923253b46bdf86063421f796f60c54d
https://github.com/llvm/llvm-project/commit/6b64a9f7e923253b46bdf86063421f796f60c54d
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2026-03-04 (Wed, 04 Mar 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/Randstruct.cpp
M clang/lib/Basic/FileManager.cpp
M clang/lib/CodeGen/CodeGenFunction.cpp
M clang/lib/Driver/CreateASTUnitFromArgs.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/OffloadBundler.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Lex/LiteralSupport.cpp
M clang/lib/Lex/PPExpressions.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaLookup.cpp
M clang/lib/StaticAnalyzer/Checkers/IvarInvalidationChecker.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngineCXX.cpp
M clang/lib/Tooling/DependencyScanningTool.cpp
M clang/test/Analysis/missing-z3-nocrash.c
M clang/test/CodeGenOpenCL/amdgpu-ieee.cl
A clang/test/SemaCXX/attr-exclude_from_explicit_instantiation.ignore-dllattr.cpp
M clang/test/lit.cfg.py
M flang/lib/Lower/PFTBuilder.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Lower/OpenMP/target.f90
M flang/test/Lower/do-while-to-scf-while.f90
M flang/test/Lower/loops.f90
M flang/test/Lower/mixed_loops.f90
M flang/test/Lower/pre-fir-tree02.f90
M flang/test/Lower/while_loop.f90
M flang/test/Semantics/OpenMP/resolve05.f90
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCKernelDescriptor.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.cpp
M llvm/lib/Target/AMDGPU/SIProgramInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/test/CodeGen/AArch64/clmul-fixed.ll
M llvm/test/CodeGen/AArch64/clmul.ll
M llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-default.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll
A llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp-on.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp.ll
M llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll
M llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll
M llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
M llvm/test/MC/AMDGPU/hsa-diag-v4.s
M llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-dx10-clamp.ll
M llvm/test/Transforms/Inline/AMDGPU/inline-amdgpu-ieee.ll
A llvm/test/Transforms/LoopVectorize/AArch64/early_exit_with_stores.ll
A llvm/test/Transforms/LoopVectorize/RISCV/early_exit_with_stores.ll
A llvm/test/Transforms/LoopVectorize/VPlan/early_exit_with_stores_vplan.ll
M llvm/test/Transforms/LoopVectorize/early_exit_store_legality.ll
A llvm/test/Transforms/LoopVectorize/early_exit_with_stores.ll
M llvm/test/Transforms/LoopVectorize/find-last.ll
M mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/IR/CommonTypeConstraints.td
M mlir/lib/Dialect/Func/IR/FuncOps.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
M mlir/lib/Dialect/NVGPU/Transforms/OptimizeSharedMemory.cpp
M mlir/test/Dialect/Arith/canonicalize.mlir
M mlir/test/Dialect/Arith/invalid.mlir
M mlir/test/Dialect/Func/invalid.mlir
M mlir/test/Dialect/LLVMIR/sroa.mlir
M mlir/test/Dialect/NVGPU/optimize-shared-memory.mlir
M mlir/test/Dialect/Vector/invalid.mlir
M mlir/test/IR/test-region-branch-op-verifier.mlir
Log Message:
-----------
Merge remote-tracking branch 'external-upstream/main' into users/mariusz-sikora-at-amd/add-flat-offset-bits-feature
Compare: https://github.com/llvm/llvm-project/compare/dac78e98f526...6b64a9f7e923
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