[all-commits] [llvm/llvm-project] 5cf09a: [AArch64][ISel] Use vector register for scalar CLM...

[Matthew Devereau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5cf09a68a63dde0158973682717b1a5f2c0d552c
      https://github.com/llvm/llvm-project/commit/5cf09a68a63dde0158973682717b1a5f2c0d552c
  Author: Matthew Devereau <matthew.devereau at arm.com>
  Date:   2026-03-04 (Wed, 04 Mar 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/clmul-fixed.ll
    M llvm/test/CodeGen/AArch64/clmul.ll

  Log Message:
  -----------
  [AArch64][ISel] Use vector register for scalar CLMUL (#183282)

Even though there are only v8i8 and v1i64 variants for pmul/pmull, Using
them is faster than the current implementation for scalar CLMUL.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications