[all-commits] [llvm/llvm-project] 7f0449: [MLIR][Arith][Vector] Reject i0 integer type in ar...

Mehdi Amini via All-commits all-commits at lists.llvm.org
Wed Mar 4 03:34:40 PST 2026


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7f044944e43eab4f5f52664a9022b1cc083ab258
      https://github.com/llvm/llvm-project/commit/7f044944e43eab4f5f52664a9022b1cc083ab258
  Author: Mehdi Amini <joker.eph at gmail.com>
  Date:   2026-03-04 (Wed, 04 Mar 2026)

  Changed paths:
    M mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
    M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
    M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
    M mlir/include/mlir/IR/CommonTypeConstraints.td
    M mlir/test/Dialect/Arith/canonicalize.mlir
    M mlir/test/Dialect/Arith/invalid.mlir
    M mlir/test/Dialect/Vector/invalid.mlir

  Log Message:
  -----------
  [MLIR][Arith][Vector] Reject i0 integer type in arith and vector ops (#183589)

Add ODS type constraints that exclude zero-bitwidth integers (i0) from
operations in the arith and vector dialects.  i0 has no meaningful
arithmetic representation and operations on it can trigger undefined
behavior (e.g. bitwidth calculations assuming non-zero width).

Changes:
- Add `AnyNonZeroBitwidthSignlessInteger` (as a `ConfinedType` over
  `AnySignlessInteger`) and `AnyNonZeroBitwidthSignlessIntegerOrIndex`
  to CommonTypeConstraints.td.
- Introduce `Arith_SignlessIntegerOrIndexLike` in ArithOps.td that wraps
  `AnyNonZeroBitwidthSignlessIntegerOrIndex` via
`TypeOrValueSemanticsContainer`, and update
`SignlessFixedWidthIntegerLike`
  to use `AnyNonZeroBitwidthSignlessInteger`.  Replace all uses of the
  shared `SignlessIntegerOrIndexLike` in ArithOps.td with the new
  dialect-local constraint.
- Update `IndexCastTypeConstraint` to use
`Arith_SignlessIntegerOrIndexLike`.
- Update `BitcastTypeConstraint` to exclude i0 by composing the already-
  defined `SignlessFixedWidthIntegerLike` and `FloatLike` constraints,
  keeping the definition compact (3 alternatives instead of 7).
- Add `AnyVectorOfNonI0Elem` and `AnyVectorOfNonZeroRankNonI0Elem` in
  VectorOps.td and apply them to `vector.contract`, `vector.reduction`,
  `vector.multi_reduction`, `vector.outerproduct`, `vector.bitcast`, and
  `vector.scan`.
- Update arith/invalid.mlir with explicit i0 rejection tests covering
all
integer op families (binary ops, cast ops, extended-multiply ops, cmpi,
bitcast, index_cast, index_castui) for both scalar and vector<N> forms.
- Update vector/invalid.mlir with i0 rejection tests for all covered
ops.
- Remove the now-invalid i0 canonicalization tests from
  arith/canonicalize.mlir.

Fixes #177822
Fixes #179266
Fixes #180463
Fixes #181532

See also
https://discourse.llvm.org/t/rfc-reject-i0-integer-type-in-arith-and-vector-ops/90011



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