[all-commits] [llvm/llvm-project] c62d5f: [AArch64] Avoid folding sign-extend of vector extr...

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c62d5f35b6785ff1fac0047c6e5d9e6dd8f745f8
      https://github.com/llvm/llvm-project/commit/c62d5f35b6785ff1fac0047c6e5d9e6dd8f745f8
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2026-03-04 (Wed, 04 Mar 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h
    M llvm/test/CodeGen/AArch64/combine-sdiv.ll
    A llvm/test/CodeGen/AArch64/extend_vecreduce_add.ll

  Log Message:
  -----------
  [AArch64] Avoid folding sign-extend of vector extracts into ALU ops (#183522)

This breaks a tie where the `SEXT_IN_REG` in an expression like 
`SUB(0, SEXT_IN_REG(VECTOR_EXTRACT(..))` can fold into the `SUB` or the
`VECTOR_EXTRACT`. Currently, the `SUB` is always preferred, but it's
better to fold the `SEXT_IN_REG` into the `VECTOR_EXTRACT` extract,
which allows for `SMOV` to be used.



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