[all-commits] [llvm/llvm-project] e71f32: [X86] support reserve r8~r15 on X86_64 (#180242)

[zhouguangyuan0718 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e71f327b46059fe232b205414a3e8c1fc537c80f
      https://github.com/llvm/llvm-project/commit/e71f327b46059fe232b205414a3e8c1fc537c80f
  Author: zhouguangyuan0718 <89333397+zhouguangyuan0718 at users.noreply.github.com>
  Date:   2026-03-03 (Tue, 03 Mar 2026)

  Changed paths:
    M clang/include/clang/Options/Options.td
    M clang/lib/Basic/Targets/X86.h
    M clang/lib/Driver/ToolChains/Arch/X86.cpp
    A clang/test/Driver/x86_64-fixed-r-register.c
    M llvm/lib/Target/X86/X86.td
    M llvm/lib/Target/X86/X86FrameLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86RegisterInfo.cpp
    M llvm/lib/Target/X86/X86Subtarget.cpp
    M llvm/lib/Target/X86/X86Subtarget.h
    A llvm/test/CodeGen/X86/reserveRreg.ll

  Log Message:
  -----------
  [X86] support reserve r8~r15 on X86_64 (#180242)

Which is under discussion in
https://github.com/llvm/llvm-project/issues/179036

Add new options -ffixed_r{8-15} for clang X86 target, like option
"-ffixed_x" for RISCV/AArch64 target.
Also, add target-feature +reserve-r{8-15} for the X86 backend.

The registers which are specified reserved will not be used in
RegAlloc/CalleeSave. Then the reserved registers can be maintained by
user. It will be useful for the runtime/interpreter implementation.

Other registers are used in specific instructions or mechanism, so they
can't be reserved.



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