[all-commits] [llvm/llvm-project] 703649: [DAG] isKnownNeverZero - add ISD::OR DemandedElts ...

[Shekhar via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 703649554da8f7b92873d21da7f3c51fbc7112ed
      https://github.com/llvm/llvm-project/commit/703649554da8f7b92873d21da7f3c51fbc7112ed
  Author: Shekhar <95859857+levi42x at users.noreply.github.com>
  Date:   2026-03-03 (Tue, 03 Mar 2026)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/X86/known-never-zero.ll

  Log Message:
  -----------
  [DAG] isKnownNeverZero - add ISD::OR DemandedElts handling (#183228)

This patch updates `SelectionDAG::isKnownNeverZero` to support `ISD::OR`
by forwarding the `DemandedElts` mask to its operands.

Previously, `ISD::OR` dropped the mask, causing the compiler to be
overly conservative if any lane in the vector was zero, even if that
lane wasn't demanded. This change allows the compiler to prove a vector
result is non-zero even if ignored lanes are zero.

Fixes #183037

**Tests:**

- Moved tests from the C++ file to the IR assembly file
(`known-never-zero.ll`) as requested.
- Confirmed the code now correctly tracks which parts of a vector are
actually needed for `ISD::OR`.
- This allows the compiler to prove a result is "never zero" even if
some unused lanes contain zeros.



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