[all-commits] [llvm/llvm-project] 4922ab: [RISCV] Relax codegen predicates for HINT-based in...

[Kito Cheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4922ab9915b0bc8cb6528583fe2da324d2d4bdeb
      https://github.com/llvm/llvm-project/commit/4922ab9915b0bc8cb6528583fe2da324d2d4bdeb
  Author: Kito Cheng <kito.cheng at sifive.com>
  Date:   2026-03-02 (Mon, 02 Mar 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.h
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/prefetch.ll
    M llvm/test/CodeGen/RISCV/riscv-zihintpause.ll

  Log Message:
  -----------
  [RISCV] Relax codegen predicates for HINT-based instructions (#179872)

Following the assembler/disassembler changes in #178609, this patch also
relaxes the codegen predicates for HINT-based instructions. Since these
instructions use encodings that are architecturally guaranteed not to
trap, the compiler can safely generate them regardless of extension
availability.

Changes:
- int_riscv_pause: Remove HasStdExtZihintpause predicate. The pause
intrinsic now generates the FENCE hint encoding unconditionally.
- NTL hints: Remove hasStdExtZihintntl() check in emitNTLHint().
Non-temporal locality hints are now emitted for all nontemporal memory
operations.



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