[all-commits] [llvm/llvm-project] df8b74: [AMDGPU] Multi dword spilling for unaligned tuples

[Aaditya via All-commits]

  Branch: refs/heads/users/easyonaadit/amdgpu/split-unaligned-spills-into-chunks
  Home:   https://github.com/llvm/llvm-project
  Commit: df8b74e1b1d7529542b2f24fbdfe57c86740db74
      https://github.com/llvm/llvm-project/commit/df8b74e1b1d7529542b2f24fbdfe57c86740db74
  Author: Aaditya <Aaditya.AlokDeshpande at amd.com>
  Date:   2026-02-27 (Fri, 27 Feb 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/test/CodeGen/AMDGPU/vgpr-spill.mir

  Log Message:
  -----------
  [AMDGPU] Multi dword spilling for unaligned tuples

While spilling unaligned tuples, rather than breaking the
spill into 32-bit accesses, spill the first register as a
single 32-bit spill, and spill the remainder of the tuple
as an aligned tuple.
Some additional bookkeeping is required in the spilling
loop to manage the state.



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