[all-commits] [llvm/llvm-project] 4dac68: [AArch64] Cortex-A55/A320/A510 scheduling model "t...

[walkerkd via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4dac6839a7e4f02de2fd124bf3b068f1dab5ad11
      https://github.com/llvm/llvm-project/commit/4dac6839a7e4f02de2fd124bf3b068f1dab5ad11
  Author: walkerkd <keith.walker at arm.com>
  Date:   2026-02-23 (Mon, 23 Feb 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SchedA320.td
    M llvm/lib/Target/AArch64/AArch64SchedA510.td
    M llvm/lib/Target/AArch64/AArch64SchedA55.td
    M llvm/test/CodeGen/AArch64/fp-to-int-to-fp.ll
    M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
    M llvm/test/CodeGen/AArch64/qmovn.ll
    M llvm/test/CodeGen/AArch64/sat-add.ll
    M llvm/test/CodeGen/AArch64/saturating-vec-smull.ll
    M llvm/test/tools/llvm-mca/AArch64/Cortex/A320-neon-instructions.s
    M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-neon-instructions.s
    M llvm/test/tools/llvm-mca/AArch64/Cortex/A55-neon-instructions.s

  Log Message:
  -----------
  [AArch64] Cortex-A55/A320/A510 scheduling model "typo" fixes (#182854)

While working to introduce the C1-Nano scheduling model some existing
"typos" were found in the definitions used in the Cortex-A55,
Cortex-A320 and Cortex-A510 scheduling models.

This corrects these typos and updated any tests affected by the changes.

There were 2 forms of typos found:

  "8b" which should have been "8h"
  "i132" which should have been "i32"



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