[all-commits] [llvm/llvm-project] 2b7c1f: [VPlan] Directly unroll VectorEndPointerRecipe (#1...

[Ramkumar Ramachandra via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2b7c1f9d82994fddac7b33a5be6c31b3e8059be2
      https://github.com/llvm/llvm-project/commit/2b7c1f9d82994fddac7b33a5be6c31b3e8059be2
  Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
  Date:   2026-02-16 (Mon, 16 Feb 2026)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/VPlan.h
    M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
    M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
    M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
    M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
    M llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-gather-scatter-tailpred.ll
    M llvm/test/Transforms/LoopVectorize/ARM/tail-folding-not-allowed.ll
    M llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/dbg-tail-folding-by-evl.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/predicated-reverse-store.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-reverse-load-store.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll
    M llvm/test/Transforms/LoopVectorize/WebAssembly/induction-branch-cost.ll
    M llvm/test/Transforms/LoopVectorize/X86/drop-inbounds-flags-for-reverse-vector-pointer.ll
    M llvm/test/Transforms/LoopVectorize/X86/end-pointer-signed.ll
    M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
    M llvm/test/Transforms/LoopVectorize/X86/multi-exit-cost.ll
    M llvm/test/Transforms/LoopVectorize/X86/pr81872.ll
    M llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
    M llvm/test/Transforms/LoopVectorize/if-reduction.ll
    M llvm/test/Transforms/LoopVectorize/induction-wrapflags.ll
    M llvm/test/Transforms/LoopVectorize/interleave-with-i65-induction.ll
    M llvm/test/Transforms/LoopVectorize/interleaved-accesses-gep-nowrap-flags.ll
    M llvm/test/Transforms/LoopVectorize/iv-select-cmp-decreasing.ll
    M llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
    M llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll
    M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
    M llvm/test/Transforms/LoopVectorize/pointer-induction.ll
    M llvm/test/Transforms/LoopVectorize/pr37248.ll
    M llvm/test/Transforms/LoopVectorize/reuse-lcssa-phi-scev-expansion.ll
    M llvm/test/Transforms/LoopVectorize/reverse-induction-gep-nowrap-flags.ll
    M llvm/test/Transforms/LoopVectorize/reverse_induction.ll
    M llvm/test/Transforms/LoopVectorize/runtime-check-known-true.ll
    M llvm/test/Transforms/LoopVectorize/runtime-check-needed-but-empty.ll
    M llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll
    M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave.ll
    M llvm/test/Transforms/LoopVectorize/single_early_exit_live_outs.ll
    M llvm/test/Transforms/LoopVectorize/skeleton-lcssa-crash.ll

  Log Message:
  -----------
  [VPlan] Directly unroll VectorEndPointerRecipe (#172372)

Directly unroll VectorEndPointerRecipe following 0636225b ([VPlan]
Directly unroll VectorPointerRecipe, #168886). It allows us to leverage
existing VPlan simplifications to optimize.

Co-authored-by: Luke Lau <luke at igalia.com>
Co-authored-by: Florian Hahn <flo at fhahn.com>



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