[all-commits] [llvm/llvm-project] 51df92: [SelectionDAG] Make sure demanded lanes for AND/MU...

[Björn Pettersson via All-commits]

  Branch: refs/heads/release/22.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 51df921b0d32daa98bccadef66778c60908c7f88
      https://github.com/llvm/llvm-project/commit/51df921b0d32daa98bccadef66778c60908c7f88
  Author: Björn Pettersson <bjorn.a.pettersson at ericsson.com>
  Date:   2026-02-16 (Mon, 16 Feb 2026)

  Changed paths:
    M llvm/include/llvm/CodeGen/SelectionDAG.h
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AArch64/neon-dotreduce.ll
    M llvm/test/CodeGen/X86/insertelement-zero.ll
    M llvm/test/CodeGen/X86/pr134602.ll
    M llvm/test/CodeGen/X86/pr173924.ll
    M llvm/test/CodeGen/X86/vector-fshl-256.ll
    M llvm/test/CodeGen/X86/vector-fshl-512.ll
    M llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
    M llvm/test/CodeGen/X86/vector-fshl-rot-512.ll
    M llvm/test/CodeGen/X86/vector-fshr-512.ll
    M llvm/test/CodeGen/X86/vector-fshr-rot-512.ll
    M llvm/test/CodeGen/X86/vector-rotate-256.ll
    M llvm/test/CodeGen/X86/vector-rotate-512.ll

  Log Message:
  -----------
  [SelectionDAG] Make sure demanded lanes for AND/MUL-by-zero are frozen (#180727)

DAGCombiner can fold a chain of INSERT_VECTOR_ELT into a vector AND/OR
operation. This patch adds protection to avoid that we end up making the
vector more poisonous by freezing the source vector when the elements
that should be set to 0/-1 may be poison in the source vector.

The patch also fixes a bug in SimplifyDemandedVectorElts for
MUL/MULHU/MULHS/AND that could result in making the vector more
poisonous. Problem was that we skipped demanding elements from Op0 that
were known to be zero in Op1. But that could result in elements being
simplified into poison when simplifying Op0, and then the result would
be poison and not zero after the MUL/MULHU/MULHS/AND. The solution is to
defensively make sure that we demand all the elements originally
demanded also when simplifying Op0.

This bugs were found when analysing the miscompiles in
https://github.com/llvm/llvm-project/issues/179448

Main culprit in #179448 seems to have been the bug in DAGCombiner. The
bug in SimplifyDemandedVectorElts surfaced when fixing the DAGCombiner,
as that fix typically introduce the (AND (FREEZE x), y) pattern that
wasn't handled correctly in SimplifyDemandedVectorElts.

Also fixes #180409.
Also fixes #176682.

(cherry picked from commit 6420099bcc62a09e002e500870216b2dd9d256a9)



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications