[all-commits] [llvm/llvm-project] 2380e1: [RISCV] Start zvlsseg-spill.mir test before regall...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2380e12fd61b687b82a1a67cb0161c9d6a77f4f6
      https://github.com/llvm/llvm-project/commit/2380e12fd61b687b82a1a67cb0161c9d6a77f4f6
  Author: Luke Lau <luke at igalia.com>
  Date:   2026-02-16 (Mon, 16 Feb 2026)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir

  Log Message:
  -----------
  [RISCV] Start zvlsseg-spill.mir test before regalloc. NFC

Currently this starts from the beginning of the codegen pipeline, but
because it has pseudos that directly define physical registers this
triggers an assertion in an upcoming change to RISCVVLOptimizer. In the
full pipeline a vector pseudo should only define virtual VR registers.

Move it to before regalloc to avoid the crash. It could probably be
moved further to just before prologepilog but we would need to change
the input to handle vsetvli insertion too.


  Commit: 820d15c8e68fc6405c5ceb9e96b387013bf1f5e7
      https://github.com/llvm/llvm-project/commit/820d15c8e68fc6405c5ceb9e96b387013bf1f5e7
  Author: Luke Lau <luke at igalia.com>
  Date:   2026-02-16 (Mon, 16 Feb 2026)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vl-opt.ll

  Log Message:
  -----------
  [RISCV] Add test for reducing vl of vlseg2e32.v. NFC


Compare: https://github.com/llvm/llvm-project/compare/12b561a5e208...820d15c8e68f

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