[all-commits] [llvm/llvm-project] af1a5c: [GISel][RISCV] Simplify the generated code for nar...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: af1a5c5c24fa7d0f6fd4445242a0d8f2ce7dd2ba
      https://github.com/llvm/llvm-project/commit/af1a5c5c24fa7d0f6fd4445242a0d8f2ce7dd2ba
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2026-02-13 (Fri, 13 Feb 2026)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctls-rv32.mir

  Log Message:
  -----------
  [GISel][RISCV] Simplify the generated code for narrowScalarCTLS. (#180827)

Instead of trying to make CTLS work for the Lo part, conditionally
invert Lo using the Hi sign bit, then do a CTLZ. If the CTLZ is
zero, then the Lo sign bit differs from the Hi sign bit. Otherwise,
each leading zero represents an additional sign bit.

This generates better code when CTLS and CTLZ are both supported.
I've added Zbb to the P extension command line for RISC-V since
P is likely to imply Zbb when it is ratified, but that isn't written
in the spec yet. If that doesn't happen, I expect CLZ would get
added back to the P extension.



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