[all-commits] [llvm/llvm-project] b79494: [AArch64][clang][llvm] Add ACLE `stshh` atomic sto...

[Jonathan Thackray via All-commits]

  Branch: refs/heads/users/jthackray/acle_pcdphint_arm_atomic_store_with_stshh
  Home:   https://github.com/llvm/llvm-project
  Commit: b7949459c63beced19d2fef9bffa4baec6f11cf8
      https://github.com/llvm/llvm-project/commit/b7949459c63beced19d2fef9bffa4baec6f11cf8
  Author: Jonathan Thackray <jonathan.thackray at arm.com>
  Date:   2026-02-13 (Fri, 13 Feb 2026)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsAArch64.def
    M clang/include/clang/Basic/DiagnosticSemaKinds.td
    M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
    M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
    M clang/lib/Headers/arm_acle.h
    M clang/lib/Sema/SemaARM.cpp
    A clang/test/CodeGen/AArch64/pcdphint-atomic-store.c
    M llvm/include/llvm/IR/IntrinsicsAArch64.td
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

  Log Message:
  -----------
  [AArch64][clang][llvm] Add ACLE `stshh` atomic store builtin

Add `__arm_atomic_store_with_stshh` implementation as defined
in the ACLE. Validate that the arguments passed are correct, and
lower it to the stshh intrinsic plus an atomic store with the
allowed orderings.

Gate this on FEAT_PCDPHINT so that availability matches
hardware support for the `STSHH` instruction. Use an i64
immediate and side-effect modeling to satisfy tablegen and decoding.



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