[all-commits] [llvm/llvm-project] 892ac6: Add HexagonGlobalScheduler pass (#180803)

[Fateme Hosseini via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 892ac614bf8fafd4d13381bb45b369721309785a
      https://github.com/llvm/llvm-project/commit/892ac614bf8fafd4d13381bb45b369721309785a
  Author: Fateme Hosseini <Fhossein at qti.qualcomm.com>
  Date:   2026-02-13 (Fri, 13 Feb 2026)

  Changed paths:
    M llvm/lib/Target/Hexagon/CMakeLists.txt
    M llvm/lib/Target/Hexagon/Hexagon.h
    A llvm/lib/Target/Hexagon/HexagonGlobalScheduler.cpp
    M llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
    M llvm/lib/Target/Hexagon/HexagonRegisterInfo.h
    M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
    M llvm/test/CodeGen/Hexagon/autohvx/hfsplat.ll
    A llvm/test/CodeGen/Hexagon/avoid-debug-increment.mir
    M llvm/test/CodeGen/Hexagon/cext-check.ll
    A llvm/test/CodeGen/Hexagon/dbg-label-pullup.ll
    A llvm/test/CodeGen/Hexagon/global-sched-skip-vsub_fake.ll
    A llvm/test/CodeGen/Hexagon/pull-delayed-new.mir
    A llvm/test/CodeGen/Hexagon/pull-no-comp-code.ll
    A llvm/test/CodeGen/Hexagon/pull-up-dbg-label.mir
    A llvm/test/CodeGen/Hexagon/pull-up-slots.mir
    A llvm/test/CodeGen/Hexagon/pull-up.ll

  Log Message:
  -----------
  Add HexagonGlobalScheduler pass (#180803)

This patch adds the HexagonGlobalScheduler, a post-packetization pass
that performs global instruction scheduling and pull-up optimizations to
improve packet density on Hexagon VLIW architecture.

The scheduler operates on scheduling regions (super-blocks with single
entry and multiple exits) and attempts to move instructions across basic
blocks to fill packet slots more efficiently. It supports both
speculative and predicative scheduling modes.

Key features:
- Global instruction scheduling across basic blocks
- Speculative scheduling with safety checks
- Predicative scheduling using predication
- Local pull-up within basic blocks
- Dual jump formation
- Branch optimizations
- Liveness preservation using HexagonLiveVariables

The pass depends on HexagonLiveVariables and HexagonGlobalRegion
infrastructure for maintaining correct liveness information when moving
instructions across basic block boundaries.

This patch also adds two helper functions to HexagonRegisterInfo that
are required by the scheduler to prevent correctness issues.

1. isGlobalReg(MCPhysReg Reg) - Returns true for reserved physical
registers (R29, R30, R31) that are live across function calls. This
prevents the scheduler from incorrectly speculating instructions that
modify the stack pointer or frame pointer.

2. isFakeReg(MCPhysReg Reg) - Returns true for fake HVX registers
(VF0-VF31, VFR0-VFR31) used as sub-registers in vector pairs. This
prevents crashes when the scheduler processes HVX vector operations by
skipping these internal bookkeeping registers.

The scheduler runs in the pre-emit pipeline after packetization and is
only active when optimizations are enabled.

Patch by Sergei Larin <slarin at qti.qualcomm.com>

Co-authored-by: Ikhlas Ajbar <iajbar at qti.qualcomm.com>
Co-authored-by: Krzysztof Parzyszek <kparzysz at codeaurora.org>



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