[all-commits] [llvm/llvm-project] c6f247: [RISCV] Fix ordering of CHECK prefixes in some tes...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c6f24719afa3d76f12a26604936898cbfc4568a5
      https://github.com/llvm/llvm-project/commit/c6f24719afa3d76f12a26604936898cbfc4568a5
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2026-02-12 (Thu, 12 Feb 2026)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll

  Log Message:
  -----------
  [RISCV] Fix ordering of CHECK prefixes in some tests to mitigate UTC bug. NFCI (#181259)

This patch fixes the exact same problem as #173125 . Where certain order
of CHECK prefixes will somehow causing UTC to incorrectly (re)generate
surplus check lines and failed the tests.



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