[all-commits] [llvm/llvm-project] 046ee4: [CodeGen] Expand power-of-2 div/rem at IR level in...

[Daniil Fukalov via All-commits]

  Branch: refs/heads/users/dfukalov/add_ir_pow2expansion
  Home:   https://github.com/llvm/llvm-project
  Commit: 046ee44ee6417481a9afdca3683185570fb306a6
      https://github.com/llvm/llvm-project/commit/046ee44ee6417481a9afdca3683185570fb306a6
  Author: Daniil Fukalov <dfukalov at gmail.com>
  Date:   2026-02-12 (Thu, 12 Feb 2026)

  Changed paths:
    M llvm/lib/CodeGen/ExpandIRInsts.cpp
    M llvm/test/CodeGen/AMDGPU/div_i128.ll
    M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
    M llvm/test/CodeGen/AMDGPU/rem_i128.ll
    M llvm/test/CodeGen/RISCV/div_minsize.ll
    M llvm/test/CodeGen/X86/div_i129_v_pow2k.ll
    M llvm/test/Transforms/ExpandIRInsts/X86/sdiv129.ll
    M llvm/test/Transforms/ExpandIRInsts/X86/srem129.ll
    M llvm/test/Transforms/ExpandIRInsts/X86/udiv129.ll
    M llvm/test/Transforms/ExpandIRInsts/X86/urem129.ll

  Log Message:
  -----------
  [CodeGen] Expand power-of-2 div/rem at IR level in ExpandIRInsts.

Previously, power-of-2 div/rem operations wider than
MaxLegalDivRemBitWidth were excluded from IR expansion and left for
backend peephole optimizations. Some backends can fail to process such
instructions in case we switch off DAGCombiner.

Now ExpandIRInsts expands them into shift/mask sequences:
- udiv X, 2^C  ->  lshr X, C
- urem X, 2^C  ->  and X, (2^C - 1)
- sdiv X, 2^C  ->  bias adjustment + ashr X, C
- srem X, 2^C  ->  X - (((X + Bias) >> C) << C)

Special cases handled:
- Division/remainder by 1 or -1 (identity, negation, or zero)
- Exact division (sdiv exact skips bias, produces ashr exact)
- Negative power-of-2 divisors (result is negated)
- INT_MIN divisor (correct via countr_zero on bit pattern)


  Commit: 9f4ed865711848d315525aeb461f425b050ebb4c
      https://github.com/llvm/llvm-project/commit/9f4ed865711848d315525aeb461f425b050ebb4c
  Author: Daniil Fukalov <dfukalov at gmail.com>
  Date:   2026-02-12 (Thu, 12 Feb 2026)

  Changed paths:
    M llvm/lib/CodeGen/ExpandIRInsts.cpp
    M llvm/test/CodeGen/AMDGPU/div_i128.ll
    M llvm/test/CodeGen/X86/div_i129_v_pow2k.ll
    M llvm/test/CodeGen/X86/i128-sdiv.ll
    A llvm/test/Transforms/ExpandIRInsts/X86/divrem-pow2.ll
    M llvm/test/Transforms/ExpandIRInsts/X86/sdiv129.ll
    M llvm/test/Transforms/ExpandIRInsts/X86/srem129.ll
    M llvm/test/Transforms/ExpandIRInsts/X86/udiv129.ll
    M llvm/test/Transforms/ExpandIRInsts/X86/urem129.ll

  Log Message:
  -----------
  Addressed review comments:

- Added proofs for power-of-2 div/rem expansion in ExpandIRInsts at
  https://alive2.llvm.org/ce/z/Y-iWm-
- Tests updated as requested.

Also added CreateFreeze() where needed.


Compare: https://github.com/llvm/llvm-project/compare/0e726201e51e...9f4ed8657118

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