[all-commits] [llvm/llvm-project] 5ec570: Reapply "[MC][TableGen] Expand Opcode field of MCI...

[sstipano via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5ec5701db3cfb44fd125413f9a246f6e2d80ac84
      https://github.com/llvm/llvm-project/commit/5ec5701db3cfb44fd125413f9a246f6e2d80ac84
  Author: sstipano <sstipano7 at gmail.com>
  Date:   2026-02-12 (Thu, 12 Feb 2026)

  Changed paths:
    M llvm/docs/HowToUseInstrMappings.rst
    M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
    M llvm/include/llvm/CodeGen/MachineInstr.h
    M llvm/include/llvm/MC/MCInstrDesc.h
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    M llvm/lib/MCA/InstrBuilder.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.h
    M llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp
    M llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h
    M llvm/lib/Target/AMDGPU/R600InstrInfo.h
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    M llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
    M llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
    M llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
    M llvm/lib/Target/SystemZ/SystemZInstrInfo.h
    M llvm/lib/Target/WebAssembly/TargetInfo/WebAssemblyTargetInfo.h
    M llvm/test/TableGen/get-named-operand-idx.td
    M llvm/utils/TableGen/AsmMatcherEmitter.cpp
    M llvm/utils/TableGen/CodeGenMapTable.cpp
    M llvm/utils/TableGen/InstrInfoEmitter.cpp

  Log Message:
  -----------
  Reapply "[MC][TableGen] Expand Opcode field of MCInstrDesc" (#180321) (#180954)

Difference from the previous version is that this one doesn't actually
encode opcodes in matcher tables as 32 bits, but still as 16 bits.



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