[all-commits] [llvm/llvm-project] db5889: [RISCV] Use NSRL/NSRA for legalizing i64 shifts wi...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: db588931c5bca3f09965689b883a56abf322bbd4
      https://github.com/llvm/llvm-project/commit/db588931c5bca3f09965689b883a56abf322bbd4
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2026-02-11 (Wed, 11 Feb 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
    M llvm/test/CodeGen/RISCV/rv32p.ll

  Log Message:
  -----------
  [RISCV] Use NSRL/NSRA for legalizing i64 shifts with P extension on RV32. (#181040)

If the shift amount might be in the range [0, 31], we can use
NSRL/NSRA to shift the i64 value to compute the lower 32 bits of
the result.

If the shift amount is >= 32, the high half of the result is all
zeros or sign bits. Otherwise it is a srl/sra of the high bits.

I've handled the constant case in ReplaceNodeResults but deferred
the non-constant case to lowerShiftRightParts. This function is
not called for constants. This gives the opportunity for DAGCombine to
optimize the SRL_PARTS/SRA_PARTS if the shift amount can be proven
to be >= 32 or < 32.

Sequences were also discussed on the P extension mailing list here
https://lists.riscv.org/g/tech-p-ext/message/861

Assisted-by: claude



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