[all-commits] [llvm/llvm-project] 7cc7a9: [AMDGPU][Scheduler] Fix inconsistent MI slots afte...

[Lucas Ramirez via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7cc7a94128931891b7f00414edcf01c76e255483
      https://github.com/llvm/llvm-project/commit/7cc7a94128931891b7f00414edcf01c76e255483
  Author: Lucas Ramirez <11032120+lucas-rami at users.noreply.github.com>
  Date:   2026-02-12 (Thu, 12 Feb 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
    M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
    A llvm/test/CodeGen/AMDGPU/misched-remat-revert.ll

  Log Message:
  -----------
  [AMDGPU][Scheduler] Fix inconsistent MI slots after rematerialization revert  (#180646)

This fixes an issue in the scheduler's rematerialization stage wherein
slot indices could end up being inconsistent with respect to MI order
following a scheduling revert coupled with rematerialization rollbacks.

When a region's schedule is reverted, instructions are re-ordered into
the region's original instruction order. Furthermore, non-debug
instructions have their slot moved if necessary to maintain consistency
between MI and slot order. Importantly, the rematerialization stage
marks rematerialized MIs as debug during re-scheduling. When reverting
the schedule of regions that have had some of their MIs rematerialized,
the latter are still marked debug, and therefore maintain their
pre-re-scheduling slot even if it no longer is consistent with MI order.

This fixes the issue by restoring the original state of rematerialized
MIs before reverting region schedules, ensuring they are moved if
necessary. An EXPENSIVE_CHECK is added to check that slot order
makes sense with respect to MI order in re-scheduled regions.

Fixes SWDEV-579187.



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