[all-commits] [llvm/llvm-project] 26add8: [AMDGPU][ISel] `setcc` peephole for comparisons wi...

zGoldthorpe via All-commits all-commits at lists.llvm.org
Wed Feb 11 12:41:25 PST 2026


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 26add8a27277f1495ef705d323fdee12975ab950
      https://github.com/llvm/llvm-project/commit/26add8a27277f1495ef705d323fdee12975ab950
  Author: zGoldthorpe <Zach.Goldthorpe at amd.com>
  Date:   2026-02-11 (Wed, 11 Feb 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
    M llvm/test/CodeGen/AMDGPU/commute-compares.ll
    M llvm/test/CodeGen/AMDGPU/div_i128.ll
    M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
    M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
    M llvm/test/CodeGen/AMDGPU/extract-subvector.ll
    M llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll
    M llvm/test/CodeGen/AMDGPU/itofp.i128.ll
    M llvm/test/CodeGen/AMDGPU/rem_i128.ll
    M llvm/test/CodeGen/AMDGPU/saddo.ll
    M llvm/test/CodeGen/AMDGPU/saddsat.ll
    A llvm/test/CodeGen/AMDGPU/setcc-select.ll
    M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
    M llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll

  Log Message:
  -----------
  [AMDGPU][ISel] `setcc` peephole for comparisons with upper 32 bits of a 64-bit register pair (#177662)

This optimisation is motivated by [this minimal
example](https://godbolt.org/z/9o83GvGsM).

Particularly, if `mask` is a 64-bit integer, a select
```cpp
auto out = ((mask >> 32) != 0) ? a : b;
```
converts the null-check on the higher 32-bits of `mask` into a
`v_cmp_lt_u64` with the integer `1 << 32` stored in a pair of VGPRs
(effectively wasting two VGPRs).

More generally, if a 64-bit integer (whose lower 32 bits are known to be
irrelevant) is compared with a 64-bit constant, two VGPRs are wasted to
construct this constant.

This patch modifies ISel to take advantage of how 64-bit values are
stored in pairs of VGPRs (or SGPRs), and truncates the 64-bit constant
to its upper 32-bit constant where possible.

Alive2 proof for analogous middle-end transformation:
https://alive2.llvm.org/ce/z/zizKms



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