[all-commits] [llvm/llvm-project] 5d21da: [AArch64] Eliminate XTN/SSHLL for vector splats

[Guy David via All-commits]

  Branch: refs/heads/users/guy-david/aarch64-dup-trunc-combine
  Home:   https://github.com/llvm/llvm-project
  Commit: 5d21da981dd5226e6bc482a609d7f641ace4549a
      https://github.com/llvm/llvm-project/commit/5d21da981dd5226e6bc482a609d7f641ace4549a
  Author: Guy David <guyda96 at gmail.com>
  Date:   2026-02-11 (Wed, 11 Feb 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    A llvm/test/CodeGen/AArch64/vec-combine-dup-trunc-sext.ll

  Log Message:
  -----------
  [AArch64] Eliminate XTN/SSHLL for vector splats

Combine:
  sext(duplane(insert_subvector(undef, trunc(X), 0), idx))
Into:
  duplane(X, idx)

This avoids XTN/SSHLL instruction sequences that occur when splatting
elements from boolean vectors after type legalization, which is common
when using shufflevector with comparison results.



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