[all-commits] [llvm/llvm-project] 47ddde: Lower misaligned register spills to 32-bit access.

[Aaditya via All-commits]

  Branch: refs/heads/users/easyonaadit/amdgpu/remove-alignment-constraint-from-spill-pseudos
  Home:   https://github.com/llvm/llvm-project
  Commit: 47ddde72ad48661aefdec7313c13c4861052c5c8
      https://github.com/llvm/llvm-project/commit/47ddde72ad48661aefdec7313c13c4861052c5c8
  Author: Aaditya <Aaditya.AlokDeshpande at amd.com>
  Date:   2026-02-11 (Wed, 11 Feb 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/test/CodeGen/AMDGPU/vgpr-spill.mir

  Log Message:
  -----------
  Lower misaligned register spills to 32-bit access.



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