[all-commits] [llvm/llvm-project] 355b67: [MLIR][NFC] Ignore clang-tidy `modernize-use-using...
Sameer Sahasrabuddhe via All-commits
all-commits at lists.llvm.org
Mon Feb 9 23:18:19 PST 2026
Branch: refs/heads/users/ssahsara/async-lds-dma
Home: https://github.com/llvm/llvm-project
Commit: 355b676f2fe419b02d1324dcc04e827d265a1d3e
https://github.com/llvm/llvm-project/commit/355b676f2fe419b02d1324dcc04e827d265a1d3e
Author: Twice <twice at apache.org>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M mlir/.clang-tidy
Log Message:
-----------
[MLIR][NFC] Ignore clang-tidy `modernize-use-using` check in C code (#180326)
In the MLIR C API headers, clang-tidy’s `modernize-use-using` check
reports a large number of type definitions that use `typedef`. In my
IDE, this even causes the `typedef` code to be shown as struck through.
However, in this case it is clearly not possible to replace them with
`using`. This PR suppresses the `modernize-use-using` check for the code
inside `extern "C"` blocks.
Commit: 8e02d249ba5db620ca0d0962f1b49f4b210fcee7
https://github.com/llvm/llvm-project/commit/8e02d249ba5db620ca0d0962f1b49f4b210fcee7
Author: Devanshi <devanshitiwari250 at gmail.com>
Date: 2026-02-08 (Sun, 08 Feb 2026)
Changed paths:
M bolt/include/bolt/Profile/DataAggregator.h
Log Message:
-----------
[Bolt] Replace -1ULL/-2ULL/-3ULL with std::numeric_limits in DataAggregator (#178597)
Replace instances of -1ULL, -2ULL, and -3ULL with std::numeric_limits in
Bolt DataAggregator Trace constants to address C4146 compiler warning.
Changes:
- BR_ONLY: -1ULL → std::numeric_limits<uint64_t>::max()
- FT_ONLY: -1ULL → std::numeric_limits<uint64_t>::max()
- FT_EXTERNAL_ORIGIN: -2ULL → std::numeric_limits<uint64_t>::max() - 1
- FT_EXTERNAL_RETURN: -3ULL → std::numeric_limits<uint64_t>::max() - 2
Fixes part of #147439
Commit: fad32ff3eaf09c140bf441600f7907e8e20af2a2
https://github.com/llvm/llvm-project/commit/fad32ff3eaf09c140bf441600f7907e8e20af2a2
Author: JaydeepChauhan14 <chauhan.jaydeep.ashwinbhai at intel.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/combine-adc.ll
Log Message:
-----------
[X86] Optimized ADC + ADD to ADC (#176713)
Commit: 151fadecd15b8c0b2f233b0df4292776a093ee19
https://github.com/llvm/llvm-project/commit/151fadecd15b8c0b2f233b0df4292776a093ee19
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
A llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/features-info.ll
A llvm/test/MC/RISCV/rvv/zvabd-invalid.s
A llvm/test/MC/RISCV/rvv/zvabd.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV][MC] Support experimental Zvabd instructions
The `Zvabd` is for `RISC-V Integer Vector Absolute Difference` and
it provides 5 instructions:
* `vabs.v`: Vector Signed Integer Absolute.
* `vabd.vv`: Vector Signed Integer Absolute Difference.
* `vabdu.vv`: Vector Unsigned Integer Absolute Difference.
* `vwabda.vv`: Vector Signed Integer Absolute Difference And Accumulate.
* `vwabdau.vv`: Vector Unsigned Integer Absolute Difference And Accumulate.
Doc: https://github.com/riscv/integer-vector-absolute-difference
Reviewers: topperc, lukel97, preames, tclin914, asb, kito-cheng, mshockwave
Pull Request: https://github.com/llvm/llvm-project/pull/180139
Commit: e992593341688862f658348f82e83a0f89a84b2f
https://github.com/llvm/llvm-project/commit/e992593341688862f658348f82e83a0f89a84b2f
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
M llvm/test/CodeGen/RISCV/rvv/abd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
Log Message:
-----------
[RISCV][CodeGen] Lower `abds`/`abdu` to `Zvabd` instructions
We directly lower `ISD::ABDS`/`ISD::ABDU` to `Zvabd` instructions.
Note that we only support SEW=8/16 for `vabd.vv`/`vabdu.vv`.
Reviewers: mshockwave, lukel97, topperc, preames, tclin914, 4vtomat
Reviewed By: lukel97, topperc
Pull Request: https://github.com/llvm/llvm-project/pull/180141
Commit: aa808967eb96995f58288bb3bc0f37516ca70cbe
https://github.com/llvm/llvm-project/commit/aa808967eb96995f58288bb3bc0f37516ca70cbe
Author: Steffen Larsen <sholstla at amd.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaType.cpp
A clang/test/SemaHIP/shared-variable-too-large.hip
A clang/test/SemaOpenCL/amdgpu-variables-too-large-for-address-space.cl
Log Message:
-----------
[Clang][HIP][CUDA] Validate that variable type fits in address spaces (#178909)
Currently, Clang only checks arrays and structures for size at a
top-level view, that is it does not consider whether they will fit in
the address space when applying the address space attribute. This can
lead to situations where a variable is declared in an address space but
its type is too large to fit in that address space, leading to
potentially invalid modules.
This patch proposes a fix for this by checking the size of the type
against the maximum size that can be addressed in the given address
space when applying the address space attribute.
This does not currently handle instantiations of dependent variables, as
the attributes are not re-processesd at that time. This is planned for
further investigation and a follow-up patch.
---------
Signed-off-by: Steffen Holst Larsen <HolstLarsen.Steffen at amd.com>
Co-authored-by: Steffen Holst Larsen <HolstLarsen.Steffen at amd.com>
Commit: 972e73b812cb7b6dd349c7c07daae73314f29e8f
https://github.com/llvm/llvm-project/commit/972e73b812cb7b6dd349c7c07daae73314f29e8f
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
M llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
Log Message:
-----------
[RISCV][CodeGen] Lower `ISD::ABS` to Zvabd instructions
We add pseudos/patterns for `vabs.v` instruction and handle the
lowering in `RISCVTargetLowering::lowerABS`.
Reviewers: topperc, 4vtomat, mshockwave, preames, lukel97, tclin914
Reviewed By: mshockwave
Pull Request: https://github.com/llvm/llvm-project/pull/180142
Commit: 0c583e784ecec8fbc8115217710d364edc4929b4
https://github.com/llvm/llvm-project/commit/0c583e784ecec8fbc8115217710d364edc4929b4
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaAMDGPU.cpp
A clang/test/SemaOpenCL/builtins-amdgcn-s-wait-event.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll
Log Message:
-----------
AMDGPU: Add llvm.amdgcn.s.wait.event intrinsic (#180170)
Exactly match the s_wait_event instruction. For some reason we already
had this instruction used through llvm.amdgcn.s.wait.event.export.ready,
but that hardcodes a specific value. This should really be a bitmask
that
can combine multiple wait types.
gfx11 -> gfx12 broke compatabilty in a weird way, by inverting the
interpretation of the bit but also shifting the used bit by 1. Simplify
the selection of the old intrinsic by just using the magic number 2,
which should satisfy both cases.
Commit: e16f35493c06d10682fca840786012266a591b42
https://github.com/llvm/llvm-project/commit/e16f35493c06d10682fca840786012266a591b42
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/abs.ll
Log Message:
-----------
[RISCV][TTI] Adjust the cost of `llvm.abs` intrinsic when `Zvabd` exists
When `Zvabd` exists, `llvm.abs` is lowered to `vabs.v` so the cost
is 1.
Reviewers: mshockwave, topperc, lukel97, skachkov-sc, preames
Reviewed By: topperc
Pull Request: https://github.com/llvm/llvm-project/pull/180146
Commit: f2d5b3952b3fde599e303c3fdf8fb4d40f113a4d
https://github.com/llvm/llvm-project/commit/f2d5b3952b3fde599e303c3fdf8fb4d40f113a4d
Author: Luke Lau <luke at igalia.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll
M llvm/test/Analysis/CostModel/RISCV/splice.ll
Log Message:
-----------
[RISCV] Add cost for @llvm.vector.splice.{left,right} (#179219)
Currently vector splice intrinsics are costed through getShuffleCost
when the offset is fixed. When the offset is variable though we can't
use a shuffle mask so it currently returns invalid.
This implements the cost in RISCVTTIImpl::getIntrinsicInstrCost as the
cost of a slideup and a slidedown, which matches the codegen.
It also implements the type based cost whenever the offset argument
isn't available.
It may be possible to reduce the cost in future when one of the vector
operands is known to be poison, in which case we only generate a single
slideup or slidedown.
Commit: 6c31bf0474942f8452965c38e091008235730988
https://github.com/llvm/llvm-project/commit/6c31bf0474942f8452965c38e091008235730988
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Transforms/Utils/PredicateInfo.cpp
M llvm/test/Transforms/SCCP/assume-operand-bundles.ll
Log Message:
-----------
[PredicateInfo] Fix crash on nonnull assume taking a constant (#180440)
Commit: 8554ed738f870bdd3eb5fb05a61fa98cd66eaddd
https://github.com/llvm/llvm-project/commit/8554ed738f870bdd3eb5fb05a61fa98cd66eaddd
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll
M llvm/test/MC/AMDGPU/gfx11_asm_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx12_err.s
M llvm/test/MC/AMDGPU/gfx13_asm_sopp.s
Log Message:
-----------
AMDGPU: Add syntax for s_wait_event values (#180272)
Previously this would just print hex values. Print names for the
recognized values, matching the sp3 syntax.
Commit: c1c97088b85cd48a939ecd51bf89576fddcc5e54
https://github.com/llvm/llvm-project/commit/c1c97088b85cd48a939ecd51bf89576fddcc5e54
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/test/CIR/CodeGenBuiltins/AArch64/acle_sve_dup.c
Log Message:
-----------
[CIR][AArch64] Add lowering for predicated SVE svdup builtins (zeroing) (#175976)
This PR adds CIR lowering support for predicated SVE `svdup` builtins on
AArch64. The corresponding ACLE intrinsics are documented at:
https://developer.arm.com/architectures/instruction-sets/intrinsics
This change focuses on the zeroing-predicated variants (suffix `_z`,
e.g. `svdup_n_f32_z`), which lower to the LLVM SVE `dup` intrinsic
with a `zeroinitializer` passthrough operand.
IMPLEMENTATION NOTES
--------------------
* The CIR type converter is extended to support `BuiltinType::SveBool`,
which is lowered to `cir.vector<[16] x i1>`, matching current Clang
behaviour and ensuring compatibility with existing LLVM SVE lowering.
* Added logic that converts `cir.vector<[16] x i1>` according to the
underlying element type. This is done by calling
`@llvm.aarch64.sve.convert.from.svbool`.
TEST NOTES
----------
Compared to the unpredicated `svdup` tests
(https://github.com/llvm/llvm-project/pull/174433), the new tests
perform more explicit checks to verify:
* Correct argument usage
* Correct return value + type
This helped validate differences between the default Clang lowering and
the CIR-based lowering. Once all `svdup` variants are implemented, the tests
will be unified.
EXAMPLE LOWERING
----------------
The following example illustrates that CIR lowering produces equivalent
LLVM IR to the default Clang path.
Input:
```c
svint8_t test_svdup_n_s8(svbool_t pg, int8_t op) {
return svdup_n_s8_z(pg, op);
}
OUTPUT 1 (default):
```llvm
define dso_local <vscale x 16 x i8> @test(<vscale x 16 x i1> %pg, i8
noundef %op) #0 {
entry:
%pg.addr = alloca <vscale x 16 x i1>, align 2
%op.addr = alloca i8, align 1
store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
store i8 %op, ptr %op.addr, align 1
%0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
%1 = load i8, ptr %op.addr, align 1
%2 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.nxv16i8(<vscale x 16
x i8> zeroinitializer, <vscale x 16 x i1> %0, i8 %1)
ret <vscale x 16 x i8> %2
}
```
OUTPUT 2 (via `-fclangir`):
```llvm
; Function Attrs: noinline
define dso_local <vscale x 16 x i8> @test(<vscale x 16 x i1> %0, i8 %1)
#0 {
%3 = alloca <vscale x 16 x i1>, i64 1, align 2
%4 = alloca i8, i64 1, align 1
%5 = alloca <vscale x 16 x i8>, i64 1, align 16
store <vscale x 16 x i1> %0, ptr %3, align 2
store i8 %1, ptr %4, align 1
%6 = load <vscale x 16 x i1>, ptr %3, align 2
%7 = load i8, ptr %4, align 1
%8 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.nxv16i8(<vscale x 16
x i8> zeroinitializer, <vscale x 16 x i1> %6, i8 %7)
store <vscale x 16 x i8> %8, ptr %5, align 16
%9 = load <vscale x 16 x i8>, ptr %5, align 16
ret <vscale x 16 x i8> %9
}
```
Commit: 531430b614cf8a5122335168abbc54096b5225a2
https://github.com/llvm/llvm-project/commit/531430b614cf8a5122335168abbc54096b5225a2
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Transforms/InstCombine/maxnum.ll
M llvm/test/Transforms/InstCombine/minnum.ll
Log Message:
-----------
[InstCombine] Relax one-use check for min/max(fpext x, fpext y) to fpext(min/max(x, y)) fold (#180164)
If only of the operands is one-use, the total number of fpexts stays the
same, but the min/max is performed on a narrowed type. Additionally, the
fpext may fold with a following fptrunc.
Commit: 2ead49ff09802bec6fdaad69133369357299a3b9
https://github.com/llvm/llvm-project/commit/2ead49ff09802bec6fdaad69133369357299a3b9
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/test/Transforms/PhaseOrdering/d83507-knowledge-retention-bug.ll
Log Message:
-----------
[PhaseOrdering] Regenerate test checks (NFC)
The partial check lines while claiming UTC output here were
highly confusing. Regenerate the check lines. While here, use a
newer version and rename blocks to avoid anon block conflicts.
Commit: b79ba024790200d8e3900cdd050585c962535eb6
https://github.com/llvm/llvm-project/commit/b79ba024790200d8e3900cdd050585c962535eb6
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.td
M clang/include/clang/Sema/SemaAMDGPU.h
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/CodeGen/TargetInfo.cpp
M clang/lib/CodeGen/TargetInfo.h
M clang/lib/CodeGen/Targets/AMDGPU.cpp
M clang/lib/CodeGen/Targets/SPIR.cpp
M clang/lib/Sema/SemaAMDGPU.cpp
A clang/test/CodeGenHIP/builtins-amdgcn-gfx1250-cooperative-atomics-templated.hip
A clang/test/CodeGenHIP/builtins-amdgcn-gfx1250-load-monitor-templated.hip
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-load-monitor.cl
A clang/test/SemaHIP/builtins-amdgcn-gfx1250-cooperative-atomics-templated.hip
A clang/test/SemaHIP/builtins-amdgcn-gfx1250-load-monitor-templated.hip
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl
M llvm/docs/AMDGPUUsage.rst
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
Log Message:
-----------
[AMDGPU][GFX12.5] Reimplement monitor load as an atomic operation (#177343)
Load monitor operations make more sense as atomic operations, as
non-atomic operations cannot be used for inter-thread communication w/o
additional synchronization.
The previous built-in made it work because one could just override the
CPol bits, but that bypasses the memory model and forces the user to learn
about ISA bits encoding.
Making load monitor an atomic operation has a couple of advantages.
First, the memory model foundation for it is stronger. We just lean on the
existing rules for atomic operations. Second, the CPol bits are abstracted away
from the user, which avoids leaking ISA details into the API.
This patch also adds supporting memory model and intrinsics
documentation to AMDGPUUsage.
Solves SWDEV-516398.
Commit: a654a27fcd4a44e6c76a93fabc11aed2cb3b97ef
https://github.com/llvm/llvm-project/commit/a654a27fcd4a44e6c76a93fabc11aed2cb3b97ef
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Transforms/InstCombine/minnum.ll
Log Message:
-----------
[InstCombine] Fold min/max(fpext x, C) to fpext(min/max(x, fptrunc C)) (#179968)
Fold `min/max(fpext x, C)` to `fpext(min/max(x, fptrunc C))` in cases
where the truncation of the constant is lossless.
This helps eliminate fpext/fptrunc pairs around min/max and addresses
the regression from https://github.com/llvm/llvm-project/pull/177988.
Proof: https://alive2.llvm.org/ce/z/y_Bcdd
Commit: 25315f287c08f4ab50198461dd84ac8d2eed8cc7
https://github.com/llvm/llvm-project/commit/25315f287c08f4ab50198461dd84ac8d2eed8cc7
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Log Message:
-----------
[AMDGPU] Remove `NoNaNsFPMath` uses (#180469)
Should use `nnan` flag only.
Commit: 2298b8606d84262ef0f420524c9afdded6d71470
https://github.com/llvm/llvm-project/commit/2298b8606d84262ef0f420524c9afdded6d71470
Author: Gergo Stomfai <55883018+stomfaig at users.noreply.github.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-ctls.mir
M llvm/test/CodeGen/AArch64/cls.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32p.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64p.ll
Log Message:
-----------
[GISel] computeKnownBits - add CTLS handling (#178063)
Closes llvm/llvm-project#174370
Commit: fe91384a5b3766894951c5832ea88a0391f82bf1
https://github.com/llvm/llvm-project/commit/fe91384a5b3766894951c5832ea88a0391f82bf1
Author: Arun Thangamani <arun.thangamani at intel.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M mlir/include/mlir/Dialect/Vector/TransformOps/VectorTransformOps.td
M mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp
M mlir/test/Dialect/Vector/transform-vector.mlir
M mlir/test/python/dialects/transform_vector_ext.py
Log Message:
-----------
[mlir][vector] Wrapping `populateFlattenVectorTransferPatterns` as a transform pass. (#178134)
This PR covers the `mlir::vector::populateFlattenVectorTransferPatterns`
as a transform pass.
Commit: a07347f60997b971314563c7427aff5153677d95
https://github.com/llvm/llvm-project/commit/a07347f60997b971314563c7427aff5153677d95
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/ordering/TestDataFormatterStdOrdering.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/vbool/TestDataFormatterStdVBool.py
M lldb/test/API/functionalities/gdb_remote_client/TestWasm.py
Log Message:
-----------
[lldb][test] Rename/remove duplicate methods in API tests (#180250)
Ran my python script from
https://github.com/llvm/llvm-project/pull/97043 over the repo again and
there were 2 duplicate test-cases that have been introduced since I last
did this.
Also one of the WASM classes had a duplicate method which I just
removed.
Commit: e12c8f08c046af6ae9929b843ec463bcf0a597a5
https://github.com/llvm/llvm-project/commit/e12c8f08c046af6ae9929b843ec463bcf0a597a5
Author: jeanPerier <jperier at nvidia.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
A flang/include/flang/Optimizer/Analysis/ArraySectionAnalyzer.h
A flang/lib/Optimizer/Analysis/ArraySectionAnalyzer.cpp
M flang/lib/Optimizer/Analysis/CMakeLists.txt
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
Log Message:
-----------
[flang][NFC] Extract ArraySectionAnalyzer from OptimizedBufferization (#180278)
Extract `ArraySectionAnalyzer` from `OptimizedBufferization` into a
standalone
analysis utility so it can be reused by other passes (e.g.,
`ScheduleOrderedAssignments`).
Also extracts the logic to detect if a designate is using the indices
of an elemental operation in storage order.
This will be used in WHERE construct optimization in the next patch.
Commit: 233a9918bc18953bc96fb091c8c3e7bd8a95ed4a
https://github.com/llvm/llvm-project/commit/233a9918bc18953bc96fb091c8c3e7bd8a95ed4a
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/loop_dependence_mask.ll
Log Message:
-----------
[AArch64] Tweak fixed-length loop.dependence.mask costs (#175538)
For fixed-length masks we need to AND the result of the whilewr/rw with
`ptrue vl*` (which is at least one more instruction).
Commit: 2ffb54364ff5669da0ed2a0daff744fd3c33ec4a
https://github.com/llvm/llvm-project/commit/2ffb54364ff5669da0ed2a0daff744fd3c33ec4a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
Log Message:
-----------
AMDGPU: Add a test for libcall simplify pow handling (#180491)
This case could be turned into powr or pown, so track which
case ends up preferred.
Commit: 936ec4ea6658106e6b13157c5d14b9b6d5070141
https://github.com/llvm/llvm-project/commit/936ec4ea6658106e6b13157c5d14b9b6d5070141
Author: puneeth_aditya_5656 <myakampuneeth at gmail.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
A lldb/test/Shell/ObjectFile/ELF/stt-tls-symbol.yaml
Log Message:
-----------
[lldb] Handle STT_TLS symbol type in ELF parser (#178975)
Add handling for `STT_TLS` (thread-local storage) symbols in the ELF
symbol parsing code. Previously, TLS symbols like `errno` from glibc
were not recognized because `STT_TLS` was not handled in the symbol type
switch statement.
This treats TLS symbols as data symbols (`eSymbolTypeData`), similar to
`STT_OBJECT`. The actual TLS address resolution is already implemented
in `DynamicLoaderPOSIXDYLD::GetThreadLocalData()` which uses the DWARF
`DW_OP_form_tls_address` opcode to calculate thread-local addresses.
Commit: 4ef7be9b80e156c59a533557e2a0d058cb91019f
https://github.com/llvm/llvm-project/commit/4ef7be9b80e156c59a533557e2a0d058cb91019f
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
Log Message:
-----------
[SimplifyLibCalls] Directly convert fmin/fmax to intrinsics (#177988)
Drop the custom shrinking code, which we'll also do for intrinsics.
Having libcall-only optimizations is confusing, as these are typically
directly emitted as intrinsics by the frontend.
Commit: 3862a4f733002e90ecee7b79aca87bb46d5575b1
https://github.com/llvm/llvm-project/commit/3862a4f733002e90ecee7b79aca87bb46d5575b1
Author: Eliz Habiboullah <eliz4ads at gmail.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
Log Message:
-----------
[GlobalISel] Use named constant for impossible repair cost (#180490)
replace magic value `std::numeric_limits<unsigned>::max()` with a named
constant `ImpossibleRepairCost` to improve readability
Commit: 27a8ab09fa7b5f966b8201377f29f338cdc9fb90
https://github.com/llvm/llvm-project/commit/27a8ab09fa7b5f966b8201377f29f338cdc9fb90
Author: Petr Kurapov <petr.kurapov at amd.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
A llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.ll
A llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.mir
Log Message:
-----------
[AMDGPU] Fix V_INDIRECT_REG_READ_GPR_IDX expansion with immediate index (#179699)
The definition for V_INDIRECT_REG_READ_GPR_IDX_B32_V*'s SSrc_b32 operand
allows immediates, but the expansion logic handles only register cases
now. This can result in expansion failures when e.g.
llvm.amdgcn.wave.reduce.umin.i32 is folded into a constant and then used
as an insertelement idx.
Commit: 964651ad515b61df56ce51cdc9978b2bcc8d0a7b
https://github.com/llvm/llvm-project/commit/964651ad515b61df56ce51cdc9978b2bcc8d0a7b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/select-big-integer.ll
Log Message:
-----------
[X86] Allow handling of i128/256/512 SELECT on the FPU (#180197)
If the scalar integer selection sources are freely transferable to the
FPU, then splat to create an allbits select condition and create a
vector select instead
Commit: 5b2bfcedf501109d188eb39cf63b54cc1c3ca33b
https://github.com/llvm/llvm-project/commit/5b2bfcedf501109d188eb39cf63b54cc1c3ca33b
Author: Matt <MattPD at users.noreply.github.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M flang/lib/Optimizer/Analysis/CMakeLists.txt
Log Message:
-----------
[flang][NFC] Remove dependency on FIRBuilder from FIRAnalysis. (#180300)
The dependency actually appears to be unused.
Co-authored-by: Matt P. Dziubinski <matt-p.dziubinski at hpe.com>
Commit: 2eb811239c2845619285480329a5d78daa9986ef
https://github.com/llvm/llvm-project/commit/2eb811239c2845619285480329a5d78daa9986ef
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/CAS/OnDiskGraphDB.cpp
Log Message:
-----------
[CAS] getInternalFileBackedObjectData - fix MSVC not all control paths return a value warning. NFC. (#180499)
Commit: bf84e84f06ce4e752b54acb6af2c947ce62692d0
https://github.com/llvm/llvm-project/commit/bf84e84f06ce4e752b54acb6af2c947ce62692d0
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/lib/CodeGen/Targets/AMDGPU.cpp
Log Message:
-----------
[clang][amdgpu] getLLVMSyncScopeStr - fix MSVC not all control paths return a value warning. NFC. (#180501)
Commit: 1d61ac2d41d9c77d02af4ac149d83b52eb782704
https://github.com/llvm/llvm-project/commit/1d61ac2d41d9c77d02af4ac149d83b52eb782704
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
Log Message:
-----------
[clang][amdgpu] mapCABIAtomicOrdering - fix MSVC not all control paths return a value warning. NFC. (#180500)
Commit: f71e32196667264607974e22d28d3badb2d73b5e
https://github.com/llvm/llvm-project/commit/f71e32196667264607974e22d28d3badb2d73b5e
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/InterpState.cpp
M clang/lib/AST/ByteCode/InterpState.h
A clang/test/AST/ByteCode/constexpr-steps.cpp
Log Message:
-----------
[clang][bytecode] Implement constexpr step limit (#176150)
This only calls `noteStep()` on jump opcodes, so this works for loops.
It does not prevent "hangs" when a function is just _very_ long (could
be interesting how this interfaces with expand statements?).
Fixes https://github.com/llvm/llvm-project/issues/165951
Commit: f88e0185d7333827f5342143e7c515fc8fb57020
https://github.com/llvm/llvm-project/commit/f88e0185d7333827f5342143e7c515fc8fb57020
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang-tools-extra/clangd/ClangdLSPServer.cpp
Log Message:
-----------
[clangd] Add explicit std::move(...) to avoid a few copies (#180475)
Moving an std::map is almost always profitable (DiagnosticToDiagRefMap).
Changes suggested by performance-use-std-move from #179467
Commit: dbf2caaaef120bb7a9f7cf6b5611ba5584cff887
https://github.com/llvm/llvm-project/commit/dbf2caaaef120bb7a9f7cf6b5611ba5584cff887
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/OHOS.cpp
Log Message:
-----------
[clang] Add explicit std::move(...) to avoid a few copies (#180477)
Moving a clang::MultilibSet is almost always profitable.
Changes suggested by performance-use-std-move from #179467
Commit: a40275c8c821c89046111d4954165daba7a24f36
https://github.com/llvm/llvm-project/commit/a40275c8c821c89046111d4954165daba7a24f36
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/lib/Analysis/CloneDetection.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/StaticAnalyzer/Core/ProgramState.cpp
M clang/lib/Tooling/DependencyScanningTool.cpp
Log Message:
-----------
[clang] Add explicit std::move(...) to avoid a few copies (#180482)
Moving an std::vector is almost always profitable.
A clang::CXXScopeSpec contains an owned
clang::NestedNameSpecifierLocBuilder which currently does not benefit
from being moved, but may structurally in the future.
A clang::MultiLevelTemplateArgumentList contains an llvm::SmalVector
which may benefit from being moved dependiong on its size.
A clang::Environment contains an llvm::ImmutableMap which itself
contains an llvm::IntrusiveRefCntPtr that benefits from being moved.
Changes suggested by performance-use-std-move from #179467
---------
Co-authored-by: Timm Baeder <tbaeder at redhat.com>
Commit: 72ff1cb2f87244ade6dda960946346bb3dc6fd68
https://github.com/llvm/llvm-project/commit/72ff1cb2f87244ade6dda960946346bb3dc6fd68
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M flang/test/Lower/equivalence-with-host-assoc.f90
M flang/test/Lower/explicit-interface-results-2.f90
M flang/test/Lower/explicit-interface-results.f90
M flang/test/Lower/ext-proc-as-actual-argument-1.f90
M flang/test/Lower/ext-proc-as-actual-argument-2.f90
Log Message:
-----------
[flang][NFC] Converted five tests from old lowering to new lowering (part 15) (#179854)
Tests converted from test/Lower: equivalence-with-host-assoc.f90,
explicit-interface-results-2.f90, explicit-interface-results.f90,
ext-proc-as-actual-argument-1.f90, ext-proc-as-actual-argument-2.f90
Commit: 8cd86ff284c3aa1b47c00500a5dc7889b1c9bade
https://github.com/llvm/llvm-project/commit/8cd86ff284c3aa1b47c00500a5dc7889b1c9bade
Author: Luke Lau <luke at igalia.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
A llvm/test/Transforms/LoopVectorize/phi-with-fastflags-vplan.ll
A llvm/test/Transforms/LoopVectorize/phi-with-fastflags.ll
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp
Log Message:
-----------
[VPlan] Propagate FastMathFlags from phis to blends (#180226)
If a phi has fast math flags, we can propagate it to the widened select.
To do this, this patch makes VPPhi and VPBlendRecipe subclasses of
VPRecipeWithIRFlags, and propagates it through PlainCFGBuilder and
VPPredicator.
Alive2 proofs for some of the FMFs (it looks like it can't reason about
the full "fast" set yet)
nnan: https://alive2.llvm.org/ce/z/f0bRd4
nsz: https://alive2.llvm.org/ce/z/u9P96T
The actual motivation for this to eventually be able to move the special
casing for tail folding in
LoopVectorizationPlanner::addReductionResultComputation into the CFG in
#176143, which requires passing through FMFs.
Commit: 0cd8fd974dd674cab2f53cedeb674622413561bd
https://github.com/llvm/llvm-project/commit/0cd8fd974dd674cab2f53cedeb674622413561bd
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M lld/COFF/Driver.cpp
M lld/wasm/OutputSections.cpp
M lld/wasm/Writer.cpp
Log Message:
-----------
[lld] Add explicit std::move(...) to avoid a few vector copies (#180474)
In corner cases, it is profitable to move an llvm::SmallString instead
of copying it.
It is almost always profitable to move an std::vector
Changes suggested by performance-use-std-move from
https://github.com/llvm/llvm-project/pull/179467
Commit: fed9abcb4796507622bdd9e2e36bc80260a5197b
https://github.com/llvm/llvm-project/commit/fed9abcb4796507622bdd9e2e36bc80260a5197b
Author: Prajwal P J <prajwaljalwadi at gmail.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaChecking.cpp
M clang/test/SemaCXX/constant-expression-cxx2a.cpp
Log Message:
-----------
[Clang] Fix missing -Warray-bounds warning on member function calls. (#179647)
Fixes #179128.
This patch fixes a false negative where Clang failed to detect
out-of-bounds access when calling a member function on an invalid array
index. It adds handling for CXXMemberCallExpr in CheckArrayAccess.
Signed-off-by: prajwal jalwadi<prajwaljalwadi at gmail.com>
Commit: bf1340598ec3af1169d47e6deff427fe9e703251
https://github.com/llvm/llvm-project/commit/bf1340598ec3af1169d47e6deff427fe9e703251
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/include/llvm/Support/TargetOpcodes.def
Log Message:
-----------
[CodeGen] Improve documentation for SUBREG_TO_REG (#180504)
The most important change is to remove the claim that the extra bits are
necessarily set to zero.
Commit: 4bb16b130df2f5f132d04fcd8960a860a290402f
https://github.com/llvm/llvm-project/commit/4bb16b130df2f5f132d04fcd8960a860a290402f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-shuffles.ll
Log Message:
-----------
[VectorCombine][X86] Add test coverage for #161980 (#180508)
Commit: 6dbdfd824affb4a0b2beda56af222758500cffa2
https://github.com/llvm/llvm-project/commit/6dbdfd824affb4a0b2beda56af222758500cffa2
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Analysis/ValueTracking/assume-queries-counter.ll
M llvm/test/Transforms/InstCombine/assume.ll
M llvm/test/Transforms/PhaseOrdering/d83507-knowledge-retention-bug.ll
Log Message:
-----------
[InstCombine] Drop nonnull assumes if the pointer is already known to be nonnull (#180434)
Commit: 695095fff67e622309d8059c261e4df0b73fe4a9
https://github.com/llvm/llvm-project/commit/695095fff67e622309d8059c261e4df0b73fe4a9
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M lldb/tools/lldb-dap/Handler/AttachRequestHandler.cpp
Log Message:
-----------
[lldb-dap][NFC] Add new line to attach message (#180510)
Commit: ef68a53139626bf4067889016f82a8fa945fac61
https://github.com/llvm/llvm-project/commit/ef68a53139626bf4067889016f82a8fa945fac61
Author: Sergei Lebedev <185856+superbobry at users.noreply.github.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M utils/bazel/MODULE.bazel.lock
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/build_defs.bzl
A utils/bazel/llvm-project-overlay/mlir/stubgen_runner.py
M utils/bazel/third_party_build/nanobind.BUILD
Log Message:
-----------
[MLIR] [Python] Added plumbing to run stubgen on the mlir._mlir package (#179211)
This allows generating stubs during Bazel builds, which was previously
only supported under CMake.
I decided not to use nanobind_stubgen from nanobind-bazel, because the
py_binary it generates is not easily usable in a genrule.
Commit: f6acc800f2c6e57e2e22bad3f475cd7a01139ca1
https://github.com/llvm/llvm-project/commit/f6acc800f2c6e57e2e22bad3f475cd7a01139ca1
Author: Marina Taylor <marina_taylor at apple.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/test/Driver/darwin-ld-lto.c
Log Message:
-----------
[Driver][Darwin] Pass stack usage file for LTO (#178005)
Add a .su extension to the main output's filename and pass this down to
the LLVM layer.
rdar://143089305
Commit: 4344268ad605a3b77d00a30fb9284f453b240ec0
https://github.com/llvm/llvm-project/commit/4344268ad605a3b77d00a30fb9284f453b240ec0
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/include/clang/AST/Expr.h
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/Context.h
M clang/lib/AST/ExprConstant.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Sema/SemaChecking.cpp
Log Message:
-----------
[clang] Return std::optional from all Expr::tryEvaluate* API (#179230)
tryEvaluateString was returning an std::optional, but the other try* API
was not. Update tryEvaluateObjectSize and tryEvaluateStrLen to return an
std::optional<uint64_t>.
Commit: 2805c8aaa61a94ef22ac76c8dac56f7dfe970651
https://github.com/llvm/llvm-project/commit/2805c8aaa61a94ef22ac76c8dac56f7dfe970651
Author: Luke Lau <luke at igalia.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/phi-with-fastflags.ll
Log Message:
-----------
[VPlan] Add missing REQUIRES: asserts to VPlan output test
Should fix https://lab.llvm.org/buildbot/#/builders/11/builds/33293
Commit: dd356180b3ea7cedec7584dbb9de1e58c9426855
https://github.com/llvm/llvm-project/commit/dd356180b3ea7cedec7584dbb9de1e58c9426855
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
M mlir/test/Dialect/SPIRV/IR/types.mlir
M mlir/test/Dialect/SPIRV/Transforms/replicated-const-composites.mlir
Log Message:
-----------
[mlir][spirv] Verify vector types when parsing (#180430)
Also remove some invalid test cases (replicated constants).
Fixes: https://github.com/llvm/llvm-project/issues/180419
Commit: 45b037cf7a26641bf778bbe7532d99935d35be1b
https://github.com/llvm/llvm-project/commit/45b037cf7a26641bf778bbe7532d99935d35be1b
Author: Mirko Brkušanin <Mirko.Brkusanin at amd.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-amdgcn-fp8.cl
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
A llvm/test/MC/AMDGPU/gfx1150_unsupported.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop1-fake16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop1.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop1_dpp16-fake16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop1_dpp16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop1_dpp8-fake16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop1_dpp8.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3-fake16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3_dpp16-fake16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3_dpp16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3_dpp8-fake16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3_dpp8.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3_err.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1-fake16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1_dpp16-fake16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1_dpp16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1_dpp8-fake16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1_dpp8.s
A llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop1_dpp16.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop1_dpp8.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_dpp16.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_dpp8.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_from_vop1.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_from_vop1_dpp16.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_from_vop1_dpp8.txt
Log Message:
-----------
[AMDGPU] Add fp8/bf8 conversion instructions for gfx1170 (#180191)
Commit: d1b402b61298d7f28578650e452874e51ea818c4
https://github.com/llvm/llvm-project/commit/d1b402b61298d7f28578650e452874e51ea818c4
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/test/Transforms/InstCombine/trunc-extractelement.ll
Log Message:
-----------
[InstCombine] Avoid overflow in `foldVecExtTruncToExtElt` (#180414)
This weird pattern was introduced by LoopVectorize. But it was placed in
an unreachable path, so we cannot assert that the indices are always
valid in InstCombine.
Closes https://github.com/llvm/llvm-project/issues/180233.
Commit: da0ad392ffc689cf4909b487e3d956e074be87c6
https://github.com/llvm/llvm-project/commit/da0ad392ffc689cf4909b487e3d956e074be87c6
Author: Ruoyu Qiu <cabbaken at outlook.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
A llvm/include/llvm/TargetParser/AVRTargetParser.h
M llvm/include/llvm/TargetParser/Triple.h
A llvm/lib/TargetParser/AVRTargetParser.cpp
M llvm/lib/TargetParser/CMakeLists.txt
A llvm/test/tools/llvm-objdump/ELF/AVR/lit.local.cfg
A llvm/test/tools/llvm-objdump/ELF/AVR/mattr.test
M llvm/tools/llvm-objdump/llvm-objdump.cpp
Log Message:
-----------
[llvm-objdump][AVR] Detect AVR architecture from ELF flags for disassembling (#180468)
Reland #174731, resolve cyclic dependency issue.
The use of LLVM_Object in LLVM_Util would cause cyclic dependency.
Fix cyclic dependency by reimplement `getFeatureSetFromEFlag()`.
Original description:
---
This PR updates llvm-objdump to detect the specific AVR architecture
from the ELF header flags when no specific CPU is provided.
Fixes: https://github.com/llvm/llvm-project/issues/146451
Signed-off-by: Ruoyu Qiu <cabbaken at outlook.com>
Commit: 1ff4b503802b049463da4a8fd4aaac496ddd260b
https://github.com/llvm/llvm-project/commit/1ff4b503802b049463da4a8fd4aaac496ddd260b
Author: David Spickett <david.spickett at arm.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M lldb/test/API/driver/batch_mode/TestBatchMode.py
M lldb/tools/driver/Driver.cpp
Log Message:
-----------
[lldb] Quit automatically if --batch has no commands to run (#179969)
Fixes #179700
Simple fix, if we are in batch mode, don't go into an interactive
session after checking if there are commands to run.
Testing it is more tricky. I tried a shell test as I thought it would be
simplest. However to be able to FileCheck I had to pipe and the pipe
turns off the prompt because it's non-interactive. The prompt is the
thing that must not be printed.
So I've just spawned lldb as a subprocess. If it doesn't quit quickly
then something is wrong. The timeout is high not because it should
normally take that long, but because sometimes a process will get
stalled for a while and I don't want this to be flaky.
(though in theory it can get stalled for much longer than a minute)
If it does time out, the process will be cleaned up automatically. See
https://docs.python.org/3/library/subprocess.html#subprocess.run
> A timeout may be specified in seconds, it is internally
> passed on to Popen.communicate(). If the timeout expires,
> the child process will be killed and waited for.
Commit: 7defb0a4a35817ee7accb310d99912152a542ec2
https://github.com/llvm/llvm-project/commit/7defb0a4a35817ee7accb310d99912152a542ec2
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
Log Message:
-----------
[VPlan] Skip applying InstsToScalarize with forced instr costs. (#168269)
ForceTargetInstructionCost in the legacy cost model overrides any costs
from InstsToScalarize. Match the behavior in the VPlan-based cost model.
This fixes a crash with -force-target-instr-cost for the added test
case.
PR: https://github.com/llvm/llvm-project/pull/168269
Commit: 42d5e76b469f56fbf522fe6f119e755db730610b
https://github.com/llvm/llvm-project/commit/42d5e76b469f56fbf522fe6f119e755db730610b
Author: Sergei Druzhkov <serzhdruzhok at gmail.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M lldb/tools/lldb-dap/extension/package-lock.json
M lldb/tools/lldb-dap/extension/package.json
Log Message:
-----------
[lldb-dap] Bump vscode version (#177008)
VS Code and node versions should be synchronized. We use node >= 18.19,
so expected VS Code version is 1.90.0. I checked it using this
[info](https://github.com/ewanharris/vscode-versions).
Commit: b2e6b987839a9b94f6d998805f750515680d31f4
https://github.com/llvm/llvm-project/commit/b2e6b987839a9b94f6d998805f750515680d31f4
Author: Djordje Todorovic <djordje.todorovic at htecgroup.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsFastISel.cpp
A llvm/test/CodeGen/Mips/musttail-fastisel.ll
Log Message:
-----------
[MIPS] Fix argument size in Fast ISel (#180336)
Fix bug where Fast ISel incorrectly set `IncomingArgSize` to `0` for
functions with no arguments, since `MIPS O32` uses _the reserved
argument area_ of 16 bytes even for the functions with no args at all.
Commit: 0bbf25ffd4b2e665e2a36adcd11b732ac8bb74e6
https://github.com/llvm/llvm-project/commit/0bbf25ffd4b2e665e2a36adcd11b732ac8bb74e6
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/test/Transforms/InstCombine/gep-sext.ll
Log Message:
-----------
[InstCombine] Regenerate test checks (NFC)
Commit: 44031ae79f7d3a4a2f56efecb75d4467955c043c
https://github.com/llvm/llvm-project/commit/44031ae79f7d3a4a2f56efecb75d4467955c043c
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll
Log Message:
-----------
[LV] Fix issue in VPFirstOrderRecurrencePHIRecipe::usesFirstLaneOnly (#179977)
In some cases we decide to vectorise loops with first-order recurrences
using VF=1, IC>1. We then attempt to unroll a vplan in replicateByVF,
however when trying to erase the list of values from the parent we
trigger the following assert:
```
virtual llvm::VPRecipeValue::~VPRecipeValue(): Assertion `Users.empty()
&& "trying to delete a VPRecipeValue with remaining users"' failed.
```
The problem seems to stem from this code:
```
DefR->replaceUsesWithIf(LaneDefs[0], [DefR](VPUser &U, unsigned) {
return U.usesFirstLaneOnly(DefR);
});
```
since usesFirstLaneOnly returns false and we fail to replace uses of
DefR with LaneDefs[0]. Upon inspection the only VPUser objects that
return false are VPInstruction::FirstOrderRecurrenceSplice and
VPFirstOrderRecurrencePHIRecipe. Since the values are all scalar it's
simply not possible for us to be using anything other than the first
lane. I've fixed this by bailing out of replicateByVF early for plans with
only a scalar VF.
Fixes https://github.com/llvm/llvm-project/issues/179671
Commit: 33e3384aa899d20c42c89af537f50111e30d68ba
https://github.com/llvm/llvm-project/commit/33e3384aa899d20c42c89af537f50111e30d68ba
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M offload/test/offloading/fortran/basic-target-parallel-do.f90
M offload/test/offloading/fortran/basic-target-parallel-reduction.f90
M offload/test/offloading/fortran/basic-target-teams-parallel-reduction.f90
M offload/test/offloading/fortran/default-mapper-nested-derived-type.f90
M offload/test/offloading/fortran/do-concurrent-to-omp-saxpy-2d.f90
M offload/test/offloading/fortran/do-concurrent-to-omp-saxpy.f90
M offload/test/offloading/fortran/explicit-and-implicit-record-field-mapping.f90
M offload/test/offloading/fortran/implicit-record-field-mapping.f90
M offload/test/offloading/fortran/target-custom-reduction-derivedtype.f90
M offload/test/offloading/fortran/target-no-loop.f90
M offload/test/offloading/fortran/target-parallel-do-collapse.f90
M offload/test/offloading/ompx_bare.c
M offload/test/offloading/ompx_bare_multi_dim.cpp
Log Message:
-----------
[offload] Adapt tests to new PluginInterface quoting [NFC] (#180505)
https://github.com/llvm/llvm-project/commit/4096cb60175a3bfdde25dd0cca167416f4f4338e
removed the quotes around PluginInterface
Commit: dbbea962c9f9e05c56b5566b9b4f66351adf8079
https://github.com/llvm/llvm-project/commit/dbbea962c9f9e05c56b5566b9b4f66351adf8079
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M lldb/test/Shell/DAP/TestSTDINConsole.test
Log Message:
-----------
[lldb-dap][windows] fix invalid path substitution for lldb-dap (#180237)
https://github.com/llvm/llvm-project/pull/178642 added
`lldb/test/Shell/DAP/TestSTDINConsole.test` with an incorrect
`%lldb-dap` expansion. This patch fixes it.
Commit: 041ce9fe0f4ac7bc1a8927153d69418c416a5623
https://github.com/llvm/llvm-project/commit/041ce9fe0f4ac7bc1a8927153d69418c416a5623
Author: David Sherwood <david.sherwood at arm.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/phi-with-fastflags-vplan.ll
Log Message:
-----------
[LV][NFC] Add "REQUIRES: assert" to new test file (#180522)
Fixes a minor test regression introduced by
https://github.com/llvm/llvm-project/pull/180226 in file
llvm/test/Transforms/LoopVectorize/phi-with-fastflags-vplan.ll
Commit: 392f0c976728fdc3c1db1c4e93a8c26d66c5488d
https://github.com/llvm/llvm-project/commit/392f0c976728fdc3c1db1c4e93a8c26d66c5488d
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
A llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx1250.mir
Log Message:
-----------
[NFC][AMDGPU] Add a test to show the impact of wrong `s_mov_b64` instruction size (#180386)
Commit: b13dc236220eb1a6479282eaaa2bd317aef5f233
https://github.com/llvm/llvm-project/commit/b13dc236220eb1a6479282eaaa2bd317aef5f233
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/make/Makefile.rules
Log Message:
-----------
[lldb] add cross platform test commands in Makefile.rules (#180224)
This patch adds cross platform (Darwin, Linux, Windows) commands in
`Makefile.rules` which is used to build lldb test targets.
This maps POSIX commands like `mkdir -p` to their Windows equivalent,
which allows to create cross platform `Makefile` for lldb's test
targets. This is currently not needed by any test but might become
useful later as we are working on enabling more lldb Windows tests.
This was originally done in the `swiftlang/llvm-project` fork
(https://github.com/swiftlang/llvm-project/pull/12127)
Commit: ed19bbfe01d4fcf5d457cb563cb900763b8f2189
https://github.com/llvm/llvm-project/commit/ed19bbfe01d4fcf5d457cb563cb900763b8f2189
Author: Luke Lau <luke at igalia.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/phi-with-fastflags.ll
Log Message:
-----------
Revert "[VPlan] Add missing REQUIRES: asserts to VPlan output test"
This reverts commit 2805c8aaa61a94ef22ac76c8dac56f7dfe970651.
This added the REQUIRES line to the wrong test, 041ce9f added it to the
correct one.
Commit: f6ee5bd4dfea88604ac27c0cc11b48ec1500e325
https://github.com/llvm/llvm-project/commit/f6ee5bd4dfea88604ac27c0cc11b48ec1500e325
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
A llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/apint-constant.ll
Log Message:
-----------
[SPIRV] Fix constant materialization for width > 64bit (#180182)
selectConst() was asserting for constants wider than 64 bits. Add APInt
overloads of getOrCreateConstInt and getOrCreateConstVector that avoid
the uint64_t truncation.
Commit: d8e679c28650082a97675c8edeaa01fac3e695c1
https://github.com/llvm/llvm-project/commit/d8e679c28650082a97675c8edeaa01fac3e695c1
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/X86/shuffle-transpose.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-shuffles.ll
Log Message:
-----------
[CostModel][X86] getShuffleCost - SK_Transpose v4f64/v4i64 matches UNPCK - don't generalise to SK_PermuteTwoSrc (#180514)
Other SK_Transpose shuffles can be cheaper than SK_PermuteTwoSrc but this is the easy one to handle
Fixes #161980
Commit: b4bc9fa1c6eec1fc4789f203326b01368bffc63b
https://github.com/llvm/llvm-project/commit/b4bc9fa1c6eec1fc4789f203326b01368bffc63b
Author: Christian Sigg <csigg at google.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Port da0ad392ffc6.
Commit: 03ab85cb873eee64da5a4a34c44955682bdc7e34
https://github.com/llvm/llvm-project/commit/03ab85cb873eee64da5a4a34c44955682bdc7e34
Author: Kiva <imkiva at islovely.icu>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
A llvm/test/Transforms/InstCombine/gep-srem-to-and-deref.ll
Log Message:
-----------
[InstCombine] fold `gepi _, (srem x, y)` to `gepi _, (urem x, y)` if `y` is power-of-2 (#180148)
This PR adds a small, targeted InstCombine fold for the pattern:
```
%idx = srem i64 %x, 2^k
%p = getelementptr inbounds nuw i8, ptr %base, i64 %idx
```
When the GEP is inbounds + nuw, and the divisor is a non-zero
power-of-two constant, the signed remainder cannot produce a negative
offset without violating the inbounds/nuw constraints. In that case we
can canonicalize the index to a non-negative form and expose the common
power-of-two rewrite:
- Rewrite the GEP index from `srem %x, 2^k` to `urem %x, 2^k`
- Create a new GEP with the new index and replace the original GEP
- the `urem %x, 2^k` will further folds to `and %x (2^k-1)`
resulting the following pattern
```
%idx = and i64 %x, (2^k-1)
%p = getelementptr inbounds nuw i8, ptr %base, i64 %idx
```
Fixes #180097.
generalized alive2 proof: https://alive2.llvm.org/ce/z/8EBxug
Commit: f9528a3608a2aa4094c982dcb093bd191524c72d
https://github.com/llvm/llvm-project/commit/f9528a3608a2aa4094c982dcb093bd191524c72d
Author: Baranov Victor <bar.victor.2002 at gmail.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
A clang/test/Sema/warn-lifetime-safety-fixits.cpp
Log Message:
-----------
[LifetimeSafety] Add fixit verification with FileCheck (#180488)
Verify that produced messages/fixes are located in the right place.
With this patch, we can proceed to do
https://github.com/llvm/llvm-project/issues/180344
Commit: fccbdcb15a1347e96a15e95ff540e03aea87ca00
https://github.com/llvm/llvm-project/commit/fccbdcb15a1347e96a15e95ff540e03aea87ca00
Author: Twice <twice at apache.org>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
A mlir/include/mlir-c/ExtensibleDialect.h
M mlir/include/mlir/Bindings/Python/IRCore.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/CAPI/IR/CMakeLists.txt
A mlir/lib/CAPI/IR/ExtensibleDialect.cpp
M mlir/test/python/dialects/ext.py
Log Message:
-----------
[MLIR][Python] Support dynamic traits in python-defined dialects (#179705)
This is a follow-up PR of #169045 and the second part of #179086.
In #179086, we added support for defining regions in Python-defined ops,
but its usefulness was quite limited because we still couldn’t mark an
op as a `Terminator` or `NoTerminator`. In this PR, we port the
`DynamicOpTrait` (introduced on the C++ side for `DynamicDialect` in
#177735) to Python, so we can dynamically attach traits to
Python-defined ops.
Commit: 65b4099219ce7bf172dac26b641d56eb38680bd7
https://github.com/llvm/llvm-project/commit/65b4099219ce7bf172dac26b641d56eb38680bd7
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx1250.mir
Log Message:
-----------
[AMDGPU] Fix instruction size for 64-bit literal constant operands (#180387)
`getLit64Encoding` uses a different approach to determine whether 64-bit
literal encoding is used, which caused a size mismatch between the
`MachineInstr` and the `MCInst`.
For `!isValid32BitLiteral`, it is effectively `!(isInt<32>(Val) ||
isUInt<32>(Val))`, which is `!isInt<32>(Val) && !isUInt<32>(Val)`, but
in `getLit64Encoding`, it is `!isInt<32>(Val) || !isUInt<32>(Val)`.
Commit: fbcfbd9d3a33d14430250ad056c7d726db41673a
https://github.com/llvm/llvm-project/commit/fbcfbd9d3a33d14430250ad056c7d726db41673a
Author: Jessica Clarke <jrtc27 at jrtc27.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M lld/ELF/Relocations.cpp
Log Message:
-----------
[NFC][ELF] Fix overzealous find/replace affecting comments
Commit a94060ca0c87 ("[ELF] Pass Ctx & to Relocations") swapped the
InputSectionBase &c argument for an InputSectionBase *sec member, and so
"c." was replaced with "sec->". However, this must have done in such a
way that "Local-Exec." was transformed to "Local-Exesec->" and
"RISCV::relocateAlloc." to "RISCV::relocateAllosec->", i.e. without the
use of something like clangd, and without appropriate word boundaries in
a regex.
Commit: 1026944313daa82e68094b446d208a24906f8af0
https://github.com/llvm/llvm-project/commit/1026944313daa82e68094b446d208a24906f8af0
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M libcxx/test/benchmarks/format/format_to.bench.cpp
M libcxx/test/benchmarks/format/format_to_n.bench.cpp
M libcxx/test/benchmarks/format/formatted_size.bench.cpp
Log Message:
-----------
[libc++] Reduce the number of runs on the format_to{,n} and formatted_size benchmarks (#179922)
Testing a bunch of sizes has relatively little value. This reduces the
number of benchmarks so we can run them on a regular basis. This saves
~8 minutes when running the benchmarks.
Commit: 77ccd853d0ec9a96f49c8017030b653ab82bcb45
https://github.com/llvm/llvm-project/commit/77ccd853d0ec9a96f49c8017030b653ab82bcb45
Author: hanbeom <kese111 at gmail.com>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M llvm/lib/Analysis/IVDescriptors.cpp
A llvm/test/Transforms/LoopVectorize/loop-legality-checks-remarks.ll
Log Message:
-----------
[IVDesc] Check loop-preheader for loop-legality when pass-remarks enabled (#166310)
When `-pass-remarks=loop-vectorize` is specified, the subsequent logic
is executed to display detailed debug messages even if no PreHeader
exists in the loop.
Therefore, an assert occurs when the `getLoopPreHeader()` function is
called. This commit resolves that issue.
Fixed: #165377
Commit: 3cd0bb7f67dca7307fc7b3956e9721da87ca32f6
https://github.com/llvm/llvm-project/commit/3cd0bb7f67dca7307fc7b3956e9721da87ca32f6
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/lib/AST/ByteCode/Context.cpp
M clang/test/AST/ByteCode/c.c
Log Message:
-----------
[clang][bytecode] Check evaluate{String,Strlen} for pointer type (#180524)
We can only use block pointers here.
Commit: 7de4eb97d9c07d44a1460cc30b6f26fbdf77416e
https://github.com/llvm/llvm-project/commit/7de4eb97d9c07d44a1460cc30b6f26fbdf77416e
Author: Christian Sigg <csigg at google.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Port fccbdcb.
Commit: 12ec215e8ab74510ddd6b43b8e7c0422fbc16cfb
https://github.com/llvm/llvm-project/commit/12ec215e8ab74510ddd6b43b8e7c0422fbc16cfb
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/include/llvm/IR/Value.h
Log Message:
-----------
[IR] Update docstring for stripAndAccumulateConstantOffset (#180365)
Make it clear that the returned object in the case where a variable
offset is found is the first value to introduce a non-constant offset,
not necessarily the actual underlying object.
Found while investigating #180361.
Commit: 2e2167309de5d21629c0f7c769ed027f6c670e86
https://github.com/llvm/llvm-project/commit/2e2167309de5d21629c0f7c769ed027f6c670e86
Author: ShashwathiNavada <shashwathinavada at gmail.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M flang/lib/Lower/OpenMP/OpenMP.cpp
A flang/test/Semantics/OpenMP/allocate_do.f90
A flang/test/Semantics/OpenMP/allocate_do1.f90
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[OpenMP][flang] Enabling support for Allocate clause in DO construct (#180172)
Fixes [#179425](https://github.com/llvm/llvm-project/issues/179425).
Allocate clause is allowed inside DO and parallel DO constructs as per
[13.6.2](https://www.openmp.org/wp-content/uploads/OpenMP-API-Specification-6-0.pdf)
but flang seemed to throw diagnostic against the same. This patch
enables initial support for allocate clause in DO construct.
Commit: 90691641e6419c285671f183628a0e16792df43c
https://github.com/llvm/llvm-project/commit/90691641e6419c285671f183628a0e16792df43c
Author: Vladislav Dzhidzhoev <vdzhidzhoev at accesssoftek.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
A clang/test/DebugInfo/CXX/ctor-homing-local-type.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/unittests/IR/IRBuilderTest.cpp
Log Message:
-----------
[llvm][DebugInfo] Avoid attaching retained nodes to unrelated subprograms in DIBuilder (#180294)
Fix a regression introduced by
https://github.com/llvm/llvm-project/pull/165032, where DIBuilder could
attach local metadata nodes to the wrong subprogram during finalization.
DIBuilder records freshly created local variables, labels, and types in
`DIBuilder::SubprogramTrackedNodes`, and later attaches them to their
parent subprogram's retainedNodes in `finalizeSubprogram()`.
However, a temporary local type created via
`createReplaceableCompositeType()` may later be replaced by a type with
a different scope.
DIBuilder does not currently verify that the scopes of the original and
replacement types match.
As a result, local types can be incorrectly attached to the
retainedNodes of an unrelated subprogram. This issue is observable in
clang with limited debug info mode (see
`clang/test/DebugInfo/CXX/ctor-homing-local-type.cpp`).
This patch updates `DIBuilder::finalizeSubprogram()` to verify that
tracked metadata nodes still belong to the subprogram being finalized,
and avoids adding nodes whose scopes no longer match to retainedNodes
field of an unrelated subprogram.
Commit: 94971b7c8ebd3107c9b72b47074e97144f0a5b7d
https://github.com/llvm/llvm-project/commit/94971b7c8ebd3107c9b72b47074e97144f0a5b7d
Author: Mikhail Gudim <mgudim at qti.qualcomm.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/include/llvm/CodeGen/Register.h
Log Message:
-----------
[CodeGen][NFC] Update a comment. (#180531)
Since a register can represent a negative frame index, remove
"non-negative" from the comment.
Commit: 84f4b1e52df736d4bd0bcf821c7fbe06f3534042
https://github.com/llvm/llvm-project/commit/84f4b1e52df736d4bd0bcf821c7fbe06f3534042
Author: Vishruth Thimmaiah <vishruththimmaiah at gmail.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/multiple-result-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/multiple-result-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/struct-return.ll
Log Message:
-----------
Reland "[LoopVectorize] Support vectorization of overflow intrinsics" (#180526)
Enables support for marking overflow intrinsics `uadd`, `sadd`, `usub`,
`ssub`, `umul` and `smul` as trivially vectorizable.
Fixes #174617
---
This patch is a reland of #174835.
Reverts #179819
Commit: ab2e10d80f94ae65fea253c52433b23a1050e28e
https://github.com/llvm/llvm-project/commit/ab2e10d80f94ae65fea253c52433b23a1050e28e
Author: Anshil Gandhi <95053726+gandhi56 at users.noreply.github.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.v2f16.mir
Log Message:
-----------
[AMDGPU] Add legalization rules for G_ATOMICRMW_FADD (#175257)
G_ATOMICRMW_FADD is supported on flat, global and local address spaces
for S32, S64 and V2S16 values.
Commit: 091972c3543c91ce9bed76d61b6581dc19bb582f
https://github.com/llvm/llvm-project/commit/091972c3543c91ce9bed76d61b6581dc19bb582f
Author: Nathan Gauër <brioche at google.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
A llvm/test/CodeGen/SPIRV/pointers/sgep-array.ll
A llvm/test/CodeGen/SPIRV/pointers/sgep-class.ll
A llvm/test/CodeGen/SPIRV/pointers/sgep-dynamic-index.ll
A llvm/test/CodeGen/SPIRV/pointers/sgep-nested-struct-array.ll
A llvm/test/CodeGen/SPIRV/pointers/sgep-runtime-array.ll
A llvm/test/CodeGen/SPIRV/pointers/sgep-struct.ll
A llvm/test/CodeGen/SPIRV/pointers/sgep-vector.ll
Log Message:
-----------
[SPIR-V] initial support for @llvm.structured.gep (#178668)
This commit adds initial support to lower the intrinsinc
`@llvm.structured.gep` into proper SPIR-V.
For now, the backend continues to support both GEP formats. We might
want to revisit this at some point for the logical part.
Commit: 0a740668a4b512ee29486950474c12fac625a164
https://github.com/llvm/llvm-project/commit/0a740668a4b512ee29486950474c12fac625a164
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
A llvm/test/Transforms/InstCombine/maximumnum.ll
A llvm/test/Transforms/InstCombine/minimumnum.ll
Log Message:
-----------
[InstCombine] Support minimumnum/maximumnum (#180529)
Support minimumnum/maximumnum intrinsics in various existing
minnum/maxnum/minimum/maximum folds.
The test coverage has been copied from minnum/maxnum.
Proofs: https://alive2.llvm.org/ce/z/YMlLwO
Proofs that time out: https://alive2.llvm.org/ce/z/dJN8wj
Commit: a911fc12ec1f280203e243810de2b8acafbca4b8
https://github.com/llvm/llvm-project/commit/a911fc12ec1f280203e243810de2b8acafbca4b8
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
Log Message:
-----------
[X86] Fold expand(splat,passthrough,mask) -> select(splat,passthrough,mask) (#180238)
If all elements of the expansion vector are already splatted in place then we can use a vselect directly
Commit: 47fb7cd732ffc666d2865e1a187db24f8e09ab25
https://github.com/llvm/llvm-project/commit/47fb7cd732ffc666d2865e1a187db24f8e09ab25
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn
Log Message:
-----------
[gn build] Port da0ad392ffc6
Commit: e6c73eb0c4c38fa18450c96154228e8ea73799be
https://github.com/llvm/llvm-project/commit/e6c73eb0c4c38fa18450c96154228e8ea73799be
Author: Hristo Hristov <hristo.goshev.hristov at gmail.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M libcxx/docs/CodingGuidelines.rst
Log Message:
-----------
[libc++][docs] Update `[[nodiscard]]` coding guidelines (#178384)
as requested in
https://github.com/llvm/llvm-project/pull/176936#pullrequestreview-3706775444
Clarifies when not to apply `[[nodiscard]]`.
https://libcxx.llvm.org/CodingGuidelines.html#apply-nodiscard-where-relevant
---------
Co-authored-by: Nikolas Klauser <nikolasklauser at berlin.de>
Co-authored-by: Hristo Hristov <zingam at outlook.com>
Commit: e6a72a1d42cdc605dd3c9bc3e0ee8add930b19f9
https://github.com/llvm/llvm-project/commit/e6a72a1d42cdc605dd3c9bc3e0ee8add930b19f9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/test/CodeGen/RISCV/rv32p.ll
Log Message:
-----------
[RISCV] Combine ADDD+WMULSU to WMACCSU (#180454)
Extend the existing combineADDDToWMACC DAG combine to also match
RISCVISD::WMULSU and produce RISCVISD::WMACCSU. This is similar to
how ADDD+UMUL_LOHI is combined to WMACCU and ADDD+SMUL_LOHI is
combined to WMACC.
This patch was generated by AI, but I reviewed it.
Commit: 7fcc12c3be0550bdcaa5305c557eee73fd719ff3
https://github.com/llvm/llvm-project/commit/7fcc12c3be0550bdcaa5305c557eee73fd719ff3
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M offload/test/lit.cfg
M offload/test/mapping/firstprivate_aligned.cpp
Log Message:
-----------
Reapply [Offload][lit] Link against SPIR-V DeviceRTL if present (#180231)
I'll merge this at the same time as some llvm-zorg changes that start
building the DeviceRTL.
We only see one new test passing because everything still fails because
of the issue described in
https://github.com/llvm/llvm-project/pull/178980
Once a fix for that issue is merged we will see many new passes.
Commit: 35efbc00bef4acec1d73c3d1789618f171f9afce
https://github.com/llvm/llvm-project/commit/35efbc00bef4acec1d73c3d1789618f171f9afce
Author: Leandro Lupori <leandro.lupori at linaro.org>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M flang/lib/Parser/prescan.cpp
A flang/test/Parser/OpenMP/cont-in-cond-comp.f
M flang/test/Parser/OpenMP/sentinels.f
M flang/test/Parser/continuation-in-conditional-compilation.f
Log Message:
-----------
[flang] Warn if conditional compilation statements begin with a continuation line (#179802)
In fixed source form, allow conditional compilation statements to begin
with a continuation line and emit a warning. This behavior is similar
to that of regular statements and -E mode.
Fixes #129457
Commit: d62bc3ae0ea289e586e706332a364fa2f1114778
https://github.com/llvm/llvm-project/commit/d62bc3ae0ea289e586e706332a364fa2f1114778
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Transforms/IPO/AlwaysInliner.cpp
M llvm/lib/Transforms/IPO/BarrierNoopPass.cpp
M llvm/lib/Transforms/IPO/DeadArgumentElimination.cpp
M llvm/lib/Transforms/IPO/GlobalDCE.cpp
M llvm/lib/Transforms/IPO/IPO.cpp
M llvm/lib/Transforms/IPO/LoopExtractor.cpp
M llvm/tools/llc/llc.cpp
Log Message:
-----------
[NFC][LLVM][IPO] Remove pass initialization from pass constructors (#180154)
Commit: 8bbdac9e52498e773283fba48e7eb8eec03ef14c
https://github.com/llvm/llvm-project/commit/8bbdac9e52498e773283fba48e7eb8eec03ef14c
Author: Ryan Mitchell <Ryan.Mitchell at amd.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/CodeGen/MIRParser/MILexer.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.h
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
A llvm/test/CodeGen/MIR/AMDGPU/instr-mmra-error.mir
A llvm/test/CodeGen/MIR/AMDGPU/instr-mmra.mir
Log Message:
-----------
[MIParser] - Add support for MMRAs (#180320)
Probably just forgotten in #78569
Commit: cc7292056683f592c33055bb6456d509201654ec
https://github.com/llvm/llvm-project/commit/cc7292056683f592c33055bb6456d509201654ec
Author: Sergei Druzhkov <serzhdruzhok at gmail.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M lldb/source/Plugins/InstrumentationRuntime/TSan/InstrumentationRuntimeTSan.cpp
M lldb/test/API/functionalities/tsan/thread_leak/TestTsanThreadLeak.py
M lldb/test/API/functionalities/tsan/thread_numbers/TestTsanThreadNumbers.py
Log Message:
-----------
[lldb] Fix TSan report on Linux (#179115)
Linux uses 0 for `RTLD_DEFAULT` opposite to macOS and BSD systems (they
use -2).
Commit: 0040bdf5322a0acca5e9c40e06d8031bf6d7d10d
https://github.com/llvm/llvm-project/commit/0040bdf5322a0acca5e9c40e06d8031bf6d7d10d
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.swap.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.swap.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.swap.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.swap.ll
Log Message:
-----------
AMDGPU/GlobalISel: Regbanklegalize rules for buffer atomic swap (#180265)
Commit: b6ee085068972a41f3b2735a9f7e3ca48eab0f00
https://github.com/llvm/llvm-project/commit/b6ee085068972a41f3b2735a9f7e3ca48eab0f00
Author: Tom Stellard <tstellar at redhat.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M .github/workflows/release-documentation.yml
M .github/workflows/release-tasks.yml
Log Message:
-----------
workflows/release-task: Use less privileged token for uploading release notes (#180299)
We were using one token for both pushing to the llvmbot fork and for
creating a pull request against the www-releases repository, since the
fork and the repository have different owners, we were using a classic
access token which has very coarse-grained permissions. By using two
separate tokens, we limit the permissions to just what we need to do the
task.
Also, at the same time run the release-documentation job in an
environment, so we can limit the accessiblity to these secrets.
Commit: 404f9e6c993cb26fff1888f943284f1f6e86adc0
https://github.com/llvm/llvm-project/commit/404f9e6c993cb26fff1888f943284f1f6e86adc0
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sffbh.ll
Log Message:
-----------
AMDGPU/GlobalISel: RegBankLegalize rules for amdgcn_sffbh (#180099)
Change test to use update_llc_test_checks.py and make `v_flbit` test
actually divergent.
Commit: 77cb6660781eccdd0856c77dda8d6bf49c350397
https://github.com/llvm/llvm-project/commit/77cb6660781eccdd0856c77dda8d6bf49c350397
Author: John Brawn <john.brawn at arm.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/test/CodeGen/AArch64/ldst-opt.mir
Log Message:
-----------
[AArch64] Add support for B and H loads/stores in LoadStoreOptimizer (#180535)
This means the load/store optimizer can generate pre and post increment
versions of these instructions.
Commit: a29f0dd09680fbf7c24aa182c87f51cf4b93e21d
https://github.com/llvm/llvm-project/commit/a29f0dd09680fbf7c24aa182c87f51cf4b93e21d
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M llvm/docs/CommandGuide/index.rst
A llvm/docs/CommandGuide/llubi.rst
M llvm/test/CMakeLists.txt
M llvm/test/lit.cfg.py
A llvm/test/tools/llubi/main.ll
A llvm/test/tools/llubi/main2.ll
A llvm/test/tools/llubi/poison.ll
A llvm/tools/llubi/CMakeLists.txt
A llvm/tools/llubi/lib/CMakeLists.txt
A llvm/tools/llubi/lib/Context.cpp
A llvm/tools/llubi/lib/Context.h
A llvm/tools/llubi/lib/Interpreter.cpp
A llvm/tools/llubi/lib/Value.cpp
A llvm/tools/llubi/lib/Value.h
A llvm/tools/llubi/llubi.cpp
Log Message:
-----------
[llubi] Add initial support for llubi (#180022)
This patch implements the initial support for upstreaming
[llubi](https://github.com/dtcxzyw/llvm-ub-aware-interpreter). It only
provides the minimal functionality to run a simple main function. I hope
we can focus on the interface design in this PR, rather than trivial
implementations for each instruction.
RFC link:
https://discourse.llvm.org/t/rfc-upstreaming-llvm-ub-aware-interpreter/89645
Excluding the driver `llubi.cpp`, this patch contains three components
for better decoupling:
+ `Value.h/cpp`: Value representation
+ `Context.h/cpp`: Global state management (e.g., memory) and
interpreter configuration
+ `Interpreter.cpp`: The main interpreter loop
Compared to the out-of-tree version, the major differences are listed
below:
+ The interpreter logic always returns the control to its caller, i.e.,
it never calls `exit/abort` when immediate UBs are triggered.
+ `EventHandler` provides an interface to dump the trace. It also allows
callers to inspect the actual value and verify the correctness of
analysis passes (e.g, KnownBits/SCEV).
+ The context is designed to be reentrant. That is, you can call
`runFunction` multiple times. But its usefulness remains in doubt due to
side effects made by previous calls.
+ `runFunction` handles function calls with a loop, instead of calling
itself recursively. This makes it no longer bounded by the stack depth.
+ Uninitialized memory is planned to be approximated by returning random
values each time an uninitialized byte is loaded.
Commit: 9ab3e3312ddd07eefd009eca4fe4d14a49e9f47e
https://github.com/llvm/llvm-project/commit/9ab3e3312ddd07eefd009eca4fe4d14a49e9f47e
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Transforms/IPO/AlwaysInliner.cpp
M llvm/lib/Transforms/IPO/BarrierNoopPass.cpp
M llvm/lib/Transforms/IPO/DeadArgumentElimination.cpp
M llvm/lib/Transforms/IPO/GlobalDCE.cpp
M llvm/lib/Transforms/IPO/IPO.cpp
M llvm/lib/Transforms/IPO/LoopExtractor.cpp
M llvm/tools/llc/llc.cpp
Log Message:
-----------
Revert "[NFC][LLVM][IPO] Remove pass initialization from pass constructors" (#180571)
Reverts llvm/llvm-project#180154
It seems to cause llc build failures, likely due to missing `ipo`
dependency.
Commit: d34d19d987f46c98c03dfdd059976469faadb402
https://github.com/llvm/llvm-project/commit/d34d19d987f46c98c03dfdd059976469faadb402
Author: Florian Mayer <fmayer at google.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/unittests/Analysis/FlowSensitive/UncheckedStatusOrAccessModelTestFixture.cpp
Log Message:
-----------
[NFC] [FlowSensitive] [StatusOr] Add tests for pointer receivers
Reviewers: jvoung
Reviewed By: jvoung
Pull Request: https://github.com/llvm/llvm-project/pull/180079
Commit: bc884a0feab579ef56cf1faa0a5b1df9023304e2
https://github.com/llvm/llvm-project/commit/bc884a0feab579ef56cf1faa0a5b1df9023304e2
Author: Florian Mayer <fmayer at google.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/unittests/Analysis/FlowSensitive/UncheckedStatusOrAccessModelTestFixture.cpp
Log Message:
-----------
[NFC] [FlowSensitive] [StatusOr] Add test for StatusOr nested in optional
Reviewers: jvoung
Reviewed By: jvoung
Pull Request: https://github.com/llvm/llvm-project/pull/180082
Commit: 839676bef18649adacb3de8b44d4f596aaa0da58
https://github.com/llvm/llvm-project/commit/839676bef18649adacb3de8b44d4f596aaa0da58
Author: Jake Egan <Jake.egan at ibm.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M compiler-rt/lib/asan/asan_allocator.cpp
M compiler-rt/lib/asan/asan_allocator.h
M compiler-rt/lib/asan/asan_malloc_linux.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_allocator.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_allocator_dlsym.h
M compiler-rt/lib/sanitizer_common/sanitizer_allocator_internal.h
A compiler-rt/test/asan/TestCases/AIX/vec_malloc_calloc.cpp
Log Message:
-----------
[asan][AIX] Add vec_malloc and vec_calloc interceptors (#175584)
On AIX, when both the `__VEC__` and `_ALL_SOURCE` macros are defined
(they are defined by default), the malloc and calloc system calls are
mapped to vec_malloc and vec_calloc respectively, so we need the
following vec_malloc and vec_calloc interceptors.
Issue: #138916
Commit: f7e2e4d2175e4517b304bd40caa5c82701b4c013
https://github.com/llvm/llvm-project/commit/f7e2e4d2175e4517b304bd40caa5c82701b4c013
Author: Florian Mayer <fmayer at google.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/unittests/Analysis/FlowSensitive/UncheckedStatusOrAccessModelTestFixture.cpp
Log Message:
-----------
[NFC] [FlowSensitive] [StatusOr] Add test reassigning variable in loop
Reviewers: jvoung
Reviewed By: jvoung
Pull Request: https://github.com/llvm/llvm-project/pull/180091
Commit: 352932c1b4950cff324e4bdb41e89b9cf3863797
https://github.com/llvm/llvm-project/commit/352932c1b4950cff324e4bdb41e89b9cf3863797
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M lldb/include/lldb/Host/windows/ProcessLauncherWindows.h
M lldb/source/Host/windows/ProcessLauncherWindows.cpp
Log Message:
-----------
[NFC][lldb][windows] extract the UpdateProcThreadAttribute logic (#180565)
This NFC patch extracts the `UpdateProcThreadAttribute` logic to a
dedicated method be able to reuse it in
https://github.com/llvm/llvm-project/pull/180561.
Commit: 1bfa71743b0803e00a1aad15722cc78771453481
https://github.com/llvm/llvm-project/commit/1bfa71743b0803e00a1aad15722cc78771453481
Author: Koakuma <koachan at protonmail.com>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M llvm/lib/Target/Sparc/CMakeLists.txt
M llvm/lib/Target/Sparc/SparcTargetMachine.cpp
M llvm/lib/Target/Sparc/SparcTargetMachine.h
A llvm/lib/Target/Sparc/SparcTargetTransformInfo.cpp
A llvm/lib/Target/Sparc/SparcTargetTransformInfo.h
A llvm/test/Transforms/LoopIdiom/Sparc/lit.local.cfg
A llvm/test/Transforms/LoopIdiom/Sparc/popcnt.ll
Log Message:
-----------
[SPARC] Add TTI implementation for getPopcntSupport (#178843)
This is to inform the middle-end transform passes about the capabilities
of the codegen backend.
This should solve the issue where popcount loops not gets converted
properly to `popc`, even if it's available
(https://github.com/llvm/llvm-project/issues/171969).
Commit: cd47ae9f8ff9afa46209806e94bfadb0056049c5
https://github.com/llvm/llvm-project/commit/cd47ae9f8ff9afa46209806e94bfadb0056049c5
Author: Marina Taylor <marina_taylor at apple.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M compiler-rt/test/profile/instrprof-binary-correlate.c
M llvm/include/llvm/ProfileData/InstrProfCorrelator.h
M llvm/lib/ProfileData/InstrProfCorrelator.cpp
Log Message:
-----------
[Profile] Enable binary profile correlation for Mach-O binaries (#179937)
The existing ELF/COFF correlation code mostly "just works" on Mach-O
files, with one gotcha: on disk, the pointers in `__llvm_covdata` are
stored in an encoded format due to dyld fixup chains. (In memory, they
would normally be fixed up at load time in a running binary, but the
correlator only looks at the on-disk values.)
LLVM's Mach-O reader knows how to decode the format, so this patch walks
the fixup table to create a set of mappings that the correlator can use
to resolve the values.
rdar://168259786
Commit: be711a08b3f4fb8360cb660d6ab2a6816cb4de7d
https://github.com/llvm/llvm-project/commit/be711a08b3f4fb8360cb660d6ab2a6816cb4de7d
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M lldb/source/Host/windows/ProcessLauncherWindows.cpp
Log Message:
-----------
[lldb][windows] remove unneeded DeleteProcThreadAttributeList call (#180579)
Remove an unneeded call to `DeleteProcThreadAttributeList`, which is
already done in the `ProcThreadAttributeList` destructor.
Commit: 1d5884d7cffbee85b695970ee64d3965729f5a74
https://github.com/llvm/llvm-project/commit/1d5884d7cffbee85b695970ee64d3965729f5a74
Author: Ebuka Ezike <yerimyah1 at gmail.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M lldb/test/API/tools/lldb-dap/breakpoint-events/Makefile
M lldb/test/API/tools/lldb-dap/breakpoint-events/TestDAP_breakpointEvents.py
M lldb/test/API/tools/lldb-dap/breakpoint-events/foo.cpp
Log Message:
-----------
[lldb-dap] Fix the breakpoint events test. (#180518)
Previously the test was written in a way that may be flaky, fixed with
the following changes.
- The breakpoint are placed on functions and set during the
configuration stage of the protocol.
- Add the rpath to the test binary.
- Check we also hit the breakpoint we set directly using lldb.
Commit: 48f53422fe7f627fcdace90bd7c3c5ee056bc0a6
https://github.com/llvm/llvm-project/commit/48f53422fe7f627fcdace90bd7c3c5ee056bc0a6
Author: Christian Sigg <csigg at google.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/build_defs.bzl
Log Message:
-----------
[bazel] Slight polish after ef68a53.
Commit: 80677dc5e00c16e55dc29fce93867a77467b25ea
https://github.com/llvm/llvm-project/commit/80677dc5e00c16e55dc29fce93867a77467b25ea
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
A clang/test/CodeGen/AArch64/neon/intrinsics.c
M clang/test/lit.cfg.py
Log Message:
-----------
[CIR][NEON] Add lowering support for `vceqzd_s64` (#179779)
Rather than creating a dedicated ClangIR test file, the original test file for
this intrinsic is effectively reused:
* clang/test/CodeGen/AArch64/neon-intrinsics.c
“Effectively” meaning that the corresponding test is moved (rather than
literally reused) to a new file within the original AArch64 builtins test
directory:
* clang/test/CodeGen/AArch64/neon/intrinsics.c
This is necessary to avoid lowering unsupported examples from intrinsics.c with
`-fclangir`. The new file will eventually replace the original one once all
builtins from it can be lowered via ClangIR.
To facilitate test re-use, new LIT "feature" is added so that CIR tests can be
run conditionally, e.g. the following will only run when `CLANG_ENABLE_CIR` is
set:
```C
// RUN: %if cir %{%clang_cc1 ... %}
```
This sort of substitutions are documented in [2].
REFERENCES:
[1] https://developer.arm.com/architectures/instruction-sets/intrinsics/#f:@navigationhierarchiessimdisa=[Neon]&q=vceqzd_s64
[2] https://llvm.org/docs/TestingGuide.html#substitutions
Commit: 74c8891c9afe4bd836ab385f4489b1ede5c28a0e
https://github.com/llvm/llvm-project/commit/74c8891c9afe4bd836ab385f4489b1ede5c28a0e
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M lldb/source/Plugins/InstrumentationRuntime/TSan/InstrumentationRuntimeTSan.cpp
M lldb/test/API/functionalities/tsan/thread_leak/TestTsanThreadLeak.py
M lldb/test/API/functionalities/tsan/thread_numbers/TestTsanThreadNumbers.py
Log Message:
-----------
Revert "[lldb] Fix TSan report on Linux (#179115)"
This reverts commit cc7292056683f592c33055bb6456d509201654ec.
This patch causes two tests to unexpectedly pass:
1. lldb-api.functionalities/tsan/cpp_global_location/TestTsanCPPGlobalLocation.py
2. lldb-api.functionalities/tsan/global_location/TestTsanGlobalLocation.py
Reverting to fix premerge. Not fixing forward so someone who is familiar
with LLDB can take a look and make sure those tests now should pass.
Commit: 20d3aa944fb5cdbeb7e855fcd0800abd6d4a7842
https://github.com/llvm/llvm-project/commit/20d3aa944fb5cdbeb7e855fcd0800abd6d4a7842
Author: Jessica Clarke <jrtc27 at jrtc27.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M lld/ELF/Arch/X86_64.cpp
M lld/ELF/Target.h
M lld/ELF/Writer.cpp
Log Message:
-----------
[NFC][ELF] Remove redundant and unused file argument from deleteFallThruJmpInsn (#180540)
This was added in 94317878d826 ("LLD Support for Basic Block Sections")
and was only ever used for getRelocTargetVA. It was always redundant
even back then, as it was always the same as is.file, and so passing it
separately made it confusing and less obvious which file it was
referring to, but 2b5cb1bf628f ("[ELF] getRelocTargetVA: pass Ctx and
Relocation. NFC") removed that one use so it is now completely unused.
Remove it, and if anyone ever finds a need for it, they can just use
is.file like should have been done in the first place.
Commit: d1dc843c18a670ec4fce747b92401faaf95b01ba
https://github.com/llvm/llvm-project/commit/d1dc843c18a670ec4fce747b92401faaf95b01ba
Author: Gheorghe-Teodor Bercea <doru.bercea at amd.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/test/CodeGen/AMDGPU/loop-vector-sink.ll
M llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll
Log Message:
-----------
[AMDGPU] Enable sinking of free vector ops that will be folded into their uses (#162580)
Sinking ShuffleVectors / ExtractElement / InsertElement into user blocks
can help enable SDAG combines by providing visibility to the values
instead of emitting CopyTo/FromRegs. The sink IR pass disables sinking
into loops, so this PR extends the CodeGenPrepare target hook
shouldSinkOperands.
Co-authored-by: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Commit: afd53ae84b49a2644f0e76d1aa9001cf6e17e528
https://github.com/llvm/llvm-project/commit/afd53ae84b49a2644f0e76d1aa9001cf6e17e528
Author: Christian Sigg <csigg at google.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Fix layering checks
Commit: 61c24328fcc5a59bec9b98a9471cfb2b87dfe639
https://github.com/llvm/llvm-project/commit/61c24328fcc5a59bec9b98a9471cfb2b87dfe639
Author: Christian Sigg <csigg at google.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Fix llvm reference
Commit: 754fc78d713285855e2a45225ec2b8b4f51e7ff9
https://github.com/llvm/llvm-project/commit/754fc78d713285855e2a45225ec2b8b4f51e7ff9
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Transforms/IPO/ForceFunctionAttrs.cpp
M llvm/test/Transforms/ForcedFunctionAttrs/forced.ll
Log Message:
-----------
[ForceFunctionAttrs] Fix handling of `alwaysinline` and `noinline` attributes. (#180026)
Address
https://github.com/llvm/llvm-project/pull/152365#issuecomment-3198921342
Commit: 87d73f74713039cacf9d174a9d74de0db8eccb8b
https://github.com/llvm/llvm-project/commit/87d73f74713039cacf9d174a9d74de0db8eccb8b
Author: Brian Cain <brian.cain at oss.qualcomm.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
A llvm/test/MC/Hexagon/newvalue_jump_ext_imm.s
Log Message:
-----------
[Hexagon] Fix encoding of packets with fixups followed by alignment (#179168)
When a packet containing extended immediates and new-value compare-jump
instructions with fixups was followed by a .p2align directive, we would
incorrectly add nops to the packet. After reshuffling, the fixup offsets
would become invalid, causing corrupted encodings.
Fixes round-trip assembly for patterns like:
{
r18 = ##65536
if (!cmp.gtu(r1,r18.new)) jump:t .L1
}
.p2align 4
Commit: 1d1a34ff3e57ae55fe82acb91b1391a04162556c
https://github.com/llvm/llvm-project/commit/1d1a34ff3e57ae55fe82acb91b1391a04162556c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Log Message:
-----------
[TargetLowering] Avoid creating a VTList until we know we need it. NFC (#180599)
Since I was in the area, also use SDValue::getValue() to shorten getting
result 1.
Commit: 55d75d2a1fc10a2975795a4656273b464c6ba3be
https://github.com/llvm/llvm-project/commit/55d75d2a1fc10a2975795a4656273b464c6ba3be
Author: Alex Langford <alangford at apple.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M lldb/source/Commands/Options.td
Log Message:
-----------
[lldb][NFC] Fix typo in memory read help text (#180301)
rdar://168081328
Commit: 62d018b87a161bb2797c1ed03a482ffcdc8b162c
https://github.com/llvm/llvm-project/commit/62d018b87a161bb2797c1ed03a482ffcdc8b162c
Author: Brian Cain <brian.cain at oss.qualcomm.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M lld/ELF/Arch/Hexagon.cpp
M lld/test/ELF/hexagon-tls-ie.s
Log Message:
-----------
[lld][Hexagon] Fix R_HEX_TPREL_11_X relocation on duplex instructions (#179860)
findMaskR11() was missing handling for duplex instructions. This caused
incorrect encoding when R_HEX_TPREL_11_X relocations were applied to
duplex instructions with large TLS offsets.
For duplex instructions, the immediate bits are located at positions
20-25 (mask 0x03f00000), not in the standard positions used for
non-duplex instructions.
This fix adds the isDuplex() check to findMaskR11() to return the
correct mask for duplex instruction encodings.
Commit: 2e34fecf02962e4c8477ca88cc5ac9386a0f76bb
https://github.com/llvm/llvm-project/commit/2e34fecf02962e4c8477ca88cc5ac9386a0f76bb
Author: Rahul Joshi <rjoshi at nvidia.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Transforms/IPO/AlwaysInliner.cpp
M llvm/lib/Transforms/IPO/BarrierNoopPass.cpp
M llvm/lib/Transforms/IPO/DeadArgumentElimination.cpp
M llvm/lib/Transforms/IPO/GlobalDCE.cpp
M llvm/lib/Transforms/IPO/IPO.cpp
M llvm/lib/Transforms/IPO/LoopExtractor.cpp
M llvm/tools/llc/CMakeLists.txt
M llvm/tools/llc/llc.cpp
Log Message:
-----------
[NFC][LLVM][IPO] Remove pass initialization from pass constructors (#180584)
Commit: 8ee6c63f24a1fb7fb0537fee80456d329306af45
https://github.com/llvm/llvm-project/commit/8ee6c63f24a1fb7fb0537fee80456d329306af45
Author: Robert Imschweiler <robert.imschweiler at amd.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M flang-rt/lib/runtime/CMakeLists.txt
Log Message:
-----------
[offload][flang-rt] Fix NVPTX runtime build (#180530)
During the check for availability of `strerror_r`, the host include file is used. This doesn't matter for AMDGPU since it actually performs the link step during `check_cxx_symbol_exists`. But for NVPTX, due to `-c`, it doesn't link and then incorrectly assumes that the symbol exists.
For now, removing `io-error.cpp` from the list of GPU sources is the most sensible option since it's unused.
Commit: 8418c4196d5c5a60003b0f19257dfef2ffbe008e
https://github.com/llvm/llvm-project/commit/8418c4196d5c5a60003b0f19257dfef2ffbe008e
Author: GkvJwa <gkvjwa at gmail.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/lib/CodeGen/CGDecl.cpp
M clang/test/CodeGenCXX/exceptions-seh.cpp
Log Message:
-----------
[WinEH] Check object unwinding in seh block only when -eha is used (#180108)
After this [PR](https://github.com/llvm/llvm-project/pull/172287), build
errors may occur even when `/EHa` is not enabled(like use `/EHsc`).
While MSVC performs similar checks whenever exceptions are enabled, LLVM
is more prone to generating invalid code where SEH fails to function
correctly when asyn exceptions(`/EHa`) are not used. Valid SEH code
generation is typically only ensured when `/EHa` are enabled. Therefore,
this patch is designed to perform the check only when `/EHa` is used.
Of course, on Windows, if LLVM doesn't use `/EHa` but uses `/EHsc` or
`/EHs` instead the code within the `__except` block may behave
unexpectedly, it unlike msvc. This is consistent with previous LLVM
versions.
Commit: 4136d3f24896cd666e32ed97ec4191344d5fe898
https://github.com/llvm/llvm-project/commit/4136d3f24896cd666e32ed97ec4191344d5fe898
Author: Alexey Merzlyakov <60094858+AlexeyMerzlyakov at users.noreply.github.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
A llvm/test/CodeGen/AArch64/inline-asm-nop-reg.ll
Log Message:
-----------
[AArch64] Inline asm v0-v31 are scalar when having less than 64-bit capacity (#169930)
If 32-bit (or less) "v0" registers coming from inline asm are treated as
vector ones, codegen might produce incorrect vector<->scalar
conversions. This causes types mismatch assertion failures later during
compile-time. The fix treats 32-bit or less v0-v31 AArch64 registers as
scalar, along with 64-bit ones.
Fixes #153442
Commit: 470c5ca81c2a86715dbb68d6140070d08d0fdf4b
https://github.com/llvm/llvm-project/commit/470c5ca81c2a86715dbb68d6140070d08d0fdf4b
Author: Jianhui Li <jian.hui.li at intel.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
Log Message:
-----------
[MLIR][XeGPU] Fix insert_strided_slice op in subgroup distribution (#180604)
The PR modifies the subgroup distribution pass to only sink
insert_strided_slice operation if it becomes the last op before yield.
It avoids sinking insert_strided_slice multiple times and cause
potential issue in worst case.
Commit: cba0e6ad8e888c517133b4128fe3f767d2f86a63
https://github.com/llvm/llvm-project/commit/cba0e6ad8e888c517133b4128fe3f767d2f86a63
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUTypes.td
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/test/Conversion/AMDGPUToROCDL/gfx1250.mlir
Log Message:
-----------
[mlir][AMDGPU] Change width of LDS barrier count (#180554)
Whoops, turns out I was off by 1 on how many bits are in the counts and
phases ind these new LDS barriers. This commit fixes this.
Co-authored-by: Claude Opus 4.5 <noreply at anthropic.com>
Commit: fbed673f5238f219e43af0f88802d5422a77218b
https://github.com/llvm/llvm-project/commit/fbed673f5238f219e43af0f88802d5422a77218b
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td
M mlir/test/Conversion/AMDGPUToROCDL/gfx1250.mlir
M mlir/test/Dialect/AMDGPU/invalid.mlir
M mlir/test/Dialect/AMDGPU/ops.mlir
Log Message:
-----------
[mlir][amdgpu] Update TDM ops to use the new barrier type, improve docs (#180572)
Now that we have an AMDGPU dialect type for the in-LDS barriers that the
tensor data mover can automatically visit, update the definition of the
tensor descriptor operations to use said types and document the behavior
of the barrier.
Commit: 37c3241d23950d73f329cb5bef838d3c396b2c64
https://github.com/llvm/llvm-project/commit/37c3241d23950d73f329cb5bef838d3c396b2c64
Author: HighW4y2H3ll <zhenghaohuu at gmail.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/include/llvm/ProfileData/SampleProf.h
Log Message:
-----------
[SPGO] Use std::hash instead of MD5 to avoid run time regression in llvm-profgen (#180581)
https://github.com/llvm/llvm-project/pull/66164 changed the hashing in
`SampleContextFrame` from `std::hash` to `MD5` in a very hot function
(ContextTrieNode::getOrCrateChildContext()) in llvm-profgen. This
creates over 2x run time regression when running llvm-profgen with
csspgo preinliner enabled, since the MD5 computation is tripled
comparing to the Murmur hash in the std library. An llvm-profgen run
time comparison shows follows:
```
$ time llvm-profgen -binary $BINARY--perfscript $SAMPLES --populate-profile-symbol-list --show-density --output=XXX
# MD5 hash
real 105m31.644s
user 104m51.334s
sys 0m35.033s
# std::hash
real 46m0.340s
user 45m17.998s
sys 0m38.420s
```
Can confirm that this patch recovers the run time regression in
llvm-profgen, and the perf testing in our internal services shows
neutral.
Commit: 8f37bf6b10e11b81032a16be711c58dda9fa0d8e
https://github.com/llvm/llvm-project/commit/8f37bf6b10e11b81032a16be711c58dda9fa0d8e
Author: Leandro Lupori <leandro.lupori at linaro.org>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/test/Sema/format-strings.c
Log Message:
-----------
[Sema] Fix format-strings test on AIX (#180566)
Simplify the conditional compilation and skip the problematic warnings
only on 32-bit Arm.
Commit: 0e7ddf395a12e0201ed0ca7131439c2fd355a72a
https://github.com/llvm/llvm-project/commit/0e7ddf395a12e0201ed0ca7131439c2fd355a72a
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M flang/lib/Semantics/resolve-directives.cpp
A flang/test/Semantics/OpenMP/local-variables-1.f90
A flang/test/Semantics/OpenMP/local-variables-2.f90
R flang/test/Semantics/OpenMP/local-variables.f90
Log Message:
-----------
[flang][OpenMP] Improve locality check when determining DSA (#180583)
Follow-up to https://github.com/llvm/llvm-project/pull/178739.
The locality check assumed that immediately after the initial symbol
resolution (i.e. prior to the OpenMP code in resolve-directives.cpp),
the scope that owns a given symbol is the scope which owns the symbol's
storage. Turns out that this isn't necessarily true as illustrated by
the included testcase, roughly something like:
```
program main
integer :: j ! host j (storage-owning)
contains
subroutine f
!$omp parallel ! scope that owns j, but j is host-associated
do j = ...
end do
!$omp end parallel
end
end program
```
In such cases, the locality should be checked for the symbol that owns
storage, i.e. a clone of the symbol that is has been privatized or a
symbol that is not host- or use-associated. This is similar to obtaning
the ultimate symbol (i.e. from the end of association chain), except the
chain traversal would stop at a privatized symbol, potentially before
reaching the end.
This fixes a few regressions in the Fujitsu test suite:
Fujitsu/Fortran/0160/Fujitsu-Fortran-0160_0000.test
Fujitsu/Fortran/0160/Fujitsu-Fortran-0160_0012.test
Fujitsu/Fortran/0160/Fujitsu-Fortran-0160_0013.test
Fujitsu/Fortran/0660/Fujitsu-Fortran-0660_0096.test
Fujitsu/Fortran/0660/Fujitsu-Fortran-0660_0097.test
Fujitsu/Fortran/1052/Fujitsu-Fortran-1052_0108.test
Fujitsu/Fortran/1052/Fujitsu-Fortran-1052_0112.test
Commit: 009cad89726673464bc5a2255e072c3b4825f6db
https://github.com/llvm/llvm-project/commit/009cad89726673464bc5a2255e072c3b4825f6db
Author: Rohan Jacob-Rao <rohanjr at google.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/docs/SafeBuffers.rst
Log Message:
-----------
[NFC][Clang][SafeBuffers] Correct naming (sz -> size). (#180629)
Commit: f0ca8fa685c34e8abfd5d9b071f74795b6ae33a6
https://github.com/llvm/llvm-project/commit/f0ca8fa685c34e8abfd5d9b071f74795b6ae33a6
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M .ci/compute_projects.py
M .ci/compute_projects_test.py
Log Message:
-----------
[CI] Add compiler-rt to LLDB runtime dependencies (#180590)
Some LLDB tests will only run if compiler-rt is built. This includes at
least two tsan tests that passed in a PR (#179115) but then failed on
other PRs that included compiler-rt in the build.
Commit: d1ec04dfd40b4ccfaddb897ddc9599ed35f2b563
https://github.com/llvm/llvm-project/commit/d1ec04dfd40b4ccfaddb897ddc9599ed35f2b563
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll
M llvm/test/Transforms/LoopVectorize/outer-loop-inner-latch-successors.ll
M llvm/test/Transforms/LoopVectorize/outer-loop-wide-phis.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_test2.ll
M llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
M llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
Log Message:
-----------
[VPlan] Simplify single-entry VPWidenPHIRecipe.
Include VPWidenPHIRecipe in phi simplification if there's a single
incoming value.
Commit: e624d5088d57eff4ec0fd1e8c3122541b81e1aa0
https://github.com/llvm/llvm-project/commit/e624d5088d57eff4ec0fd1e8c3122541b81e1aa0
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M .github/workflows/release-tasks.yml
Log Message:
-----------
[Github] Add runs-on to release-tasks.yml
This was failing validation against main and sending everyone emails.
Try adding the fix that was suggested in the workflow run.
Commit: c1059b209aa81bdf52b596b320a10077c0cddeb4
https://github.com/llvm/llvm-project/commit/c1059b209aa81bdf52b596b320a10077c0cddeb4
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M .github/workflows/release-documentation.yml
M .github/workflows/release-tasks.yml
Log Message:
-----------
Revert "workflows/release-task: Use less privileged token for uploading release notes (#180299)"
This reverts commit b6ee085068972a41f3b2735a9f7e3ca48eab0f00.
This reverts commit e624d5088d57eff4ec0fd1e8c3122541b81e1aa0.
This was causing failures like the following:
https://github.com/llvm/llvm-project/actions/runs/21842945533. The
follow up fix is also reverted as it did not actually fix the issue.
Commit: e1d2ff6caf8c1fef15561fbcc275aa93fec4c115
https://github.com/llvm/llvm-project/commit/e1d2ff6caf8c1fef15561fbcc275aa93fec4c115
Author: Steven Perron <stevenperron at google.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/test/CodeGen/SPIRV/hlsl-resources/Sample.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/Sample1D.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/Sample3D.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SampleBias.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SampleCmp.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SampleCmpLevelZero.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SampleCube.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SampleErrors.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SampleErrorsDebug.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SampleGrad.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SampleLevel.ll
Log Message:
-----------
[SPIRV] Implement lowering for HLSL Texture2D sampling intrinsics (#179312)
This patch implements the SPIR-V lowering for the following HLSL
intrinsics:
- SampleBias
- SampleGrad
- SampleLevel
- SampleCmp
- SampleCmpLevelZero
It defines the required LLVM intrinsics in 'IntrinsicsDirectX.td' and
'IntrinsicsSPIRV.td'.
It updates 'SPIRVInstructionSelector.cpp' to handle the new intrinsics
and
generates the correct 'OpImageSample*' instructions with the required
operands
(Bias, Grad, Lod, ConstOffset, MinLod, etc.).
CodeGen tests are added to verify the implementation for images with
dimension 1D, 2D, 3D, and Cube.
Assisted-by: Gemini
Commit: a9ea1cfe6ebf63fa523803d9fb7efc09148731bb
https://github.com/llvm/llvm-project/commit/a9ea1cfe6ebf63fa523803d9fb7efc09148731bb
Author: Sam Clegg <sbc at chromium.org>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M lld/test/wasm/data-layout.s
M lld/test/wasm/export-all.s
M lld/test/wasm/mutable-global-exports.s
M lld/wasm/Config.h
M lld/wasm/Driver.cpp
M lld/wasm/Writer.cpp
Log Message:
-----------
[lld][WebAssembly] Add new __rodata_start/__rodata_end symbols (#172102)
This is similar to etext/_etext in the ELF linker. Its useful in
emscripten to know where the RO data data ends and the data begins (even
though the Wasm format itself has no concept of RO data).
See
https://github.com/emscripten-core/emscripten/discussions/25939#discussioncomment-15243731
Commit: 815cf3bf14836031c5c8ad5d3cd9be8720b64981
https://github.com/llvm/llvm-project/commit/815cf3bf14836031c5c8ad5d3cd9be8720b64981
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/include/clang/Lex/PPCallbacks.h
M clang/lib/Frontend/CompilerInstance.cpp
M clang/unittests/Frontend/CompilerInstanceTest.cpp
Log Message:
-----------
[clang][modules] Add single-module-parse-mode callback (#179714)
This PR adds new preprocessor callback that's invoked whenever the
single-module-parse-mode skips over a module import. This will be used
later on from the dependency scanner.
Commit: d69ccf3b34e7ca8fa42e4c078f026b6e898e2c90
https://github.com/llvm/llvm-project/commit/d69ccf3b34e7ca8fa42e4c078f026b6e898e2c90
Author: Ryan Buchner <rbuchner at qti.qualcomm.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-merge.ll
Log Message:
-----------
[RISCV] Combine shuffle of shuffles to a single shuffle (#178095)
Compressing to a single shuffle doesn't remove any information and the backend can better apply specific optimizations to a single shuffle.
Addresses #176218.
---------
Co-authored-by: Luke Lau <luke_lau at igalia.com>
Commit: bf91c0969b55e40e75ed93a74a5672d95262ba79
https://github.com/llvm/llvm-project/commit/bf91c0969b55e40e75ed93a74a5672d95262ba79
Author: Jessica Clarke <jrtc27 at jrtc27.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M libcxx/utils/ci/BOT_OWNERS.txt
Log Message:
-----------
[libc++] Add myself as a FreeBSD point of contact
Commit: ccd93180e0f8067cd43551adaa4296b64ca43992
https://github.com/llvm/llvm-project/commit/ccd93180e0f8067cd43551adaa4296b64ca43992
Author: Jhalak Patel <jhalakpatel at outlook.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M mlir/include/mlir/Dialect/Utils/StaticValueUtils.h
M mlir/lib/Dialect/Utils/StaticValueUtils.cpp
M mlir/test/Dialect/SCF/trip_count.mlir
Log Message:
-----------
[MLIR][Utils] Fix overflow in constantTripCount for narrow types (#179985)
Extend operands when computing ub - lb to avoid overflow in signed
arithmetic. E.g., i8: ub=127, lb=-128 yields 255, which overflows
without extension.
Commit: 2b9a1aee5aa1c032e030cdeaea3e912275f3b819
https://github.com/llvm/llvm-project/commit/2b9a1aee5aa1c032e030cdeaea3e912275f3b819
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-with-invariant-stores.ll
M llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll
Log Message:
-----------
[LV] Add additional tests for reductions with intermediate stores. (NFC)
Adds missing test coverage for reductions with intermediate stores,
including partial reductions with intermediate stores, as well as
chained min/max reductions with intermediate stores.
Commit: d53272fad40a4602609a74a3b4da1519bce008bf
https://github.com/llvm/llvm-project/commit/d53272fad40a4602609a74a3b4da1519bce008bf
Author: Prabhu Rajasekaran <prabhukr at google.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M libc/config/baremetal/config.json
M libc/src/__support/str_to_float.h
Log Message:
-----------
[libc] Disable Clinger fast path for baremetal (#180598)
Clinger fast path bloats baremetal targets which are constrained in
binary size. Disabling it for baremetal libc builds.
Commit: 5d57c40043be8b1cb73466d3f53193025f26d717
https://github.com/llvm/llvm-project/commit/5d57c40043be8b1cb73466d3f53193025f26d717
Author: David Zbarsky <dzbarsky at gmail.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/driver.bzl
Log Message:
-----------
[bazel] Fix multicall tool invocation disambiguation (#180607)
The code seems to have considered the potential problem but did not
quite succeed in solving it ;)
Commit: 06cffa5ee37749b758b4c306f4c2c7e70f6ef962
https://github.com/llvm/llvm-project/commit/06cffa5ee37749b758b4c306f4c2c7e70f6ef962
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
M llvm/test/Transforms/LoopVectorize/vplan-unused-interleave-group.ll
M llvm/test/Transforms/LoopVectorize/vplan-widen-struct-return.ll
Log Message:
-----------
[VPlan] Auto-generate CHECKs in some VPlan printing tests.
Use new UTC support to re-generate check lines.
Commit: 5339ad943a5dafd4d7df29bafb50511947a23a6f
https://github.com/llvm/llvm-project/commit/5339ad943a5dafd4d7df29bafb50511947a23a6f
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/test/MC/RISCV/rv64p-valid.s
Log Message:
-----------
[RISCV] Add missing instruction tests to rv64p-valid.s. NFC (#180316)
An AI told me these were missing and helped me add them.
Commit: 0c94a1814f41495aef10735a5af2e10aa8d6affe
https://github.com/llvm/llvm-project/commit/0c94a1814f41495aef10735a5af2e10aa8d6affe
Author: HighW4y2H3ll <zhenghaohuu at gmail.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[Bazel] NFC refactor out redundant is_x86_64_non_windows config (#180296)
The logic of `is_x86_64_non_windows` looks unnecessarily complicated and
is only used at one site... clean up the unused targets and refactor
x86_64 BLAKE3 asm sources into a separate filegroup. And then
`is_x86_64_non_windows` can be put inside a default condition.
Commit: 68d4175cc15ecea2be8b778066824dc5a90fb1a3
https://github.com/llvm/llvm-project/commit/68d4175cc15ecea2be8b778066824dc5a90fb1a3
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/find-last-sink-based-iv-expr.ll
Log Message:
-----------
[LV] Add FindLast tests where IV-based expression could be sunk. (NFC)
Add set of FindLast tests where the selected expression is based on an
IV and could be sunk.
Commit: 853a39043e009cb35c6189818f883470742de9d7
https://github.com/llvm/llvm-project/commit/853a39043e009cb35c6189818f883470742de9d7
Author: Daniel Paoliello <danpao at microsoft.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64CallingConvention.td
M llvm/test/CodeGen/AArch64/cfguard-checks.ll
Log Message:
-----------
[win][aarch64] The Windows Control Flow Guard Check function also preserves X15 (#179738)
The target function to be checked by the Control Flow Guard Check
function is stored in `X15` on AArch64. This register is guaranteed to
be preserved by that function (on success), thus after it returns `X15`
can be used to branch to the target function instead of having to load
it from another register or the stack.
Commit: 19705bd7fc60e9d6756ea375714d687c138949ea
https://github.com/llvm/llvm-project/commit/19705bd7fc60e9d6756ea375714d687c138949ea
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/apint-constant.ll
Log Message:
-----------
[SPIR-V] Emit ceil(Bitwidth / 32) words during OpConstant creation (#180218)
Fixes error of handing constant integers with width in (64; 128) range.
Found during review of
https://github.com/llvm/llvm-project/pull/180182
Commit: 19d6950739a45f17d06ba55034450596625e43d3
https://github.com/llvm/llvm-project/commit/19d6950739a45f17d06ba55034450596625e43d3
Author: Petter Berntsson <petter.berntsson at arm.com>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M libc/docs/headers/math/index.rst
M libc/docs/headers/time.rst
Log Message:
-----------
[libc][docs] Fix stale entrypoints links and time.h table duplication (#180347)
Update stale links and remove duplication in table.
Commit: 55d6c6ff5802efcfc2ab9643316d9670eb29e790
https://github.com/llvm/llvm-project/commit/55d6c6ff5802efcfc2ab9643316d9670eb29e790
Author: Björn Svensson <bjorn.a.svensson at est.tech>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/test/Driver/fuzzer.c
M clang/test/Driver/sanitizer-ld.c
Log Message:
-----------
[clang][driver] Correcting arguments when using `libFuzzer` with `-shared-libsan` (#164842)
This PR contains two commits:
- Add required dependencies when using `-shared-libsan` and fuzzer.
Since libFuzzer is a static library we need to make sure that we add its
dependencies when building with `-shared-libsan`. E.g libFuzzer uses
`ceilf()` from `libm.so` when building on Gnu toolchain.
Previously, the resulting command did not contain the required link
libraries, giving build failures
(only a static sanitizer runtime would trigger the call to
`linkSanitizerRuntimeDeps`).
- Correcting dependency order when using fuzzer.
When building using `-shared-libsan` the sanitizer library needs to be
first in link order.
Since the fuzzer requires `-lstdc++` we have to make sure that the
sanitizer library is added before `-lstdc++`.
---------
Signed-off-by: Björn Svensson <bjorn.a.svensson at est.tech>
Commit: 481f248e081bd82b7a26a0b9b7ce8613544cc1a6
https://github.com/llvm/llvm-project/commit/481f248e081bd82b7a26a0b9b7ce8613544cc1a6
Author: Jason Molenda <jmolenda at apple.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M lldb/include/lldb/Host/HostInfoBase.h
M lldb/include/lldb/Host/macosx/HostInfoMacOSX.h
M lldb/include/lldb/Target/DynamicLoader.h
M lldb/source/Host/macosx/objcxx/HostInfoMacOSX.mm
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.cpp
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderMacOS.cpp
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderMacOS.h
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderMacOSXDYLD.cpp
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderMacOSXDYLD.h
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwinDevice.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwinDevice.h
M lldb/source/Plugins/Platform/MacOSX/PlatformMacOSX.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformRemoteDarwinDevice.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h
M lldb/test/API/commands/platform/basic/TestPlatformCommand.py
Log Message:
-----------
[lldb] Get shared cache path from inferior, open (#180323)
Get the shared cache filepath and uuid that the inferior process is
using from debugserver, try to open that shared cache on the lldb host
mac and if the UUID matches, index all of the binaries in that shared
cache. When looking for binaries loaded in the process, get them from
the already-indexed shared cache.
Every time a binary is loaded, PlatformMacOSX may query the shared cache
filepath and uuid from the Process, and pass that to
HostInfo::GetSharedCacheImageInfo() if available (else fall back to the
old HostInfo::GetSharedCacheImageInfo method which only looks at lldb's
own shared cache), to get the file being requested.
ProcessGDBRemote caches the shared cache filepath and uuid from the
inferior, once it has a non-zero UUID. I added a lock for this ivar
specifically, so I don't have 20 threads all asking for the shared cache
information from debugserver and updating the cached answer. If we never
get back a non-zero UUID shared cache reply, we will re-query at every
library loaded notification. debugserver has been providing the shared
cache UUID since 2013, although I only added the shared cache filepath
field last November.
Note that a process will not report its shared cache filepath or uuid at
initial launch. As dyld gets a chance to execute a bit, it will start
returning binaries -- it will be available at the point when libraries
start loading. (it won't be available yet when the binary & dyld are the
only two binaries loaded in the process)
I tested this by disabling lldb's scan of its own shared cache
pre-execution -- only loading the system shared cache when the inferior
process reports that it is using that. I got 6-7 additional testsuite
failures running lldb like that, because no system binaries were loaded
before exeuction start, and the tests assumed they would be.
rdar://148939795
---------
Co-authored-by: Jonas Devlieghere <jonas at devlieghere.com>
Commit: cfbb9a66ae92aa477c6ea38b006d64ec4b92170d
https://github.com/llvm/llvm-project/commit/cfbb9a66ae92aa477c6ea38b006d64ec4b92170d
Author: Andrew Lazarev <alazarev at google.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/test/Instrumentation/MemorySanitizer/switch-icmp.ll
Log Message:
-----------
Revert "[msan] Switch switch() from strict handling to (icmp eq)-style handling" (#180636)
Reverts llvm/llvm-project#179851
Breaks https://lab.llvm.org/buildbot/#/builders/164/builds/18551 and
https://lab.llvm.org/buildbot/#/builders/94/builds/15188
Commit: 48dffbc654f2a606025f4b14c9b789c99f8188ae
https://github.com/llvm/llvm-project/commit/48dffbc654f2a606025f4b14c9b789c99f8188ae
Author: Tom Stellard <tstellar at redhat.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M .github/workflows/release-documentation.yml
M .github/workflows/release-tasks.yml
Log Message:
-----------
workflows/release-task: Use less privileged token for uploading release notes (#180299) (#180650)
We were using one token for both pushing to the llvmbot fork and for
creating a pull request against the www-releases repository, since the
fork and the repository have different owners, we were using a classic
access token which has very coarse-grained permissions. By using two
separate tokens, we limit the permissions to just what we need to do the
task.
This is a re-commit of b6ee085068972a41f3b2735a9f7e3ca48eab0f00 minus
the environment changes which were causing the workflow to fail.
Commit: 8fc59bc0e3b7bda5a069a2e93a0367f97eebda2b
https://github.com/llvm/llvm-project/commit/8fc59bc0e3b7bda5a069a2e93a0367f97eebda2b
Author: Lleu Yang <hello at megakite.icu>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVISelLowering.h
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/test/CodeGen/SPIRV/AtomicCompareExchange.ll
A llvm/test/CodeGen/SPIRV/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/SPIRV/llc-pipeline.ll
Log Message:
-----------
[SPIRV] Add handling for `uinc_wrap` and `udec_wrap` atomics (#179114)
This adds atomicrmw `uinc_wrap` and `udec_wrap` operations support for
SPIR-V. Since SPIR-V doesn't provide dedicated instructions for those
two operations, we have to use the `AtomicExpand` pass to expand the
operations into CAS forms.
Closes #177204.
Commit: b970a376f4a90bafc9ee2a18ca7a2ebe4e1d2722
https://github.com/llvm/llvm-project/commit/b970a376f4a90bafc9ee2a18ca7a2ebe4e1d2722
Author: Peter Rong <peterrong96 at gmail.com>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
Log Message:
-----------
[DebugInfo] Update test to sync with cross-project-tests (#180655)
The test was manually generated and out-of-sync with
`cross-project-tests/debuginfo-tests/clang_llvm_roundtrip/Inputs/simplified_template_names.cpp`.
We update the test such that:
1. Automate the test generation process by using
`llvm/utils/update_test_body.py`
2. Remove host machine info when updating the tests
Predecessor of #178986, the PR was split per reviewer's request, since
that change disturbed this test a lot.
Commit: 6bce3fc1a9be3d5e2735e0e67dfdf32e47743ca5
https://github.com/llvm/llvm-project/commit/6bce3fc1a9be3d5e2735e0e67dfdf32e47743ca5
Author: Jim Lin <jim at andestech.com>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/test/MC/RISCV/rvv/invalid-alt.s
M llvm/test/MC/RISCV/rvv/vsetvl-alt.s
Log Message:
-----------
[RISCV] Generate 8alt/16alt version error message for zvfofp8min (#180450)
Commit: 0aad6b0657972ed10f30f3497277a9e6badc8b1c
https://github.com/llvm/llvm-project/commit/0aad6b0657972ed10f30f3497277a9e6badc8b1c
Author: Florian Mayer <fmayer at google.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M clang-tools-extra/docs/clang-tidy/checks/abseil/unchecked-statusor-access.rst
Log Message:
-----------
[NFC] [clang-tidy] [doc] Don't use unicode character in doc (#180641)
Commit: 9898082bd358e1706f7703291bdec6caae12993a
https://github.com/llvm/llvm-project/commit/9898082bd358e1706f7703291bdec6caae12993a
Author: vporpo <vasileios.porpodas at amd.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Log Message:
-----------
[AMDGPU][SIInsertWaitcnt][NFC] Access Waitcnt elements using InstCounterType (#178345)
This patch introduces `get(T)` and `set(T, Val)` functions for Waitcnt
and removes getCounterRef() and getWait(). For this to work we also need
to move InstrCounterType to AMDGPUBaseInfo.h.
Please note that the member variables are still public to keep this
patch small.
They will be replaced in the follow-up patch.
Commit: 1de721c414407f4b92d3e2458ce9ca38563cef9c
https://github.com/llvm/llvm-project/commit/1de721c414407f4b92d3e2458ce9ca38563cef9c
Author: Peter Collingbourne <pcc at google.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
A llvm/test/Transforms/LowerTypeTests/cond-loop.ll
Log Message:
-----------
LowerTypeTests: Optimize two-phase check used by llvm.cond.loop.
When a type test has two phases and is used by llvm.cond.loop to
implement a conditional trap, it is more efficient for two infinite
loops to be generated. Arrange for this by having the pass detect the
typical IR pattern used for conditional CFI traps and generate the second
llvm.cond.loop if found.
Part of this RFC:
https://discourse.llvm.org/t/rfc-optimizing-conditional-traps/89456
Reviewers: fmayer, vitalybuka
Reviewed By: vitalybuka
Pull Request: https://github.com/llvm/llvm-project/pull/177687
Commit: dfc8fa80c9fb24c51c3dc1af7660657ece9aeb27
https://github.com/llvm/llvm-project/commit/dfc8fa80c9fb24c51c3dc1af7660657ece9aeb27
Author: Twice <twice at apache.org>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M mlir/include/mlir-c/ExtensibleDialect.h
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/CAPI/IR/ExtensibleDialect.cpp
Log Message:
-----------
[MLIR][Python] Refine trait support in MLIR Python (#180550)
This PR is mainly to address review suggestions in #179705.
Commit: 8c0e0d732f03c50738ba48501c51767643464550
https://github.com/llvm/llvm-project/commit/8c0e0d732f03c50738ba48501c51767643464550
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M mlir/test/Conversion/AMDGPUToROCDL/amdgpu-to-rocdl.mlir
M mlir/test/Conversion/AMDGPUToROCDL/gfx1250.mlir
M mlir/test/Conversion/AMDGPUToROCDL/load_lds-gfx950.mlir
M mlir/test/Conversion/AMDGPUToROCDL/load_lds.mlir
Log Message:
-----------
[mlir][AMDGPU] Make AMDGPUToROCDL conversion tests use real address spaces (#180661)
Since #171876, -amdgpu-to-rocdl (the pass) is now set up to handle
address spaces like `#gpu.address_space<global>`. Update the tests
accordingly.
Commit: 8d8864237b993039ccbc8d0133b583e894922416
https://github.com/llvm/llvm-project/commit/8d8864237b993039ccbc8d0133b583e894922416
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
Log Message:
-----------
AMDGPU/GlobalISel: Regbanklegalize rules for G_FSQRT (#179817)
Add S16 rules for G_FSQRT. S32 and S64 are expanded by the legalizer.
Commit: 776297b0a6daf951acd3b31ece1911b8e40eb405
https://github.com/llvm/llvm-project/commit/776297b0a6daf951acd3b31ece1911b8e40eb405
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFeatures.td
Log Message:
-----------
[RISCV] Rename FeatureEnableSelectOptimize to TuneEnableSelectOptimize (#180496)
It should be a tune feature just like others.
Commit: 20bf8e0684836c48f3a5f58cafd630239c1c9385
https://github.com/llvm/llvm-project/commit/20bf8e0684836c48f3a5f58cafd630239c1c9385
Author: mitchell <mitchell.xu2 at gmail.com>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/ExceptionEscapeCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/ExceptionEscapeCheck.h
M clang-tools-extra/clang-tidy/utils/ExceptionAnalyzer.cpp
M clang-tools-extra/clang-tidy/utils/ExceptionAnalyzer.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/bugprone/exception-escape.rst
A clang-tools-extra/test/clang-tidy/checkers/bugprone/exception-escape-treat-functions-without-specification-as-throwing.cpp
Log Message:
-----------
[clang-tidy] Add options to throw unannotated functions in `bugprone-exception-escape` (#168324)
As of AI Usage: Gemini 3 was used for rephrasing the documentation.
Closes https://github.com/llvm/llvm-project/issues/164795
---------
Co-authored-by: EugeneZelenko <eugene.zelenko at gmail.com>
Co-authored-by: Baranov Victor <bar.victor.2002 at gmail.com>
Commit: 9eca0a3b8bf2068497f1d6345ea290f43c663358
https://github.com/llvm/llvm-project/commit/9eca0a3b8bf2068497f1d6345ea290f43c663358
Author: Longsheng Mou <longshengmou at gmail.com>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/test/Dialect/GPU/invalid.mlir
Log Message:
-----------
[mlir][gpu] Validate argument count in gpu.launch parser (#180388)
This PR adds validation in the `gpu.launch` parser to ensure the launch
configuration provides exactly 3 arguments. Emit a parser error when the
argument count is not 3. Fixes #176426.
Commit: d6ae568d58b31b1cdd0a5f8c84955330a35c3a38
https://github.com/llvm/llvm-project/commit/d6ae568d58b31b1cdd0a5f8c84955330a35c3a38
Author: jeffreytan81 <jeffreytan at meta.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M cross-project-tests/debuginfo-tests/llvm-prettyprinters/lldb/CMakeLists.txt
A cross-project-tests/debuginfo-tests/llvm-prettyprinters/lldb/expected.cpp
A cross-project-tests/debuginfo-tests/llvm-prettyprinters/lldb/expected.test
M cross-project-tests/lit.cfg.py
M llvm/utils/lldbDataFormatters.py
Log Message:
-----------
Fix LLDB data formatter for llvm::Expected<T> with non-reference types (#179294)
This patch fixes LLDB data formatter support for llvm::Expected<T> with
the following changes:
llvm/utils/lldbDataFormatters.py: Fix ExpectedSynthProvider to handle
non-templated storage types (e.g., int, int*). Previously the formatter
only worked with templated storage types like std::reference_wrapper<T>.
cross-project-tests/lit.cfg.py:
Fix get_lldb_version_string() to use locally-built LLDB on non-Darwin
platforms instead of system LLDB
Fix minimum version from "1900" to "19.0.0" (typo in original code)
New test files: Added expected.cpp and expected.test to test the
formatter with Expected<int> and Expected<int*>.
---------
Co-authored-by: Jeffrey Tan <jeffreytan at fb.com>
Commit: 1c503e270a4b772713c45b21fc854949ae6db66d
https://github.com/llvm/llvm-project/commit/1c503e270a4b772713c45b21fc854949ae6db66d
Author: Prabhu Rajasekaran <prabhukr at google.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M libc/config/baremetal/config.json
Log Message:
-----------
[libc] Size optimized defaults for baremetal (#180642)
Disabling options that bloat typical size constrained baremetal targets
and in general not common in these targets. These configuration changes
reduce binary size significantly in our 32 bit ARM target experiments.
Commit: 1c4a98f7687f328d9c0efb367758b0c046d5fb62
https://github.com/llvm/llvm-project/commit/1c4a98f7687f328d9c0efb367758b0c046d5fb62
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/complex.cpp
Log Message:
-----------
[clang][bytecode] Fix discarded builtin_complex (#180539)
This is the only builtin that returns a non-primitive type I think.
Commit: b9659ded76962712a1e984755c2eb54886dfaa83
https://github.com/llvm/llvm-project/commit/b9659ded76962712a1e984755c2eb54886dfaa83
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M clang/lib/Sema/SemaChecking.cpp
M clang/test/Sema/builtins-elementwise-math.c
Log Message:
-----------
[clang] Fix checkMathBuiltinElementType SignedIntOrFloatTy checks (#180528)
The previous check was way too loose and let everything except unsigned
integer types through.
See e.g. https://godbolt.org/z/3qY8EbK56
Commit: fdd9555fc015b0be790226c68391537d12581a82
https://github.com/llvm/llvm-project/commit/fdd9555fc015b0be790226c68391537d12581a82
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/complex.cpp
Log Message:
-----------
[clang][bytecode] Fix discarded Mulc/DivC opcodes (#180537)
We need to pop the pointer in that case.
Commit: 9cd29a8ba17402c6e8e4b051cc96bdf47886581c
https://github.com/llvm/llvm-project/commit/9cd29a8ba17402c6e8e4b051cc96bdf47886581c
Author: Peter Rong <peterrong96 at gmail.com>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M cross-project-tests/debuginfo-tests/clang_llvm_roundtrip/Inputs/simplified_template_names.cpp
M llvm/include/llvm/DebugInfo/DWARF/DWARFTypePrinter.h
M llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
Log Message:
-----------
[DebugInfo] Fix an assertion in DWARFTypePrinter (#178986)
A `DW_TAG_ptr_to_member_type` has no `RawName` and would trigger an
assertion.
https://github.com/llvm/llvm-project/blob/7e48b14d1e9f83b5e4e51d3e44a0fc762f9d05eb/llvm/include/llvm/DebugInfo/DWARF/DWARFTypePrinter.h#L497-L502
The assertion is mostly benign since it will be compared with other
strings and return false.
https://github.com/llvm/llvm-project/blob/7e48b14d1e9f83b5e4e51d3e44a0fc762f9d05eb/llvm/include/llvm/DebugInfo/DWARF/DWARFTypePrinter.h#L505-L510
But this is blocking our assertion builds.
We should escape `DW_TAG_ptr_to_member_type` as well when looking for
type names.
Adding a test to demonstrate how the assertion could be triggered, and
how we fixed it.
Depends on https://github.com/llvm/llvm-project/pull/180655
[Assisted-by](https://t.ly/Dkjjk): [Claude Opus
4.5](https://www.anthropic.com/news/claude-opus-4-5)
Commit: a1acc4ab9fa7bef5684d126ab0c29b035402d664
https://github.com/llvm/llvm-project/commit/a1acc4ab9fa7bef5684d126ab0c29b035402d664
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/memberpointers.cpp
Log Message:
-----------
[clang][bytecode] Fix discarded addrof operators... (#180534)
... of member pointers.
Commit: f33ea53451f01bd82cbe7bc7f795f5b4ba731f2b
https://github.com/llvm/llvm-project/commit/f33ea53451f01bd82cbe7bc7f795f5b4ba731f2b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/condops.ll
M llvm/test/CodeGen/RISCV/xaluo.ll
Log Message:
-----------
[RISCV] Remove redundant czero in multi-word comparisons (#180485)
When comparing multi-word integers with Zicond, we generate:
(or (czero_eqz (lo1 < lo2), (hi1 == hi2)),
(czero_nez (hi1 < hi2), (hi1 == hi2)))
The czero_nez is redundant because when hi1 == hi2 is true, hi1 < hi2 is
already 0. This patch adds a DAG combine to recognize:
czero_nez (setcc X, Y, CC), (setcc X, Y, eq) -> (setcc X, Y, CC)
when CC is a strict inequality (lt, gt, ult, ugt).
This saves one instruction in 128-bit comparisons on RV64 with Zicond.
Note the czero_nez becomes a czero.eqz in the final assembly because the
seteq is replaced by an xor that produces 0 when the values are equal.
Part of #179584
Assisted-by: claude
Commit: 6dc9a484fde9378d466b5626687197924f66115c
https://github.com/llvm/llvm-project/commit/6dc9a484fde9378d466b5626687197924f66115c
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/test/AST/ByteCode/invalid.cpp
Log Message:
-----------
[clang][bytecode] Handle missing target label in break statement (#180532)
Happens in error cases.
Commit: 2302110838463736b0512b4d7fbd94c4694f66d0
https://github.com/llvm/llvm-project/commit/2302110838463736b0512b4d7fbd94c4694f66d0
Author: owenca <owenpiano at gmail.com>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Don't annotate C compound literal r_paren (#180436)
Fixes #180179
Commit: 461e43371855d4c4ce84931270db5ccd1ccd453b
https://github.com/llvm/llvm-project/commit/461e43371855d4c4ce84931270db5ccd1ccd453b
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/intap.cpp
Log Message:
-----------
[clang][bytecode] Don't use trunc() to increase APInt bitWidth (#180536)
`FieldDecl::getBitWidthValue()` can return a value higher than the type
size of the bit field. We need to account for that.
Commit: a56b877056ab5ad9e599d86d48c3189350e5b2a2
https://github.com/llvm/llvm-project/commit/a56b877056ab5ad9e599d86d48c3189350e5b2a2
Author: Kyungtak Woo <kevinwkt at google.com>
Date: 2026-02-09 (Mon, 09 Feb 2026)
Changed paths:
M llvm/lib/Target/X86/CMakeLists.txt
M llvm/lib/Target/X86/X86.h
M llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
A llvm/lib/Target/X86/X86GlobalBaseReg.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86PassRegistry.def
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/test/CodeGen/X86/llc-pipeline-npm.ll
Log Message:
-----------
[NewPM] Port x86-global-base-reg (#180119)
Had to move X86GlobalBaseRegPass to its own file like in
https://github.com/llvm/llvm-project/pull/179864
No test coverage added for now as there are no MIR->MIR tests exercising
this pass and we do not have enough ported to run any end to end tests.
This is a redo of https://github.com/llvm/llvm-project/pull/180070
Commit: 10a50ce32c082f5ead4aadb1078e858dc79749b9
https://github.com/llvm/llvm-project/commit/10a50ce32c082f5ead4aadb1078e858dc79749b9
Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
Date: 2026-02-10 (Tue, 10 Feb 2026)
Changed paths:
M .ci/compute_projects.py
M .ci/compute_projects_test.py
M .github/workflows/release-documentation.yml
M .github/workflows/release-tasks.yml
M bolt/include/bolt/Profile/DataAggregator.h
M clang-tools-extra/clang-tidy/bugprone/ExceptionEscapeCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/ExceptionEscapeCheck.h
M clang-tools-extra/clang-tidy/utils/ExceptionAnalyzer.cpp
M clang-tools-extra/clang-tidy/utils/ExceptionAnalyzer.h
M clang-tools-extra/clangd/ClangdLSPServer.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/abseil/unchecked-statusor-access.rst
M clang-tools-extra/docs/clang-tidy/checks/bugprone/exception-escape.rst
A clang-tools-extra/test/clang-tidy/checkers/bugprone/exception-escape-treat-functions-without-specification-as-throwing.cpp
M clang/docs/ReleaseNotes.rst
M clang/docs/SafeBuffers.rst
M clang/include/clang/AST/ASTContext.h
M clang/include/clang/AST/Expr.h
M clang/include/clang/Basic/BuiltinsAMDGPU.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Lex/PPCallbacks.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/SemaAMDGPU.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Context.cpp
M clang/lib/AST/ByteCode/Context.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpState.cpp
M clang/lib/AST/ByteCode/InterpState.h
M clang/lib/AST/ExprConstant.cpp
M clang/lib/Analysis/CloneDetection.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltin.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenTypes.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGDecl.cpp
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/CodeGen/TargetBuiltins/ARM.cpp
M clang/lib/CodeGen/TargetInfo.cpp
M clang/lib/CodeGen/TargetInfo.h
M clang/lib/CodeGen/Targets/AMDGPU.cpp
M clang/lib/CodeGen/Targets/SPIR.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/OHOS.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Frontend/CompilerInstance.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Sema/SemaAMDGPU.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/StaticAnalyzer/Core/ProgramState.cpp
M clang/lib/Tooling/DependencyScanningTool.cpp
M clang/test/AST/ByteCode/c.c
M clang/test/AST/ByteCode/complex.cpp
A clang/test/AST/ByteCode/constexpr-steps.cpp
M clang/test/AST/ByteCode/intap.cpp
M clang/test/AST/ByteCode/invalid.cpp
M clang/test/AST/ByteCode/memberpointers.cpp
M clang/test/CIR/CodeGenBuiltins/AArch64/acle_sve_dup.c
M clang/test/CodeGen/AArch64/neon-intrinsics.c
A clang/test/CodeGen/AArch64/neon/intrinsics.c
M clang/test/CodeGenCXX/exceptions-seh.cpp
A clang/test/CodeGenHIP/builtins-amdgcn-gfx1250-cooperative-atomics-templated.hip
A clang/test/CodeGenHIP/builtins-amdgcn-gfx1250-load-monitor-templated.hip
M clang/test/CodeGenOpenCL/builtins-amdgcn-fp8.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-load-monitor.cl
A clang/test/DebugInfo/CXX/ctor-homing-local-type.cpp
M clang/test/Driver/darwin-ld-lto.c
M clang/test/Driver/fuzzer.c
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Driver/sanitizer-ld.c
M clang/test/Preprocessor/riscv-target-features.c
M clang/test/Sema/builtins-elementwise-math.c
M clang/test/Sema/format-strings.c
A clang/test/Sema/warn-lifetime-safety-fixits.cpp
M clang/test/SemaCXX/constant-expression-cxx2a.cpp
A clang/test/SemaHIP/builtins-amdgcn-gfx1250-cooperative-atomics-templated.hip
A clang/test/SemaHIP/builtins-amdgcn-gfx1250-load-monitor-templated.hip
A clang/test/SemaHIP/shared-variable-too-large.hip
A clang/test/SemaOpenCL/amdgpu-variables-too-large-for-address-space.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl
A clang/test/SemaOpenCL/builtins-amdgcn-s-wait-event.cl
M clang/test/lit.cfg.py
M clang/unittests/Analysis/FlowSensitive/UncheckedStatusOrAccessModelTestFixture.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/unittests/Frontend/CompilerInstanceTest.cpp
M compiler-rt/lib/asan/asan_allocator.cpp
M compiler-rt/lib/asan/asan_allocator.h
M compiler-rt/lib/asan/asan_malloc_linux.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_allocator.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_allocator_dlsym.h
M compiler-rt/lib/sanitizer_common/sanitizer_allocator_internal.h
A compiler-rt/test/asan/TestCases/AIX/vec_malloc_calloc.cpp
M compiler-rt/test/profile/instrprof-binary-correlate.c
M cross-project-tests/debuginfo-tests/clang_llvm_roundtrip/Inputs/simplified_template_names.cpp
M cross-project-tests/debuginfo-tests/llvm-prettyprinters/lldb/CMakeLists.txt
A cross-project-tests/debuginfo-tests/llvm-prettyprinters/lldb/expected.cpp
A cross-project-tests/debuginfo-tests/llvm-prettyprinters/lldb/expected.test
M cross-project-tests/lit.cfg.py
M flang-rt/lib/runtime/CMakeLists.txt
A flang/include/flang/Optimizer/Analysis/ArraySectionAnalyzer.h
M flang/lib/Lower/OpenMP/OpenMP.cpp
A flang/lib/Optimizer/Analysis/ArraySectionAnalyzer.cpp
M flang/lib/Optimizer/Analysis/CMakeLists.txt
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/lib/Parser/prescan.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Lower/equivalence-with-host-assoc.f90
M flang/test/Lower/explicit-interface-results-2.f90
M flang/test/Lower/explicit-interface-results.f90
M flang/test/Lower/ext-proc-as-actual-argument-1.f90
M flang/test/Lower/ext-proc-as-actual-argument-2.f90
A flang/test/Parser/OpenMP/cont-in-cond-comp.f
M flang/test/Parser/OpenMP/sentinels.f
M flang/test/Parser/continuation-in-conditional-compilation.f
A flang/test/Semantics/OpenMP/allocate_do.f90
A flang/test/Semantics/OpenMP/allocate_do1.f90
A flang/test/Semantics/OpenMP/local-variables-1.f90
A flang/test/Semantics/OpenMP/local-variables-2.f90
R flang/test/Semantics/OpenMP/local-variables.f90
M libc/config/baremetal/config.json
M libc/docs/headers/math/index.rst
M libc/docs/headers/time.rst
M libc/src/__support/str_to_float.h
M libcxx/docs/CodingGuidelines.rst
M libcxx/test/benchmarks/format/format_to.bench.cpp
M libcxx/test/benchmarks/format/format_to_n.bench.cpp
M libcxx/test/benchmarks/format/formatted_size.bench.cpp
M libcxx/utils/ci/BOT_OWNERS.txt
M lld/COFF/Driver.cpp
M lld/ELF/Arch/Hexagon.cpp
M lld/ELF/Arch/X86_64.cpp
M lld/ELF/Relocations.cpp
M lld/ELF/Target.h
M lld/ELF/Writer.cpp
M lld/test/ELF/hexagon-tls-ie.s
M lld/test/wasm/data-layout.s
M lld/test/wasm/export-all.s
M lld/test/wasm/mutable-global-exports.s
M lld/wasm/Config.h
M lld/wasm/Driver.cpp
M lld/wasm/OutputSections.cpp
M lld/wasm/Writer.cpp
M lldb/include/lldb/Host/HostInfoBase.h
M lldb/include/lldb/Host/macosx/HostInfoMacOSX.h
M lldb/include/lldb/Host/windows/ProcessLauncherWindows.h
M lldb/include/lldb/Target/DynamicLoader.h
M lldb/packages/Python/lldbsuite/test/make/Makefile.rules
M lldb/source/Commands/Options.td
M lldb/source/Host/macosx/objcxx/HostInfoMacOSX.mm
M lldb/source/Host/windows/ProcessLauncherWindows.cpp
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.cpp
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderMacOS.cpp
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderMacOS.h
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderMacOSXDYLD.cpp
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderMacOSXDYLD.h
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwinDevice.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwinDevice.h
M lldb/source/Plugins/Platform/MacOSX/PlatformMacOSX.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformRemoteDarwinDevice.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h
M lldb/test/API/commands/platform/basic/TestPlatformCommand.py
M lldb/test/API/driver/batch_mode/TestBatchMode.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/ordering/TestDataFormatterStdOrdering.py
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/vbool/TestDataFormatterStdVBool.py
M lldb/test/API/functionalities/gdb_remote_client/TestWasm.py
M lldb/test/API/tools/lldb-dap/breakpoint-events/Makefile
M lldb/test/API/tools/lldb-dap/breakpoint-events/TestDAP_breakpointEvents.py
M lldb/test/API/tools/lldb-dap/breakpoint-events/foo.cpp
M lldb/test/Shell/DAP/TestSTDINConsole.test
A lldb/test/Shell/ObjectFile/ELF/stt-tls-symbol.yaml
M lldb/tools/driver/Driver.cpp
M lldb/tools/lldb-dap/Handler/AttachRequestHandler.cpp
M lldb/tools/lldb-dap/extension/package-lock.json
M lldb/tools/lldb-dap/extension/package.json
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/CommandGuide/index.rst
A llvm/docs/CommandGuide/llubi.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/CodeGen/Register.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFTypePrinter.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/Value.h
M llvm/include/llvm/ProfileData/InstrProfCorrelator.h
M llvm/include/llvm/ProfileData/SampleProf.h
M llvm/include/llvm/Support/TargetOpcodes.def
A llvm/include/llvm/TargetParser/AVRTargetParser.h
M llvm/include/llvm/TargetParser/Triple.h
M llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h
M llvm/lib/Analysis/ConstantFolding.cpp
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/CAS/OnDiskGraphDB.cpp
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
M llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.cpp
M llvm/lib/CodeGen/MIRParser/MILexer.h
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/ProfileData/InstrProfCorrelator.cpp
M llvm/lib/Target/AArch64/AArch64CallingConvention.td
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
A llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
M llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVISelLowering.h
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/Sparc/CMakeLists.txt
M llvm/lib/Target/Sparc/SparcTargetMachine.cpp
M llvm/lib/Target/Sparc/SparcTargetMachine.h
A llvm/lib/Target/Sparc/SparcTargetTransformInfo.cpp
A llvm/lib/Target/Sparc/SparcTargetTransformInfo.h
M llvm/lib/Target/X86/CMakeLists.txt
M llvm/lib/Target/X86/X86.h
M llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
A llvm/lib/Target/X86/X86GlobalBaseReg.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86PassRegistry.def
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
A llvm/lib/TargetParser/AVRTargetParser.cpp
M llvm/lib/TargetParser/CMakeLists.txt
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/lib/Transforms/IPO/AlwaysInliner.cpp
M llvm/lib/Transforms/IPO/BarrierNoopPass.cpp
M llvm/lib/Transforms/IPO/DeadArgumentElimination.cpp
M llvm/lib/Transforms/IPO/ForceFunctionAttrs.cpp
M llvm/lib/Transforms/IPO/GlobalDCE.cpp
M llvm/lib/Transforms/IPO/IPO.cpp
M llvm/lib/Transforms/IPO/LoopExtractor.cpp
M llvm/lib/Transforms/IPO/LowerTypeTests.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Utils/PredicateInfo.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPredicator.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUnroll.cpp
M llvm/test/Analysis/CostModel/AArch64/loop_dependence_mask.ll
M llvm/test/Analysis/CostModel/RISCV/abs.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll
M llvm/test/Analysis/CostModel/RISCV/splice.ll
M llvm/test/Analysis/CostModel/X86/shuffle-transpose.ll
M llvm/test/Analysis/ValueTracking/assume-queries-counter.ll
M llvm/test/CMakeLists.txt
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-ctls.mir
M llvm/test/CodeGen/AArch64/cfguard-checks.ll
M llvm/test/CodeGen/AArch64/cls.ll
A llvm/test/CodeGen/AArch64/inline-asm-nop-reg.ll
M llvm/test/CodeGen/AArch64/ldst-opt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx942.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-rtn.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.swap.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.swap.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.swap.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.swap.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.v2f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
A llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx1250.mir
A llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.ll
A llvm/test/CodeGen/AMDGPU/indirect-reg-read-imm-idx.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sffbh.ll
M llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
M llvm/test/CodeGen/AMDGPU/loop-vector-sink.ll
M llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll
A llvm/test/CodeGen/MIR/AMDGPU/instr-mmra-error.mir
A llvm/test/CodeGen/MIR/AMDGPU/instr-mmra.mir
A llvm/test/CodeGen/Mips/musttail-fastisel.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv32p.ll
M llvm/test/CodeGen/RISCV/GlobalISel/rv64p.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/condops.ll
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/CodeGen/RISCV/rv32p.ll
M llvm/test/CodeGen/RISCV/rvv/abd.ll
M llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-merge.ll
M llvm/test/CodeGen/RISCV/xaluo.ll
M llvm/test/CodeGen/SPIRV/AtomicCompareExchange.ll
A llvm/test/CodeGen/SPIRV/atomicrmw-uinc-udec-wrap.ll
A llvm/test/CodeGen/SPIRV/extensions/SPV_ALTERA_arbitrary_precision_integers/apint-constant.ll
M llvm/test/CodeGen/SPIRV/hlsl-resources/Sample.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/Sample1D.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/Sample3D.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SampleBias.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SampleCmp.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SampleCmpLevelZero.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SampleCube.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SampleErrors.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SampleErrorsDebug.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SampleGrad.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/SampleLevel.ll
M llvm/test/CodeGen/SPIRV/llc-pipeline.ll
A llvm/test/CodeGen/SPIRV/pointers/sgep-array.ll
A llvm/test/CodeGen/SPIRV/pointers/sgep-class.ll
A llvm/test/CodeGen/SPIRV/pointers/sgep-dynamic-index.ll
A llvm/test/CodeGen/SPIRV/pointers/sgep-nested-struct-array.ll
A llvm/test/CodeGen/SPIRV/pointers/sgep-runtime-array.ll
A llvm/test/CodeGen/SPIRV/pointers/sgep-struct.ll
A llvm/test/CodeGen/SPIRV/pointers/sgep-vector.ll
M llvm/test/CodeGen/X86/combine-adc.ll
M llvm/test/CodeGen/X86/llc-pipeline-npm.ll
M llvm/test/CodeGen/X86/select-big-integer.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
M llvm/test/Instrumentation/MemorySanitizer/switch-icmp.ll
A llvm/test/MC/AMDGPU/gfx1150_unsupported.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop1-fake16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop1.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop1_dpp16-fake16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop1_dpp16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop1_dpp8-fake16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop1_dpp8.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3-fake16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3_dpp16-fake16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3_dpp16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3_dpp8-fake16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3_dpp8.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3_err.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1-fake16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1_dpp16-fake16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1_dpp16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1_dpp8-fake16.s
A llvm/test/MC/AMDGPU/gfx1170_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx11_asm_err.s
M llvm/test/MC/AMDGPU/gfx11_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx12_asm_sopp.s
M llvm/test/MC/AMDGPU/gfx12_err.s
M llvm/test/MC/AMDGPU/gfx13_asm_sopp.s
A llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop1_dpp16.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop1_dpp8.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_dpp16.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_dpp8.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_from_vop1.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_from_vop1_dpp16.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx1170_dasm_vop3_from_vop1_dpp8.txt
A llvm/test/MC/Hexagon/newvalue_jump_ext_imm.s
M llvm/test/MC/RISCV/rv64p-valid.s
M llvm/test/MC/RISCV/rvv/invalid-alt.s
M llvm/test/MC/RISCV/rvv/vsetvl-alt.s
A llvm/test/MC/RISCV/rvv/zvabd-invalid.s
A llvm/test/MC/RISCV/rvv/zvabd.s
M llvm/test/Transforms/ForcedFunctionAttrs/forced.ll
M llvm/test/Transforms/InstCombine/assume.ll
M llvm/test/Transforms/InstCombine/gep-sext.ll
A llvm/test/Transforms/InstCombine/gep-srem-to-and-deref.ll
A llvm/test/Transforms/InstCombine/maximumnum.ll
M llvm/test/Transforms/InstCombine/maxnum.ll
A llvm/test/Transforms/InstCombine/minimumnum.ll
M llvm/test/Transforms/InstCombine/minnum.ll
M llvm/test/Transforms/InstCombine/trunc-extractelement.ll
A llvm/test/Transforms/LoopIdiom/Sparc/lit.local.cfg
A llvm/test/Transforms/LoopIdiom/Sparc/popcnt.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/multiple-result-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-with-invariant-stores.ll
A llvm/test/Transforms/LoopVectorize/find-last-sink-based-iv-expr.ll
M llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll
A llvm/test/Transforms/LoopVectorize/loop-legality-checks-remarks.ll
M llvm/test/Transforms/LoopVectorize/multiple-result-intrinsics.ll
M llvm/test/Transforms/LoopVectorize/outer-loop-inner-latch-successors.ll
M llvm/test/Transforms/LoopVectorize/outer-loop-wide-phis.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll
M llvm/test/Transforms/LoopVectorize/outer_loop_test2.ll
A llvm/test/Transforms/LoopVectorize/phi-with-fastflags-vplan.ll
A llvm/test/Transforms/LoopVectorize/phi-with-fastflags.ll
M llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll
M llvm/test/Transforms/LoopVectorize/struct-return.ll
M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
M llvm/test/Transforms/LoopVectorize/vplan-printing-outer-loop.ll
M llvm/test/Transforms/LoopVectorize/vplan-unused-interleave-group.ll
M llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
M llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
M llvm/test/Transforms/LoopVectorize/vplan-widen-struct-return.ll
A llvm/test/Transforms/LowerTypeTests/cond-loop.ll
M llvm/test/Transforms/PhaseOrdering/d83507-knowledge-retention-bug.ll
M llvm/test/Transforms/SCCP/assume-operand-bundles.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-shuffles.ll
M llvm/test/lit.cfg.py
A llvm/test/tools/llubi/main.ll
A llvm/test/tools/llubi/main2.ll
A llvm/test/tools/llubi/poison.ll
M llvm/test/tools/llvm-dwarfdump/X86/simplified-template-names.s
A llvm/test/tools/llvm-objdump/ELF/AVR/lit.local.cfg
A llvm/test/tools/llvm-objdump/ELF/AVR/mattr.test
M llvm/tools/llc/CMakeLists.txt
M llvm/tools/llc/llc.cpp
A llvm/tools/llubi/CMakeLists.txt
A llvm/tools/llubi/lib/CMakeLists.txt
A llvm/tools/llubi/lib/Context.cpp
A llvm/tools/llubi/lib/Context.h
A llvm/tools/llubi/lib/Interpreter.cpp
A llvm/tools/llubi/lib/Value.cpp
A llvm/tools/llubi/lib/Value.h
A llvm/tools/llubi/llubi.cpp
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/unittests/IR/IRBuilderTest.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp
M llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn
M llvm/utils/lldbDataFormatters.py
M mlir/.clang-tidy
A mlir/include/mlir-c/ExtensibleDialect.h
M mlir/include/mlir/Bindings/Python/IRCore.h
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUOps.td
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPUTypes.td
M mlir/include/mlir/Dialect/Utils/StaticValueUtils.h
M mlir/include/mlir/Dialect/Vector/TransformOps/VectorTransformOps.td
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/CAPI/IR/CMakeLists.txt
A mlir/lib/CAPI/IR/ExtensibleDialect.cpp
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
M mlir/lib/Dialect/Utils/StaticValueUtils.cpp
M mlir/lib/Dialect/Vector/TransformOps/VectorTransformOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUSubgroupDistribute.cpp
M mlir/test/Conversion/AMDGPUToROCDL/amdgpu-to-rocdl.mlir
M mlir/test/Conversion/AMDGPUToROCDL/gfx1250.mlir
M mlir/test/Conversion/AMDGPUToROCDL/load_lds-gfx950.mlir
M mlir/test/Conversion/AMDGPUToROCDL/load_lds.mlir
M mlir/test/Dialect/AMDGPU/invalid.mlir
M mlir/test/Dialect/AMDGPU/ops.mlir
M mlir/test/Dialect/GPU/invalid.mlir
M mlir/test/Dialect/SCF/trip_count.mlir
M mlir/test/Dialect/SPIRV/IR/types.mlir
M mlir/test/Dialect/SPIRV/Transforms/replicated-const-composites.mlir
M mlir/test/Dialect/Vector/transform-vector.mlir
M mlir/test/python/dialects/ext.py
M mlir/test/python/dialects/transform_vector_ext.py
M offload/test/lit.cfg
M offload/test/mapping/firstprivate_aligned.cpp
M offload/test/offloading/fortran/basic-target-parallel-do.f90
M offload/test/offloading/fortran/basic-target-parallel-reduction.f90
M offload/test/offloading/fortran/basic-target-teams-parallel-reduction.f90
M offload/test/offloading/fortran/default-mapper-nested-derived-type.f90
M offload/test/offloading/fortran/do-concurrent-to-omp-saxpy-2d.f90
M offload/test/offloading/fortran/do-concurrent-to-omp-saxpy.f90
M offload/test/offloading/fortran/explicit-and-implicit-record-field-mapping.f90
M offload/test/offloading/fortran/implicit-record-field-mapping.f90
M offload/test/offloading/fortran/target-custom-reduction-derivedtype.f90
M offload/test/offloading/fortran/target-no-loop.f90
M offload/test/offloading/fortran/target-parallel-do-collapse.f90
M offload/test/offloading/ompx_bare.c
M offload/test/offloading/ompx_bare_multi_dim.cpp
M utils/bazel/MODULE.bazel.lock
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/driver.bzl
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/build_defs.bzl
A utils/bazel/llvm-project-overlay/mlir/stubgen_runner.py
M utils/bazel/third_party_build/nanobind.BUILD
Log Message:
-----------
Merge branch 'main' into users/ssahsara/async-lds-dma
Compare: https://github.com/llvm/llvm-project/compare/9803e3ef03b3...10a50ce32c08
To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications
More information about the All-commits
mailing list