[all-commits] [llvm/llvm-project] e99259: [RISCV][CodeGen] Lower `abds`/`abdu` to `Zvabd` in...

[Pengcheng Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e992593341688862f658348f82e83a0f89a84b2f
      https://github.com/llvm/llvm-project/commit/e992593341688862f658348f82e83a0f89a84b2f
  Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
  Date:   2026-02-09 (Mon, 09 Feb 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZvabd.td
    M llvm/test/CodeGen/RISCV/rvv/abd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll

  Log Message:
  -----------
  [RISCV][CodeGen] Lower `abds`/`abdu` to `Zvabd` instructions

We directly lower `ISD::ABDS`/`ISD::ABDU` to `Zvabd` instructions.

Note that we only support SEW=8/16 for `vabd.vv`/`vabdu.vv`.

Reviewers: mshockwave, lukel97, topperc, preames, tclin914, 4vtomat

Reviewed By: lukel97, topperc

Pull Request: https://github.com/llvm/llvm-project/pull/180141



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