[all-commits] [llvm/llvm-project] 6f0b87: [CodeGen] Refactor targets to override the new get...

[Nicolai Hähnle via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6f0b873f1c1539dc010df4fdbac2faa6bc76b2b5
      https://github.com/llvm/llvm-project/commit/6f0b873f1c1539dc010df4fdbac2faa6bc76b2b5
  Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
  Date:   2026-02-02 (Mon, 02 Feb 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.h
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.h
    M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
    M llvm/lib/Target/Hexagon/HexagonISelLowering.h
    M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
    M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    M llvm/lib/Target/PowerPC/PPCISelLowering.h
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
    M llvm/lib/Target/SPIRV/SPIRVISelLowering.h
    M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.h

  Log Message:
  -----------
  [CodeGen] Refactor targets to override the new getTgtMemIntrinsic overload (NFC) (#175844)

This is a fairly mechanical change. Instead of returning true/false,
we either keep the Infos vector empty or push one entry.



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