[all-commits] [llvm/llvm-project] f9423e: [mlir] Fix alignment for predicate (i1) vectors (#...

[Andrzej Warzyński via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f9423ed07c7a6839aa58bf010f0278f959948c99
      https://github.com/llvm/llvm-project/commit/f9423ed07c7a6839aa58bf010f0278f959948c99
  Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
  Date:   2026-02-02 (Mon, 02 Feb 2026)

  Changed paths:
    M mlir/lib/Interfaces/DataLayoutInterfaces.cpp
    M mlir/test/Interfaces/DataLayoutInterfaces/query.mlir

  Log Message:
  -----------
  [mlir] Fix alignment for predicate (i1) vectors (#175975)

Legal scalable predicate vectors (legal in the LLVM sense), e.g.
`vector<[16]xi1>` (or `<vscale x 16 x i1>`, using LLVM syntax) ought to
have alignment **2** rather than **16**, see e.g. [1].

MLIR currently computes the vector “size in bits” as:

```cpp
vecType.getNumElements()
  * dataLayout.getTypeSize(vecType.getElementType()) * 8
```

but `getTypeSize()` returns a size in *bytes* (rounded up from bits), so
for `i1` it returns 1. Multiplying by 8 converts that storage byte back to 8
bits per element, which overestimates predicate vector sizes.

Instead, use:

```cpp
vecType.getNumElements()
  * dataLayout.getTypeSizeInBits(vecType.getElementType())
```

For `vector<[16]xi1>` this changes:
  * [before]: `alignment = 16 * (1 byte * 8) (i.e.  `128 bits`),

to:
  * [after]:  `alignment = 16 * 1 bit` (i.e. `16 bits`).

This is a very small update that, based on the available tests, only
affects types like `vector<[16]xi1>`. It aligns MLIR with LLVM, making
sure that the corresponding alignment is 2 rather that 16. For context,
LLVM computes the alignment in this case via `getTypeStoreSize`, which
for `16 x i1` returns 2 bytes. Perhaps MLIR should follow similar path
in the future.

[1] https://developer.arm.com/documentation/ddi0602/2025-12/SVE-Instructions/LDR--predicate---Load-predicate-register-?lang=en



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