[all-commits] [llvm/llvm-project] 3ed483: [RISCV] Run combineOrToBitfieldInsert after DAG le...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3ed48305ab19bf0090d2ca714a37dd7b0667b6c2
      https://github.com/llvm/llvm-project/commit/3ed48305ab19bf0090d2ca714a37dd7b0667b6c2
  Author: Sudharsan Veeravalli <svs at qti.qualcomm.com>
  Date:   2026-01-26 (Mon, 26 Jan 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/xqcibm-insert.ll

  Log Message:
  -----------
  [RISCV] Run combineOrToBitfieldInsert after DAG legalize (#177830)

Not combing `OR` into `QC.INSB(I)` before DAG legalization helps known
bits analysis to simplify the code if possible.



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