[all-commits] [llvm/llvm-project] 9269f8: [clang] Add myself as an additional offloading dri...
Utkarsh Saxena via All-commits
all-commits at lists.llvm.org
Fri Jan 23 11:58:47 PST 2026
Branch: refs/heads/users/usx95/01-23-fix_issue_with_references_to_fields
Home: https://github.com/llvm/llvm-project
Commit: 9269f84d677491f7cbecff0cf2555d90ea713f28
https://github.com/llvm/llvm-project/commit/9269f84d677491f7cbecff0cf2555d90ea713f28
Author: Nick Sarnie <nick.sarnie at intel.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/Maintainers.rst
Log Message:
-----------
[clang] Add myself as an additional offloading driver maintainer (#177392)
I've worked in the offloading driver a decent amount both directly here
and in Intel's downstream forks and I feel I have the judgement to
consider the needs of the project overall as well as the bandwidth to
properly carry out the role.
Signed-off-by: Nick Sarnie <nick.sarnie at intel.com>
Commit: 10d6e4e5bd3939daa0d27a81380db16cc0367b09
https://github.com/llvm/llvm-project/commit/10d6e4e5bd3939daa0d27a81380db16cc0367b09
Author: Mingming Liu <mingmingl at google.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemProfUse.cpp
Log Message:
-----------
[StaticDataLayout] Temporarily undo diagnostic warning when the data access profile payload is not available (#177412)
Added a FIXME to add it back later after figuring out how to make it a
non-error like the PGO profile mismatch one.
Commit: 8735e0c5145d9392b85edd54ca17481eb468d4bf
https://github.com/llvm/llvm-project/commit/8735e0c5145d9392b85edd54ca17481eb468d4bf
Author: Roland McGrath <mcgrathr at google.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M libc/config/linux/app.h
M libc/src/__support/threads/fork_callbacks.cpp
Log Message:
-----------
[libc] Remove superfluous explicitly defaulted constructors (#177471)
Any user-defined constructor, even an `= default` one, is
incompatible with aggregate initialization in C++20.
The default constructor does not need to be declared at all in
these cases. It's implicit.
Commit: 7ea1fa591abc28df2596781c5d7be67cf92f6ed3
https://github.com/llvm/llvm-project/commit/7ea1fa591abc28df2596781c5d7be67cf92f6ed3
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/find-last.ll
Log Message:
-----------
[LV] Skip FindLast reductions in collectInLoopReductions.
FindLast in-loop reductions are not supported, similarly to FindLastIV
reductions. Skip them in collectInLoopReductions, to avoid a crash for
loops with FindLast reductions and in-loop reductions preferred.
Commit: ce2a5919cd69fe41322064fdec1fe9c1218e2bef
https://github.com/llvm/llvm-project/commit/ce2a5919cd69fe41322064fdec1fe9c1218e2bef
Author: Akimasa Watanuki <mencotton0410 at gmail.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/test/Dialect/GPU/invalid.mlir
Log Message:
-----------
[mlir][gpu] Enforce async keyword when parsing gpu.launch with results (#176570)
The `gpu.launch` parser attempts to add a null `asyncTokenType` to the
results list if a result is requested but the `async` keyword is
missing, leading to an assertion failure.
Explicitly verify that `asyncTokenType` is valid when
`parser.getNumResults() > 0`. Emit a diagnostic error if the `async`
keyword is missing instead of crashing.
Add a regression test to `mlir/test/Dialect/GPU/invalid.mlir`.
Fix: https://github.com/llvm/llvm-project/issues/176530
Commit: 8b72266f415a1aa98d2ea686a1059cfd90bced1f
https://github.com/llvm/llvm-project/commit/8b72266f415a1aa98d2ea686a1059cfd90bced1f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/clmul-vector.ll
M llvm/test/CodeGen/X86/combine-pclmul.ll
M llvm/test/CodeGen/X86/pclmulqdq.ll
Log Message:
-----------
[X86] combinePCLMULQDQ - attempt to fold PCLMULQDQ(SHUFFLE(X),SHUFFLE(Y),C) -> PCLMULQDQ(X,Y,C') (REAPPLIED) (#177454)
Peek through input shuffle operands and see if we can access the shuffle
source directly with an adjusted PCLMULQDQ mask bit
REAPPLIED after #176932 was reverted due to use of
is128BitLaneRepeatedShuffleMask instead of isRepeatedTargetShuffleMask
caused failures with SM_SentinalZero shuffle mask indices - regression
test added by #177414
Fixes #176880
Commit: 5af4c1c65a0a4500a4f9f892c3562f2fab0392b2
https://github.com/llvm/llvm-project/commit/5af4c1c65a0a4500a4f9f892c3562f2fab0392b2
Author: Steven Wu <stevenwu at apple.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
A llvm/include/llvm/CAS/CASNodeSchema.h
A llvm/include/llvm/CAS/NamedValuesSchema.h
A llvm/lib/CAS/CASNodeSchema.cpp
M llvm/lib/CAS/CMakeLists.txt
A llvm/lib/CAS/NamedValuesSchema.cpp
M llvm/unittests/CAS/CMakeLists.txt
A llvm/unittests/CAS/NamedValuesSchemaTest.cpp
Log Message:
-----------
[CAS] Introduce CASNodeSchema and NamedValuesSchema (#177058)
Introduce CASNodeSchema, which is the common base class for
building a schema that can be used to represent an object
inside CAS. The schema describes the ways to encode and decode
between CAS objects and their representative objects.
NamedValuesSchema is a basic schema that describes a sorted
list of named nodes, where each node is an object. The names are
stored in the root object, allowing users to decide whether to
load the objects based on their names.
Commit: f8c4974963302912cd6c5c11d5097de5530c4943
https://github.com/llvm/llvm-project/commit/f8c4974963302912cd6c5c11d5097de5530c4943
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/include/llvm/Transforms/Scalar/MemCpyOptimizer.h
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
R llvm/test/Transforms/MemCpyOpt/stack-move-offset.ll
Log Message:
-----------
Revert "[MemCpyOpt] support offset slices for performStackMoveOptzn and processMemCpy (#176436)" (#177482)
This reverts commit 019eb855dd6a18a8f7ae5dd86abf6bc3ad0d9fa4.
Causes miscompiles, see original PR and #177185
Fixes https://github.com/llvm/llvm-project/issues/177185
Commit: f6e050c5f84803c6ca0d1d6d19051d3434e439a4
https://github.com/llvm/llvm-project/commit/f6e050c5f84803c6ca0d1d6d19051d3434e439a4
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/CAS/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/CAS/BUILD.gn
Log Message:
-----------
[gn build] Port 5af4c1c65a0a
Commit: 3219f1a5ce497125025ad8d27131cdea4b6e8595
https://github.com/llvm/llvm-project/commit/3219f1a5ce497125025ad8d27131cdea4b6e8595
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M openmp/device/src/Configuration.cpp
Log Message:
-----------
[OpenMP] Force initialization of global device environment
Summary:
This causes issues when we omit this, which requires a constructor from
an incompatible address space and bad things happen.
Commit: 1e6e25573f5a9dce9591e6ab429c465a8271ad18
https://github.com/llvm/llvm-project/commit/1e6e25573f5a9dce9591e6ab429c465a8271ad18
Author: Roland McGrath <mcgrathr at google.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M libc/src/__support/CPP/type_traits/is_unsigned.h
Log Message:
-----------
[libc] Clean up cpp::is_unsigned (#177456)
There are no unsigned floating-point types, so make it a
subset of is_integral instead of is_arithmetic.
Commit: 778ee545b54792d7b43fba201669699ef2d9b033
https://github.com/llvm/llvm-project/commit/778ee545b54792d7b43fba201669699ef2d9b033
Author: Roland McGrath <mcgrathr at google.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M libc/src/__support/CPP/limits.h
Log Message:
-----------
[libc] Clean up cpp::numeric_limits (#177461)
This adds the missing is_signed member and uses a generic
implementation for all integral types, using the same methods
employed by the libc++ implementation.
Commit: 53b0a64e9826c0696f22b945aa919e8552ed432d
https://github.com/llvm/llvm-project/commit/53b0a64e9826c0696f22b945aa919e8552ed432d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/RISCV/clmul.ll
M llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
M llvm/test/CodeGen/X86/clmul-vector.ll
Log Message:
-----------
[SelectionDAG] Add very basic computeKnownBits support for ISD::CLMUL. (#177445)
This implements leading zero count support so we can remove some
unnecessary ANDs.
Commit: 707ae1df5c266522c38b9af7e9586dd891267c17
https://github.com/llvm/llvm-project/commit/707ae1df5c266522c38b9af7e9586dd891267c17
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
Log Message:
-----------
Reland "[AMDGPU][GlobalISel] Add RegBankLegalize support for G_MUL (#… (#177481)
…177314)"
Original reverted due to v2s16 test failure caused by upstream gfx6/7
16-bit vector behavior change that landed shortly before.
Rebased and regenerated mul.ll test.
Original PR: #177314
Commit: 30fc5c1cdf9b177fabba55f9fc9df0025d54cf18
https://github.com/llvm/llvm-project/commit/30fc5c1cdf9b177fabba55f9fc9df0025d54cf18
Author: Sean Fertile <sd.fertile at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
A llvm/test/CodeGen/PowerPC/ppc64-patchpoint-size-check.ll
Log Message:
-----------
[PPC64] Convert assert in patchpoint emission to usage error. (#177453)
If the patchpoint intrinsic has requested less bytes then it takes to
make the call then report a fatal usage error. Also fixed a bug where we
forgot to count one of the instructions emitted.
Commit: a7b57cf7bba13cd7851bca1f2f3a820c74110c0d
https://github.com/llvm/llvm-project/commit/a7b57cf7bba13cd7851bca1f2f3a820c74110c0d
Author: Abhinav Gaba <abhinav.gaba at intel.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/test/OpenMP/declare_mapper_codegen.cpp
M clang/test/OpenMP/target_map_array_of_structs_with_nested_mapper_codegen.cpp
M clang/test/OpenMP/target_map_array_section_of_structs_with_nested_mapper_codegen.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/test/Target/LLVMIR/omptarget-llvm.mlir
M offload/libomptarget/omptarget.cpp
A offload/test/mapping/declare_mapper_target_checks.cpp
Log Message:
-----------
[OpenMP][Mappers] Fix ref-count tracking for maps inserted by mappers. (#177059)
This is a fix for https://github.com/llvm/llvm-project/issues/61636.
Ravi had this implemented downstream before he retired. This PR is a
chery-pick of that.
The test is taken from @jdoerfert's WIP change in
https://github.com/jdoerfert/llvm-project/commit/527bf4b1293f452aac1f872c4f771c7950b911f9.
The change partially undoes the changes done in
0caf736d7e1d16d1059553fc28dbac31f0b9f788, so @alexey-bataev might need
to take a look.
---------
Co-authored-by: Ravi Narayanaswamy <ravi.narayanaswamy at intel.com>
Co-authored-by: Johannes Doerfert <johannes at jdoerfert.de>
Commit: 98b42e384a957d418b48ee7351ebcbb6eccd5a8b
https://github.com/llvm/llvm-project/commit/98b42e384a957d418b48ee7351ebcbb6eccd5a8b
Author: joaosaffran <joaosaffranllvm at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/test/CodeGenHLSL/builtins/atan2-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/ceil-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/cos-overloads.hlsl
Log Message:
-----------
[HLSL] Make atan2, cos, ceil overload tests stricter NFC (#177431)
This patch updates atan2, cos and ceil overload tests to use -O1 instead
of -disable-llvm-passes; also, the checks are updated to match the
change accordingly.
This work is part of https://github.com/llvm/llvm-project/issues/138016.
Commit: 58f3159a00a84b5a8a2f933a47e8ed92c6cca614
https://github.com/llvm/llvm-project/commit/58f3159a00a84b5a8a2f933a47e8ed92c6cca614
Author: Kelvin Li <kli at ca.ibm.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M flang/include/flang/Evaluate/real.h
Log Message:
-----------
[flang][AIX] Suppress AIX compat error (NFC) (#177174)
Commit: 8a954feb3ed879794a82ff4313d22dcf5c4f32f8
https://github.com/llvm/llvm-project/commit/8a954feb3ed879794a82ff4313d22dcf5c4f32f8
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Replace legacy FindLast check with VPlan-based one (NFCI).
Checking directly in VPlan is more accurate, as the reductions could
have been transformed. This does not happen yet, so currently NFC.
Commit: 476a194935fa55f9e18f9193d25d86170f2219ab
https://github.com/llvm/llvm-project/commit/476a194935fa55f9e18f9193d25d86170f2219ab
Author: Roland McGrath <mcgrathr at google.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M libc/src/__support/CPP/type_traits/is_integral.h
M libc/src/__support/wchar/character_converter.h
Log Message:
-----------
[libc] Handle charNN_t in cpp::is_integral (#177463)
In C++20, char8_t is a distinct type from unsigned char, but is
still an integral type. char16_t and char32_t are integral types
in both C++17 and C++20.
This also reverts the change in PR #177421, which is not needed
when cpp::is_integral_v<char8_t> works correctly in all modes.
Commit: 7d5622f7917815d224b780309432ffe4729e4852
https://github.com/llvm/llvm-project/commit/7d5622f7917815d224b780309432ffe4729e4852
Author: Abhinav Gaba <abhinav.gaba at intel.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M offload/test/mapping/declare_mapper_target_checks.cpp
Log Message:
-----------
[NFC][OpenMP] Mark new mapper test as XFAIL on intelgpu. (#177491)
Other tests in the directory already do this. The new test was added in
#177059.
Commit: bc4b2765eb60a28913af1a2c5e92e4e806144f73
https://github.com/llvm/llvm-project/commit/bc4b2765eb60a28913af1a2c5e92e4e806144f73
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
Log Message:
-----------
[NFCI][AMDGPU] Refine `AMDGPUSubtarget.h` (#177473)
This PR is to move code around to pave the path for using
`GET_SUBTARGETINFO_MACRO` in `GCNSubtarget.h`.
Commit: 12b3a9f52e76611b3d3ceb746559d2c384b2565e
https://github.com/llvm/llvm-project/commit/12b3a9f52e76611b3d3ceb746559d2c384b2565e
Author: Usman Nadeem <mnadeem at qti.qualcomm.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/test/tools/llvm-exegesis/AArch64/debug-gen-asm.s
Log Message:
-----------
[llvm-exegesis] Add -mtriple to AArch64 test (#177485)
Similar to https://github.com/llvm/llvm-project/pull/148968
Commit: 626e3423f8bde1e0e79055c4675ed7ca944579c9
https://github.com/llvm/llvm-project/commit/626e3423f8bde1e0e79055c4675ed7ca944579c9
Author: Andres-Salamanca <andrealebarbaritos at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenCoroutine.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/test/CIR/CodeGen/coro-task.cpp
Log Message:
-----------
[CIR] Upstream coroutine builtin coro_end (#176598)
This PR adds support for emitting the `__builtin_coro_end` builtin in
CIR.
Commit: 07ffea4d8c4f6da0ad6cfb83411c3f934c1821c1
https://github.com/llvm/llvm-project/commit/07ffea4d8c4f6da0ad6cfb83411c3f934c1821c1
Author: cmtice <cmtice at google.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
A llvm/test/CodeGen/AArch64/fptoi-256.ll
R llvm/test/CodeGen/fptoi-256.ll
Log Message:
-----------
[LLVM] Move CodeGen test to proper subdirectory. (#177493)
PR #176851 put an AArch64 test directly in the llvm/test/CodeGen
directory. This moves the test to the proper subdirectory.
Commit: 6fbd16115049f784dfb8aae525d6dcf6c7a1756e
https://github.com/llvm/llvm-project/commit/6fbd16115049f784dfb8aae525d6dcf6c7a1756e
Author: Nico Weber <thakis at chromium.org>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/test/AST/ast-dump-decl-stmts.cpp
Log Message:
-----------
[clang] Set end loc on declspec() (#177001)
Follow-up to #176296 where the root problem was declspec() not having a
valid range.
I don't if this is the right fix! It _is_ a progression on the included
test file though, and it's similar to what
Parser::ParsePackIndexingType() in the same file does.
Commit: 6f4661ce8f65dbc17797d7b55a3020f8b744b1c6
https://github.com/llvm/llvm-project/commit/6f4661ce8f65dbc17797d7b55a3020f8b744b1c6
Author: George Burgess IV <george.burgess.iv at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M SECURITY.md
Log Message:
-----------
[SECURITY.md] add pointers to "what is a security issue" (#177372)
Over the years, the security group has received a decent number of
reports of malicious input causing e.g., Clang to crash.
While these reports are valuable, it seems useful to clarify that many
of them are considered bugs, rather than security issues.
Commit: a24f6ce743cc2dd311e35894f386c05d0ead089c
https://github.com/llvm/llvm-project/commit/a24f6ce743cc2dd311e35894f386c05d0ead089c
Author: Adrian Prantl <aprantl at apple.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M lldb/include/lldb/Core/Debugger.h
M lldb/include/lldb/Core/ModuleList.h
M lldb/source/Core/CoreProperties.td
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/ModuleList.cpp
M lldb/source/Symbol/Variable.cpp
M lldb/test/API/commands/expression/diagnostics/TestExprDiagnostics.py
Log Message:
-----------
[LLDB] Add a setting to simulate variables with missing locations (#177279)
Writing testcases for error handling that depends on specific DWARF is
very difficult and the resulting tests tend not to be very portable.
This patch adds a new setting to inject an error into variable
materialization, thus making it possible to write very simple source
code based tests for error handling instead.
This is primarily motivated by the Swift language plugin, but
functionality is generic and should be useful for other languages as
well.
Commit: 599c2731b3bbe9add135558377dbee2e1fa24358
https://github.com/llvm/llvm-project/commit/599c2731b3bbe9add135558377dbee2e1fa24358
Author: Alireza Torabian <alireza.torabian at huawei.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
A llvm/test/Transforms/LoopFusion/pr115279.ll
Log Message:
-----------
[LoopFusion] Forget cached SCEV values after the fusion (#177455)
This patch fixes the issue #115279. After the fusion, some of the cached
SCEV values such as the induction variable may not be valid anymore and
need to be forgotten.
Commit: f53fe860385c706903f74ac45404e95a841c113f
https://github.com/llvm/llvm-project/commit/f53fe860385c706903f74ac45404e95a841c113f
Author: Jie Fu <jiefu at tencent.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
Log Message:
-----------
[Vectorize] Silence a warning (NFC)
/llvm-project/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp:1533:11:
error: unused variable 'FindIVSelect' [-Werror,-Wunused-variable]
auto *FindIVSelect = findUserOf<Instruction::Select>(FindIVCmp);
^
1 error generated.
Commit: 33c301e84137af8a6b8701657b3023355f4f22b2
https://github.com/llvm/llvm-project/commit/33c301e84137af8a6b8701657b3023355f4f22b2
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang-tools-extra/clang-tidy/llvm/UseRangesCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/llvm/use-ranges.rst
M clang-tools-extra/test/clang-tidy/checkers/llvm/use-ranges.cpp
Log Message:
-----------
[clang-tidy] Add replace_ to llvm-use-ranges (#177457)
Also sort the list of known algorithm wrappers.
Commit: 8a94708d8f64f0286401f8eb36f90111e245edb4
https://github.com/llvm/llvm-project/commit/8a94708d8f64f0286401f8eb36f90111e245edb4
Author: Akira Hatanaka <ahatanak at gmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang/lib/Sema/SemaDeclAttr.cpp
A clang/test/PlatformSpecific/xrOS/Sema/Inputs/XROS.sdk/SDKSettings.json
A clang/test/PlatformSpecific/xrOS/Sema/infer-ios-availability.c
A clang/test/PlatformSpecific/xrOS/Sema/infer-unavailable-from-missing-ios-availability-mapping.c
Log Message:
-----------
Infer visionOS availability from iOS availability (#176990)
Automatically infer and apply availability or unavailable attributes for
visionOS based on the corresponding iOS availability of the same
declaration using the version mapping information provided in
SDKSettings.json.
rdar://162148639
Commit: 11f64e92c627154a1caeb6d68c9999cca20f0dae
https://github.com/llvm/llvm-project/commit/11f64e92c627154a1caeb6d68c9999cca20f0dae
Author: Jie Fu <jiefu at tencent.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
Log Message:
-----------
[AMDGPU] Silence a warning (NFC)
llvm-project/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp:686:7:
error: unused variable 'DstTy' [-Werror,-Wunused-variable]
LLT DstTy = MRI.getType(Dst);
^
1 error generated.
Commit: e028b212c0faf23beb8f8b494315d0e3878cff5d
https://github.com/llvm/llvm-project/commit/e028b212c0faf23beb8f8b494315d0e3878cff5d
Author: valadaptive <79560998+valadaptive at users.noreply.github.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
A llvm/test/CodeGen/AArch64/arm64-vcvt-fptoi.ll
Log Message:
-----------
[AArch64] Add tests for vector rounding + float-to-int conversions (#173516)
Right now we only have tests for the scalar versions of these
intrinsics.
Commit: 700b5f1387a50bfc0e17ff21288ea4ceb3b5cc39
https://github.com/llvm/llvm-project/commit/700b5f1387a50bfc0e17ff21288ea4ceb3b5cc39
Author: valadaptive <79560998+valadaptive at users.noreply.github.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
M llvm/test/CodeGen/AArch64/round-conv.ll
M llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll
M llvm/test/CodeGen/AArch64/round-fptoui-sat-scalar.ll
Log Message:
-----------
[AArch64] Add test coverage for roundeven + float-to-int conversions (#173515)
Split off from https://github.com/llvm/llvm-project/pull/170018, which
was becoming a bit of a rats' nest.
This PR:
- Cleans up the `arm64-cvt-simd-fptoi.ll`, `round-conv.ll`,
`round-fptosi-sat-scalar.ll`, and `round-fptoui-sat-scalar.ll`
regression tests, removing `nounwind readnone` annotations from the
rounding function calls. These were changed in #171288 to be LLVM
intrinsics instead of libcalls, so we no longer need to annotate them in
order for them to be compiled to native instructions. I've also removed
the declaration blocks at the end of the files, since they're no longer
necessary.
- Adds `roundeven` tests to the 4 regression tests mentioned above, to
go along with the other rounding functions currently tested.
- Changes `round-conv.ll` to have autogenerated CHECK lines/assertions,
so it's simpler to update.
- Checks with GlobalISel as well in `round-conv.ll`,
`round-fptosi-sat-scalar.ll`, and `round-fptoui-sat-scalar.ll`. The
generated code is identical in `round-conv.ll`, but not yet as good in
the latter two.
The supporting changes are necessary here and would be difficult to
split off for little gain.
Commit: c961174b2d557c04b32fbe104ca32f5294345864
https://github.com/llvm/llvm-project/commit/c961174b2d557c04b32fbe104ca32f5294345864
Author: Dimitri Ratz <dimitri.ratz at protonmail.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M clang-tools-extra/clangd/FindSymbols.cpp
M clang-tools-extra/clangd/FindSymbols.h
M clang-tools-extra/clangd/Protocol.cpp
M clang-tools-extra/clangd/Protocol.h
M clang-tools-extra/clangd/SemanticHighlighting.cpp
A clang-tools-extra/clangd/test/symbol-tags.test
M clang-tools-extra/clangd/test/symbols.test
M clang-tools-extra/clangd/unittests/FindSymbolsTests.cpp
Log Message:
-----------
[clangd] Add support for additional symbol tags proposed for LSP 3.18 (#167536)
Implements support for symbol tags proposed for LSP 3.18 in
https://github.com/microsoft/language-server-protocol/pull/2003,
in the `documentSymbols` and `workspace/symbols` requests.
Fixes https://github.com/clangd/clangd/issues/2123.
---------
Co-authored-by: chouzz <zhouhua258 at outlook.com>
Co-authored-by: Dimitri Ratz <dimitri.ratz at thinkdigital.cc>
Commit: bf43c9813b1d70fed5507e43095fe0e2f6302e59
https://github.com/llvm/llvm-project/commit/bf43c9813b1d70fed5507e43095fe0e2f6302e59
Author: Thurston Dang <thurston at google.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
Log Message:
-----------
[msan][NFCI] Check number of operands in handleVectorComparePackedIntrinsic() (#177291)
handleVectorComparePackedIntrinsic() can currently handle x86 and Arm
NEON vector comparisons, but is a bit lax about checking the number of
operands. This patch parameterizes the handler to check for the correct
number of operands, and also that the 3rd operand in x86 vector
comparisons is an ImmArg.
Commit: b960ef30293aafaac75e222384686dc323329d01
https://github.com/llvm/llvm-project/commit/b960ef30293aafaac75e222384686dc323329d01
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
Log Message:
-----------
[AArch64] Stop using TargetFlags as RegState for LOADgot (#177411)
The register state flags have been represented using `unsigned`, but we
intend to make this an `enum class` in llvm/llvm-project#177090.
That change has shown there is some strange behaviour in this AArch64
function, which uses operand TargetFlags (usually used for representing
some abstract form of relocation information to clarify global accesses,
also represented with `unsigned`) to initialise the register state flags
(used for representing how the register operand is used by an
instruction). These TargetFlags are always 0 in the tests, so remove the
variable and assignment.
Commit: 3781a08e3e996351d76a43228c1d20399fdcc929
https://github.com/llvm/llvm-project/commit/3781a08e3e996351d76a43228c1d20399fdcc929
Author: valadaptive <79560998+valadaptive at users.noreply.github.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Clarify semantics of undef in shufflevector masks (#171453)
The current phrasing of `shufflevector` in the language reference
states:
> A poison element in the mask vector specifies that the resulting
element is poison. For backwards-compatibility reasons, LLVM temporarily
also accepts undef mask elements, which will be interpreted the same way
as poison elements.
This is a bit ambiguous. Does it mean that an undef mask element
produces a poison result element, or an undef result element?
Per https://reviews.llvm.org/D148637, the answer is the former. I've
updated the docs to make this explicit.
As part of the same paragraph, the language reference also currently
states:
> If the shuffle mask selects an undef element from one of the input
vectors, the resulting element is undef.
When I first skimmed this, I thought it meant that an undef *mask
element* resulted in an undef result element. However, it's actually
talking about undef *input elements*. That's easy to miss, since the
rest of the paragraph discusses mask elements. I've moved that sentence
to its own paragraph to make things less confusing.
Commit: dcd646889328b7f8f3ed841ec9acfc7ceead90ab
https://github.com/llvm/llvm-project/commit/dcd646889328b7f8f3ed841ec9acfc7ceead90ab
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Log Message:
-----------
[RISCV] Improve vector pseudo table's experiences on translating between two different pseudo opcodes. NFC (#177232)
Sometimes we might need to translate from one vector pseudo -- like
`PseudoVFMUL_ALT_VV_M8_E16` -- to its `VFSUB_VV` counterpart, namely
`PseudoVFSUB_ALT_VV_M8_E16`. It's difficult to do this efficiently with
the current vector pseudo search table infrastructure. So I propose two
changes in this patch:
1. Currently both `RISCVVInversePseudosTable` and `RISCVVPseudosTable`
does not distinguish between F16 and BF16. This will be problematic
during lookup -- especially for `RISCVVInversePseudosTable`. So I added
a new single-bit field `IsAltFmt` into both tables.
2. It'd be great for `RISCVVPseudosTable` to return not just the base
instruction opcode but also LMUL & SEW (if there is any). Because the
alternative will require multiple additional steps (e.g. calling
`getLMul(TSFlags)`) -- especially for the SEW-specific pseudos -- that
are not really ergonomic. So I added `VLMul`, `SEW`, and `IsAltFmt` to
the result of `RISCVVPseudosTable::getPseudoInfo`. The downside of this
is of course bloating the table size, which is why I tried to mitigate
it with using bit fields.
This should be a NFC
Commit: b043479e0c4b239ab6a5e66f1dc4fecdf8d7ff40
https://github.com/llvm/llvm-project/commit/b043479e0c4b239ab6a5e66f1dc4fecdf8d7ff40
Author: Lang Hames <lhames at gmail.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M orc-rt/lib/executor/Session.cpp
M orc-rt/unittests/SessionTest.cpp
Log Message:
-----------
[orc-rt] Fix some Session::shutdown bugs. (#177528)
All calls to Session::shutdown were enquing their on-shutdown-complete
callbacks in Session's ShutdownInfo struct, but this queue is only
drained once by the thread that initiates shutdown. After the queue is
drained, subsequent calls to Session::shutdown were enquing their
callbacks in a queue that would never be drained.
This patch updates Session::shutdown to check whether shutdown has
completed already and, if so, run the on-shutdown-complete immediately.
This patch also fixes a concurrency bug: Session::shutdownComplete was
accessing SI->OnCompletes outside the session mutex, but this could lead
to corruption of SI->OnCompletes if a concurrent call to
Session::shutdown tried to enqueue a new callback to SI->OnCompletes
concurrently. This has been fixed by moving the SI->OnCompletes queue to
a new variable under the Session mutex, then draining the new queue
outside the mutex. (No testcase yet: this was discovered by observation,
and replicating the bug would depend on timing).
Commit: 859052a34ec5ad6c240366837fda12aa6801a560
https://github.com/llvm/llvm-project/commit/859052a34ec5ad6c240366837fda12aa6801a560
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-01-22 (Thu, 22 Jan 2026)
Changed paths:
M lldb/include/lldb/Host/FileSystem.h
M lldb/source/Commands/CommandObjectProcess.cpp
M lldb/source/Host/common/FileSystem.cpp
M lldb/test/API/functionalities/process_save_core/TestProcessSaveCore.py
Log Message:
-----------
[lldb] Improve error message when we can't save core (#177496)
When you specify a filename to `process save core`, we'll write it in
the current working directory. In Xcode the CWD is `/` and you can't
generally write there.
```
(lldb) process save-core --style full foo
error: failed to save core file for process: Read-only file system
```
This PR improves the error message by including the output file when we
can't save core. However, just printing the filename isn't that much
more helpful, because FileSystem::Resolve only makes a path absolute if
it exists.
```
error: failed to save core file for process to 'foo': Read-only file system
```
Therefore I also modified the interface to add a flag to force resolve a
potentially non-exist path.
```
error: failed to save core file for process to '/foo': Read-only file system
```
Commit: fec463eea676faf85ad4e4733c62c8c7313c0266
https://github.com/llvm/llvm-project/commit/fec463eea676faf85ad4e4733c62c8c7313c0266
Author: Matthew Devereau <matthew.devereau at arm.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
A llvm/test/CodeGen/AArch64/clmul.ll
Log Message:
-----------
[AArch64][ISel] Add lowering for i8 clmul intrinsics (#177323)
clmul added in #168731, can be lowered to pmul for full i8 vector types.
Commit: 79fb1eb8c1d9a15e89a36aceb791e6fbc25641f7
https://github.com/llvm/llvm-project/commit/79fb1eb8c1d9a15e89a36aceb791e6fbc25641f7
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M lldb/source/Commands/CommandObjectApropos.cpp
A lldb/test/API/commands/apropos/formatting/TestAproposFormatting.py
M lldb/test/API/commands/settings/TestSettings.py
Log Message:
-----------
[lldb] Fix padding for settings in `apropos` output (#177295)
In the `apropos` output, commands are padded to the longest command so
that their descriptions are aligned. This PR does the same thing for the
settings.
Fixes #177284
Commit: e3c786874ae4064b78526e4b2c110484114b6dcf
https://github.com/llvm/llvm-project/commit/e3c786874ae4064b78526e4b2c110484114b6dcf
Author: yonillasky <yonillasky at users.noreply.github.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/include/llvm/IR/Metadata.h
M llvm/lib/IR/Metadata.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
A llvm/test/Transforms/Coroutines/coro-split-tbaa-md-neg-2.ll
A llvm/test/Transforms/Coroutines/coro-split-tbaa-md-neg.ll
A llvm/test/Transforms/Coroutines/coro-split-tbaa-md.ll
Log Message:
-----------
[LLVM][Coroutines] Introduce TBAA metadata for coro frame object (#176543)
This helps subsequent passes to determine that aliasing between frame
objects and all other types is impossible.
There were cases where this AA issue seriously harmed the performance
of compute intensive code running inside a coroutine, since it broke
LICM and caused it to reload frame data inside tight loops over and over.
Co-authored-by: Yoni Lavi <yoni.lavi at nextsilicon.com>
Commit: ca8c01cce22c0618a990e1ab2d7618d6f9420792
https://github.com/llvm/llvm-project/commit/ca8c01cce22c0618a990e1ab2d7618d6f9420792
Author: Matthias Springer <me at m-sp.org>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M mlir/lib/Interfaces/ControlFlowInterfaces.cpp
Log Message:
-----------
[mlir][Interfaces] Fix use-after-free after #176641 (#177536)
Fix a use-after-free after #176641: the successor operands
`OperandRange` is now longer value after the terminator has been erased.
Commit: 149c76538ef830f5213579b77ee67bcf18f24bb2
https://github.com/llvm/llvm-project/commit/149c76538ef830f5213579b77ee67bcf18f24bb2
Author: Mel Chen <mel.chen at sifive.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/AArch64/early_exit_costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-avoid-scalarization.ll
M llvm/test/Transforms/LoopVectorize/X86/conditional-scalar-assignment.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/std-find.ll
Log Message:
-----------
[LV] Separate runtime check cost from total overhead in profitability check (#176754)
In isOutsideLoopWorkProfitable function, there are two places where only
the runtime check cost (RtC) should be used, but incorrectly included
the costs of middle blocks and early-exit blocks.
1. VectorizeMemoryCheckThreshold comparison for interleaving-only
2. Minimum trip count that bounds runtime check overhead, i.e. MinTC2
calculation
This results in an overly conservative minimum profitable trip count.
This patch separates the runtime check cost from the total overhead
cost, and uses only RtC for VectorizeMemoryCheckThreshold comparison and
the MinTC2 calculation.
Commit: d904de08062f8f45a4c66fc49cacf3bf18412ed0
https://github.com/llvm/llvm-project/commit/d904de08062f8f45a4c66fc49cacf3bf18412ed0
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/test/AST/ByteCode/cxx23.cpp
M clang/test/AST/ByteCode/functions.cpp
Log Message:
-----------
[clang][bytecode] Fix a diagnostic discrepancy (#177384)
The current interpreter does _not_ evaluate function calls when checking
for a potential constant expression.
However, it _does_ evaluate the initializers of constructors. In the
bytecode interpreter, this is harder because we compile the initializers
and the body of a constructor all in the same function.
Add a special opcode that we emit after the constructor initializers and
that aborts when we're checking for a potential constant expression.
Commit: 7e25a3132f3a1854fdbaf5e443b34fda253857b1
https://github.com/llvm/llvm-project/commit/7e25a3132f3a1854fdbaf5e443b34fda253857b1
Author: Steffen Larsen <sholstla at amd.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp
M llvm/test/CodeGen/AMDGPU/opencl-printf.ll
Log Message:
-----------
[AMDGPU] Fix use-after-erase in OpenCL printf runtime binding (#177356)
When handling OpenCL printf calls, the AMDGPU backend replaces the
actual function call with a runtime binding. However, this replacement
currently assumes that there are no uses of the original call value
result. If there are uses, the erasure of the function call leads to
errors.
This patch replaces all uses of the original printf call with a 0 value
constant, signalling success of the printf operation.
---------
Signed-off-by: Steffen Holst Larsen <HolstLarsen.Steffen at amd.com>
Co-authored-by: Steffen Holst Larsen <HolstLarsen.Steffen at amd.com>
Commit: 4d55fb46624afb17e8bb70b308cf0d0e8a48e6cd
https://github.com/llvm/llvm-project/commit/4d55fb46624afb17e8bb70b308cf0d0e8a48e6cd
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
Log Message:
-----------
[TargetLowering] Avoid unnecessary EVT -> Type -> EVT roundtrip (NFC) (#177328)
For pointers, this gets the pointer EVT, then converts it back into a
type, and then gets the EVT for that type again. We can directly use the
pointer EVT.
Commit: 7184229feafb6695e2b82adda805ccb5f82a1717
https://github.com/llvm/llvm-project/commit/7184229feafb6695e2b82adda805ccb5f82a1717
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
M llvm/include/llvm/CodeGen/MachineInstrBuilder.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/PeepholeOptimizer.cpp
M llvm/lib/CodeGen/RenameIndependentSubregs.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
M llvm/lib/CodeGen/SplitKit.cpp
M llvm/lib/CodeGen/TailDuplicator.cpp
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
M llvm/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
M llvm/lib/Target/ARM/A15SDOptimizer.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp
M llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
M llvm/lib/Target/AVR/AVRISelLowering.cpp
M llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
M llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
M llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
M llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
M llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
M llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
M llvm/lib/Target/Hexagon/HexagonGenMemAbsolute.cpp
M llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
M llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
M llvm/lib/Target/Hexagon/HexagonQFPOptimizer.cpp
M llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
M llvm/lib/Target/Mips/Mips16InstrInfo.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
M llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
M llvm/lib/Target/Mips/MipsSEISelLowering.cpp
M llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
M llvm/lib/Target/PowerPC/PPCFastISel.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
M llvm/lib/Target/X86/X86TileConfig.cpp
M llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td
M llvm/test/TableGen/GlobalISelEmitter/DefaultOpsGlobalISel.td
M llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
M llvm/test/TableGen/GlobalISelEmitter/RegSequence.td
M llvm/test/TableGen/GlobalISelEmitter/Subreg.td
M llvm/test/TableGen/GlobalISelEmitter/dead-def.td
M llvm/test/TableGen/GlobalISelEmitter/gisel-physreg-input.td
M llvm/test/TableGen/GlobalISelEmitter/input-discard.td
M llvm/test/TableGen/GlobalISelEmitter/multiple-output-discard.td
M llvm/test/TableGen/GlobalISelEmitter/multiple-output.td
M llvm/test/TableGen/GlobalISelEmitter/nested-subregs.td
M llvm/test/TableGen/GlobalISelEmitter/optional-def.td
M llvm/test/TableGen/GlobalISelEmitter/output-discard.td
M llvm/test/TableGen/GlobalISelEmitter/undef-tied-input.td
M llvm/tools/llvm-exegesis/lib/Assembler.cpp
M llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
M llvm/tools/llvm-reduce/deltas/ReduceRegisterDefs.cpp
M llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
Log Message:
-----------
[NFC][MI] Tidy Up RegState enum use (2/2) (#177090)
This Change makes `RegState` into an enum class, with bitwise operators.
It also:
- Updates declarations of flag variables/arguments/returns from
`unsigned` to `RegState`.
- Updates empty RegState initializers from 0 to `{}`.
If this is causing problems in downstream code:
- Adopt the `RegState getXXXRegState(bool)` functions instead of using a
ternary operator such as `bool ? RegState::XXX : 0`.
- Adopt the `bool hasRegState(RegState, RegState)` function instead of
using a bitwise check of the flags.
Commit: 84b2f120f348484cf69a166b159a8cc104a54d90
https://github.com/llvm/llvm-project/commit/84b2f120f348484cf69a166b159a8cc104a54d90
Author: Raul Tambre <raul at tambre.ee>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/MC/MCStreamer.h
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/Target/M68k/M68kAsmPrinter.cpp
M llvm/lib/Target/M68k/M68kAsmPrinter.h
M llvm/lib/Target/X86/X86AsmPrinter.cpp
A llvm/test/CodeGen/X86/asm-dialect-directive.ll
M llvm/test/CodeGen/X86/coal-sections.ll
Log Message:
-----------
[MC][X86/M68k] Emit syntax directive for AT&T (#167234)
This eases interoperability by making it explicit in emitted assembly code which syntax is used.
Refactored to remove X86-specific directives and logic from the generic MC(Asm)Streamer.
Motivated by building LLVM with `-mllvm -x86-asm-syntax=intel` (i.e. a global preference for Intel
syntax). A Bolt test (`runtime/X86/fdata-escape-chars.ll`) was using `llc` to compile to assembly
and then assembling with `clang`. The specific option causes Clang to assume Intel syntax but only
for assembly and not inline assembly.
Commit: 2d62af808b17d62847bc9bcb724be19388ba0f72
https://github.com/llvm/llvm-project/commit/2d62af808b17d62847bc9bcb724be19388ba0f72
Author: Raul Tambre <raul at tambre.ee>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M bolt/test/X86/lit.local.cfg
M bolt/test/lit.local.cfg
Log Message:
-----------
[NFCI][bolt][test] Enable AT&T syntax generally (#172355)
Having it in the X86 subdirectory only affects tests in that directory.
That's however not sufficient as for example runtime/X86/pie-exceptions-split.test is affected but
isn't located in the X86 directory.
This essentially fixes the fix for the original commit by guarding it properly for when the X86
target has been built and the flag is recognized.
Fixes: 6c48fbc1dcfbd44a47f126f21e575340b67aac06
Commit: e85bbd09491f3409cf4d844e6f57e91ab028defa
https://github.com/llvm/llvm-project/commit/e85bbd09491f3409cf4d844e6f57e91ab028defa
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll
A llvm/test/CodeGen/AMDGPU/default-flat-work-group-size-overrides-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll
R llvm/test/CodeGen/AMDGPU/waves-per-eu-hints-lower-occupancy-target.ll
Log Message:
-----------
Revert "[AMDGPU] Allow amdgpu-waves-per-eu to lower target occupancy range" (#177544)
Reverts llvm/llvm-project#168358
Buildbot failure as commented in original PR.
Commit: a6481281940298cd96507e808ec56909bd34992c
https://github.com/llvm/llvm-project/commit/a6481281940298cd96507e808ec56909bd34992c
Author: Jannick Kremer <jannick.kremer at mailbox.org>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M clang/bindings/python/clang/cindex.py
M clang/bindings/python/tests/cindex/test_code_completion.py
M clang/bindings/python/tests/cindex/test_enums.py
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[libclang/python] Add CompletionChunkKind enum and deprecate old CompletionChunk.Kind (#176631)
This adresses point 1 from
https://github.com/llvm/llvm-project/issues/156680.
Since step 4 is already completed, `CompletionChunk.Kind` becomes unused
in this PR, so it is removed.
Commit: adc64c6e1745a14896efa48d23fc541e4efe5a53
https://github.com/llvm/llvm-project/commit/adc64c6e1745a14896efa48d23fc541e4efe5a53
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/TreeTransform.h
M clang/test/SemaCXX/cxx2c-fold-exprs.cpp
Log Message:
-----------
[Clang] Fix the normalization of fold constraints (#177531)
Fold constraints can contain packs expanded from different locations.
For `C<Ps...>`, where the ellipsis immediately follows the argument, the
pack should be expanded in place regardless of the fold expression. For
`C<Ps> && ...`, the fold expression itself is responsible for expanding
Ps.
Previously, both kinds of packs were expanded by the fold expression,
which broke assumptions within concept caching. This patch fixes that by
preserving PackExpansionTypes for the first kind of pack while rewriting
them to non-packs for the second kind.
This patch also removes an unused function and performs some cleanup of
the evaluation contexts. Hopefully it is viable for backporting.
No release note, as this issue was a regression.
Fixes https://github.com/llvm/llvm-project/issues/177245
Commit: a01e09182e79a9e6486b345593d3781fbe2a8bdd
https://github.com/llvm/llvm-project/commit/a01e09182e79a9e6486b345593d3781fbe2a8bdd
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Target/ARC/ARCRegisterInfo.cpp
Log Message:
-----------
[NFC][ARC] Tidy Up RegState in ARC Backend (#177546)
This was missed in llvm/llvm-project#177090 because Github CI and my
local build don't have experimental targets enabled.
This is the only problematic RegState use in the experimental targets.
Commit: fed07a9649802731943732ab61a5cef69b8ffbf9
https://github.com/llvm/llvm-project/commit/fed07a9649802731943732ab61a5cef69b8ffbf9
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
A llvm/test/CodeGen/AArch64/GlobalISel/pr166541.ll
Log Message:
-----------
[AArch64][GlobalISel] Commit reproducer for crash #166541 (#177190)
Crash was fixed in #175810, this is just committing the reproducer.
Commit: b9ab8885c89b80cdb638aecbd5114672ec4fdb4b
https://github.com/llvm/llvm-project/commit/b9ab8885c89b80cdb638aecbd5114672ec4fdb4b
Author: Frank Schlimbach <frank.schlimbach at intel.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M mlir/include/mlir/Dialect/Shard/IR/ShardOps.td
M mlir/include/mlir/Dialect/Shard/Transforms/Transforms.h
M mlir/lib/Conversion/ShardToMPI/ShardToMPI.cpp
M mlir/lib/Dialect/Linalg/Transforms/ShardingInterfaceImpl.cpp
M mlir/lib/Dialect/Shard/Transforms/Transforms.cpp
M mlir/test/Conversion/ShardToMPI/convert-shard-to-mpi.mlir
Log Message:
-----------
[mlir][shard,mpi] Lowering shard.allgather to MPI (#177202)
- lowering `shard.allgather` to `mpi.allgather`
- fixing lowering of `shard.allreduce`
- minor refactoring
Commit: 580b6dc05accfa32c0e46cc4a88787016ef7bbfe
https://github.com/llvm/llvm-project/commit/580b6dc05accfa32c0e46cc4a88787016ef7bbfe
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/clmul-vector-256.ll
M llvm/test/CodeGen/X86/clmul-vector-512.ll
M llvm/test/CodeGen/X86/clmul-vector.ll
Log Message:
-----------
[X86] Enable custom lowering of 256/512-bit vXi32 and vXi64 CLMUL nodes (#177554)
Similar to 128-bit v4i32/v2i64 support, these are can now be efficiently
lowered to PCLMUL nodes through unrolling, shuffle combining and
concatenation
If the target only supports PCLMUL then they will remain as 128-bit
nodes, but if VPCLMULQDQ is supported then they should merge into wider
types.
Commit: 4e51f9044f17a00f5c6c0f5b2abf1fdb9b8d9eeb
https://github.com/llvm/llvm-project/commit/4e51f9044f17a00f5c6c0f5b2abf1fdb9b8d9eeb
Author: Davide Grohmann <davide.grohmann at arm.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVOps.h
A mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.h
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td
M mlir/lib/Dialect/SPIRV/IR/SPIRVTosaOps.cpp
M mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops.mlir
M mlir/test/Target/SPIRV/tosa-ops.mlir
M mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
Log Message:
-----------
[mlir][spirv] Add Conv operations for TOSA Extended Instruction Set (001000.1) (#176908)
This patch expands support for the TOSA Extended Instruction Set
(001000.1) to the SPIR-V dialect in MLIR. The TOSA extended instruction
set provides a standardized set of machine learning operations designed
to be used within `spirv.ARM.Graph` operations (corresponding to
OpGraphARM in SPV_ARM_graph) and typed with `!spirv.arm.tensor<...>`
(corresponding to OpTypeTensorARM in SPV_ARM_tensor).
The change introduces:
* Extending dialect plumbing for import, serialization, and
deserialization of the TOSA extended instruction set.
* The `spirv.Tosa.*Conv*` convolution operation from TOSA extended
instruction, each lowering to the corresponding `OpExtInst`.
* Verification enforcing that new convolution operations appears only
within `spirv.ARM.Graph` regions, operates on `!spirv.arm.tensor<...>`
types, and is well-formed according to the TOSA 001000.1 specification.
All convolution operations from TOSA 001000.1 extended instructions are
introduced: [parser, printer, verifier, and round-trip tests using
MLIR’s SPIR-V serialization/deserialization infrastructure are included.
This work aligns with Khronos SPIR-V TOSA specifications.
Specification:
https://github.khronos.org/SPIRV-Registry/extended/TOSA.001000.1.html
---------
Signed-off-by: Davide Grohmann <davide.grohmann at arm.com>
Co-authored-by: Jakub Kuderski <kubakuderski at gmail.com>
Commit: 7f39d92d56d11f6e56db4996aba4e7c531aa8059
https://github.com/llvm/llvm-project/commit/7f39d92d56d11f6e56db4996aba4e7c531aa8059
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
Log Message:
-----------
[clang][bytecode][NFC] Move some opcode impls to the source file (#177543)
They aren't templated, so move them to Interp.cpp to make the header
file a bit shorter.
Commit: f016ee5339aa313ab90182595fe12bc1a16e2db1
https://github.com/llvm/llvm-project/commit/f016ee5339aa313ab90182595fe12bc1a16e2db1
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Add missing dependency for b9ab8885c89b80cdb638aecbd5114672ec4fdb4b
Commit: 323bb143491f61530097c8efd97f6269369e2e8d
https://github.com/llvm/llvm-project/commit/323bb143491f61530097c8efd97f6269369e2e8d
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Function.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpFrame.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/test/AST/ms-constexpr-new.cpp
M clang/test/SemaCXX/ms-constexpr-invalid.cpp
M clang/test/SemaCXX/ms-constexpr-new.cpp
M clang/test/SemaCXX/ms-constexpr.cpp
Log Message:
-----------
[clang][bytecode] Finish support for `msvc::constexpr` (#177388)
Keep track of whether an `InterpFrame` is allowed to call
`msvc::constexpr` functions via two new opcodes.
Commit: 7826cbeacb0c7277bc905a7930f00575e9be88b2
https://github.com/llvm/llvm-project/commit/7826cbeacb0c7277bc905a7930f00575e9be88b2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/test/Transforms/Attributor/IPConstantProp/openmp_parallel_for.ll
Log Message:
-----------
Attributor: Regenerate baseline test checks (#177560)
Commit: e6195237a28d46ebd25c9d97cf59136637a61d0e
https://github.com/llvm/llvm-project/commit/e6195237a28d46ebd25c9d97cf59136637a61d0e
Author: Artem Kroviakov <71938912+akroviakov at users.noreply.github.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
Log Message:
-----------
[MLIR][XeGPU] Add simple rank-based sg layout creation (#172867)
Commit: 2142388717b593f80f9e370ef1e0b1d42a3c861c
https://github.com/llvm/llvm-project/commit/2142388717b593f80f9e370ef1e0b1d42a3c861c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/test/CodeGen/X86/clmul-vector-256.ll
M llvm/test/CodeGen/X86/clmul-vector-512.ll
Log Message:
-----------
[X86] Add 256-bit and 512-bit CLMULR and CLMULH test coverage (#177561)
Commit: b791501e8062b8037c86ea1249c0ea8119f4d8fb
https://github.com/llvm/llvm-project/commit/b791501e8062b8037c86ea1249c0ea8119f4d8fb
Author: John Hui <updog at j-hui.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M clang/lib/CodeGen/CGObjC.cpp
M clang/test/CodeGenObjC/arc-arm.m
M clang/test/CodeGenObjC/arc-foreach.m
M clang/test/CodeGenObjC/arc-property.m
M clang/test/CodeGenObjC/arc-related-result-type.m
M clang/test/CodeGenObjC/arc-unopt.m
M clang/test/CodeGenObjC/arc-unsafeclaim.m
M clang/test/CodeGenObjC/arc-with-atthrow.m
M clang/test/CodeGenObjC/ns_consume_null_check.m
M clang/test/CodeGenObjC/objc-arc-container-subscripting.m
M clang/test/CodeGenObjC/os_log.m
M clang/test/CodeGenObjCXX/auto-release-result-assert.mm
M clang/test/CodeGenObjCXX/inheriting-constructor-cleanup.mm
M llvm/lib/Target/AArch64/AArch64FastISel.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/test/CodeGen/AArch64/call-rv-marker.ll
Log Message:
-----------
Revert "Reapply "[CGObjC] Allow clang.arc.attachedcall on -O0 (#164875)" (#177285)" (#177533)
This reverts commit 4b939beb79e3390046b760bef71b7d891ba9b4df.
This commit seems to be causing these test failures:
- ThreadSanitizer-x86_64-iossim.Darwin.norace-objcxx-run-time.mm
https://ci.swift.org/job/llvm.org/job/clang-san-iossim/14230/testReport/junit/ThreadSanitizer-x86_64-iossim/Darwin/norace_objcxx_run_time_mm/
- ThreadSanitizer-x86_64-iossim.Darwin.objc-synchronize-cycle-tagged.mm
https://ci.swift.org/job/llvm.org/job/clang-san-iossim/14230/testReport/junit/ThreadSanitizer-x86_64-iossim/Darwin/objc_synchronize_cycle_tagged_mm/
- ThreadSanitizer-x86_64-iossim.Darwin.objc-synchronize-tagged.mm
https://ci.swift.org/job/llvm.org/job/clang-san-iossim/14230/testReport/junit/ThreadSanitizer-x86_64-iossim/Darwin/objc_synchronize_tagged_mm/
- ThreadSanitizer-x86_64-iossim.Darwin.objc-synchronize.mm
https://ci.swift.org/job/llvm.org/job/clang-san-iossim/14230/testReport/junit/ThreadSanitizer-x86_64-iossim/Darwin/objc_synchronize_mm/
With the error message:
```
fatal error: error in backend: Cannot select: intrinsic %llvm.objc.clang.arc.noop.use
```
Commit: 39a9e659de27004b818795d4d60678857e331ade
https://github.com/llvm/llvm-project/commit/39a9e659de27004b818795d4d60678857e331ade
Author: Prathamesh Tagore <63031630+meshtag at users.noreply.github.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp
Log Message:
-----------
[mlir][bufferization] Cache SymbolTableCollection for CallOp types (#176909)
Use the BufferizationState symbol table cache when resolving CallOp
callee types in getBufferType(), avoiding repeated SymbolTableCollection
creation. Add a const accessor (backed by a mutable cache) so const
state can reuse the same tables. Completes a marked TODO.
Commit: 6fc8028516220b25d6c878f492eebbae4c350298
https://github.com/llvm/llvm-project/commit/6fc8028516220b25d6c878f492eebbae4c350298
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Analysis/LazyValueInfo.cpp
Log Message:
-----------
[LVI] Fix the type when inferring nonnull from a dereferenceable attribute bundle (#177562)
Commit: de8126d62a47a571b931e0f21aba0542e1d58e61
https://github.com/llvm/llvm-project/commit/de8126d62a47a571b931e0f21aba0542e1d58e61
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/test/AST/ByteCode/c.c
Log Message:
-----------
[clang][bytecode] Fix mulc/divc op for IntegralAP types (#177565)
We need to allocate those.
Fixes https://github.com/llvm/llvm-project/issues/176740
Commit: 689f9788d3e482791d45e1e631a1bacf78f318ba
https://github.com/llvm/llvm-project/commit/689f9788d3e482791d45e1e631a1bacf78f318ba
Author: Nathan Malimban <131171416+nmalimban at users.noreply.github.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M mlir/lib/Dialect/MLProgram/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/test/Dialect/MLProgram/one-shot-bufferize.mlir
Log Message:
-----------
[ml_program] fix bufferizesToMemoryRead for ml_program.global_store (#177387)
This is a fix for the `BufferizableOpInterface` implementation for
`ml_program.global_store`.
`bufferizesToMemoryRead` currently returns false for
`GlobalStoreOpInterface`, but I believe it should return true as
`ml_program.global_store` needs to read its input buffer to know what
value to store to global.
This manifested in a bug where `one-shot-bufferize` would produce MLIR
that copies uninitialized data to the global var instead of the intended
value to be stored.
For the following MLIR:
```
module {
ml_program.global private mutable @"state_tensor"(dense<0.0> : tensor<4x75xf32>) : tensor<4x75xf32>
func.func @main() -> tensor<4x75xf32> {
%c0 = arith.constant 0 : index
%cst_val = arith.constant 1.0 : f32
%initial_state = ml_program.global_load @"state_tensor" : tensor<4x75xf32>
%val = tensor.extract %initial_state[%c0, %c0] : tensor<4x75xf32>
%next_val = arith.addf %val, %cst_val : f32
%updated_tensor = tensor.insert %next_val into %initial_state[%c0, %c0] : tensor<4x75xf32>
ml_program.global_store @"state_tensor" = %updated_tensor : tensor<4x75xf32>
return %updated_tensor : tensor<4x75xf32>
}
}
```
`one-shot-bufferize` produces this incorrect MLIR
```
module {
memref.global "private" @state_tensor : memref<4x75xf32> = dense<0.000000e+00>
func.func @main() -> tensor<4x75xf32> {
%c0 = arith.constant 0 : index
%cst = arith.constant 1.000000e+00 : f32
%0 = memref.get_global @state_tensor : memref<4x75xf32>
%1 = memref.load %0[%c0, %c0] : memref<4x75xf32>
%2 = arith.addf %1, %cst : f32
%alloc = memref.alloc() {alignment = 64 : i64} : memref<4x75xf32>
memref.copy %0, %alloc : memref<4x75xf32> to memref<4x75xf32>
memref.store %2, %alloc[%c0, %c0] : memref<4x75xf32>
%3 = bufferization.to_tensor %alloc : memref<4x75xf32> to tensor<4x75xf32>
%alloc_0 = memref.alloc() {alignment = 64 : i64} : memref<4x75xf32>
%4 = memref.get_global @state_tensor : memref<4x75xf32>
memref.copy %alloc_0, %4 : memref<4x75xf32> to memref<4x75xf32>
return %3 : tensor<4x75xf32>
}
}
```
Note that `memref.copy` at the end copies an uninitialized `alloc_0` to
the global variable.
But after the change we see the following MLIR:
```
module {
memref.global "private" @state_tensor : memref<4x75xf32> = dense<0.000000e+00>
func.func @main() -> tensor<4x75xf32> {
%c0 = arith.constant 0 : index
%cst = arith.constant 1.000000e+00 : f32
%0 = memref.get_global @state_tensor : memref<4x75xf32>
%1 = memref.load %0[%c0, %c0] : memref<4x75xf32>
%2 = arith.addf %1, %cst : f32
%alloc = memref.alloc() {alignment = 64 : i64} : memref<4x75xf32>
memref.copy %0, %alloc : memref<4x75xf32> to memref<4x75xf32>
memref.store %2, %alloc[%c0, %c0] : memref<4x75xf32>
%3 = bufferization.to_tensor %alloc : memref<4x75xf32> to tensor<4x75xf32>
%alloc_0 = memref.alloc() {alignment = 64 : i64} : memref<4x75xf32>
memref.copy %alloc, %alloc_0 : memref<4x75xf32> to memref<4x75xf32>
%4 = memref.get_global @state_tensor : memref<4x75xf32>
memref.copy %alloc_0, %4 : memref<4x75xf32> to memref<4x75xf32>
return %3 : tensor<4x75xf32>
}
}
```
We now see that the relevant data is copied to `alloc_0` before it is
stored in global.
Co-authored-by: Nathan Malimban <nmalimba at ah-nmalimba-l.dhcp.mathworks.com>
Commit: f5b62a78e8c7c542a3e25927948320c01a19ad19
https://github.com/llvm/llvm-project/commit/f5b62a78e8c7c542a3e25927948320c01a19ad19
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/test/Dialect/Linalg/vectorization/insert-slice.mlir
Log Message:
-----------
[mlir][linalg] Update createWriteOrMaskedWrite (#174810)
`createWriteOrMaskedWrite` is used extensively in the Linalg vectorizer.
When a write uses non-zero indices, the helper currently computes mask
sizes as if the write started at 0 (`size = dim(d)`), which can produce
incorrect `vector.create_mask` operands for the generated
`vector.transfer_write`. Instead, the mask size should be computed as
`size = dim(d) - write_index(d)`.
EXAMPLE
-------
Let`s use this example to illustrate:
```mlir
%res = tensor.insert_slice
%src into %dest[0, %c2] [5, 1] [1, 1] : tensor<5x1xi32> into tensor<?x3xi32>
```
This op is vectorized as a pair of `vector.transfer_read` +
`vector.transfer_write` ops. When calculating the mask for the
vector.transfer_write operation, the write indices should be taken into
account (*):
```mlir
%dim = tensor.dim %dest, %c_0 : tensor<?x3xi32>
// Subtract dim-0 and idx-0
%mask_size_0 = arith.subi %dim, %c0 : index
%x3 = arith.constant 3 : index
// Subtract dim-1 and idx-1
%mask_size_1 = arith.subi %c3, %c2 : index
%mask = vector.create_mask %mask_size_0, %mask_size_1 : vector<8x1xi1>
```
Currently, the mask is incorrectly computed as:
```mlir
%dim = tensor.dim %dest, %c_0 : tensor<?x3xi32>
%mask = vector.create_mask %dim, %c3 : vector<8x1xi1>
```
This PR fixes that.
(*) Vectorized with `transform.structured.vectorize %0 vector_sizes [8, 1]`
Commit: 4b7cf46f6bd1bcd3f908efaedfeea27b28b6d564
https://github.com/llvm/llvm-project/commit/4b7cf46f6bd1bcd3f908efaedfeea27b28b6d564
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M lldb/include/lldb/Host/windows/ProcessLauncherWindows.h
M lldb/include/lldb/Host/windows/PseudoConsole.h
M lldb/source/Host/windows/ProcessLauncherWindows.cpp
M lldb/source/Host/windows/PseudoConsole.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
M lldb/test/Shell/Settings/TestFrameFormatColor.test
M lldb/test/Shell/Settings/TestFrameFormatNoColor.test
Log Message:
-----------
[lldb][windows] add STDIN and STDOUT forwarding support (#175812)
Commit: dc741f2f7e88edef573cc95882934ea8b44812cd
https://github.com/llvm/llvm-project/commit/dc741f2f7e88edef573cc95882934ea8b44812cd
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaShapeOps.td
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/test/Dialect/Tosa/constant_folding.mlir
Log Message:
-----------
[mlir][tosa] Add constant folding for tosa.add_shape operation (#173112)
This commit introduces constant folding for the tosa.add_shape
operation. When both operands of the add_shape operation are constant
shapes, the operation is evaluated at compile-time.
Commit: 5faa18111280cc08656777ba132a05b2270467e0
https://github.com/llvm/llvm-project/commit/5faa18111280cc08656777ba132a05b2270467e0
Author: Jorn Tuyls <jorn.tuyls at gmail.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M mlir/include/mlir/Transforms/RegionUtils.h
M mlir/lib/Transforms/Utils/RegionUtils.cpp
M mlir/test/Transforms/move-operation-deps.mlir
Log Message:
-----------
[mlir] Add side-effect check to moveOperationDependencies (#176361)
This patch adds a side-effect check to `moveOperationDependencies` to
match the behavior of `moveValueDefinitions`. Previously,
`moveOperationDependencies` would move operations with side-effecting
dependencies, which could change program semantics.
**Note** that the existing test changes are needed because unregistered
operations (e.g., "moved_op"()) are treated as side-effecting. These
tests were updated to use pure operations for operations in the moved
slice, while keeping unregistered ops for operations that aren't moved
(e.g., "before"(), "foo"()). This ensures that tests continue to
exercise their intended functionality without being blocked by the new
side-effect check.
Commit: 7a10fc8d542560068fc871d24ae1becabfd5d26b
https://github.com/llvm/llvm-project/commit/7a10fc8d542560068fc871d24ae1becabfd5d26b
Author: Vishruth Thimmaiah <vishruththimmaiah at gmail.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
A llvm/test/CodeGen/RISCV/combine-clmul.ll
M llvm/test/CodeGen/X86/pclmulqdq.ll
Log Message:
-----------
[DAG] Add basic folds for CLMUL nodes (#176961)
Closes #176783
Adds support for folding `ISD::CMUL`/`CMULH`/`CMULR` nodes.
Commit: 6bae2a98b4c757da73611afe0f28b5ca5287d8c1
https://github.com/llvm/llvm-project/commit/6bae2a98b4c757da73611afe0f28b5ca5287d8c1
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M clang/docs/LanguageExtensions.rst
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Clarify specification for float min/max operations (#172012)
This implements some clarifications for the specification of floating
point min/max operations based on the discussion in
https://discourse.llvm.org/t/rfc-a-consistent-set-of-semantics-for-the-floating-point-minimum-and-maximum-operations/89006.
The key changes are:
* Explicitly specify minnum and maxnum with an sNaN operand as
non-deterministically either returning NaN or treating sNaN as qNaN.
This was implied by our general NaN semantics, but is important to call
out here due to the special behavior of sNaN.
* Explicitly specify the same non-determinism for the minnum/maxnum
based vector reductions as well.
* Explicitly specify the meaning of nsz on float min/max ops. In
particular, clarify that unlike normal nsz semantics, it does not allow
introducing a zero with a different sign out of thin air.
* Simplify the semantics comparison section. This now focuses only on
NaN and signed zero behavior, but omits information about exceptions
that is not relevant for these non-constrained intrinsics.
Commit: 8d55fa2853e239fda117c0f6976d10a6b89e7a3f
https://github.com/llvm/llvm-project/commit/8d55fa2853e239fda117c0f6976d10a6b89e7a3f
Author: LU-JOHN <John.Lu at amd.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.mir
M llvm/test/CodeGen/AMDGPU/s_cmp_0.ll
Log Message:
-----------
[AMDGPU] Remove redundant s_cmp_* after add X, 1 (#176962)
Convert:
```
s_add_u32 X, Y, 1
s_cmp_lg_i32 X, 0
```
to:
```
s_add_u32 X, Y, 1
<invert scc uses>
```
Also delete with s_cmp_eq_i32 X, 0, but inverting scc uses is not
necessary.
---------
Signed-off-by: John Lu <John.Lu at amd.com>
Commit: 3586588cc9d0b9b76ce8370505db4d5dbf1d5b70
https://github.com/llvm/llvm-project/commit/3586588cc9d0b9b76ce8370505db4d5dbf1d5b70
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/R600Processors.td
Log Message:
-----------
[NFCI][AMDGPU] Add `FeatureMadMacF32Insts` to all R600 processors (#177509)
Commit: 668d474185340099377820464eb1f334ce8cd875
https://github.com/llvm/llvm-project/commit/668d474185340099377820464eb1f334ce8cd875
Author: Scott Manley <rscottmanley at gmail.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M mlir/lib/Dialect/OpenACC/Transforms/ACCIfClauseLowering.cpp
M mlir/test/Dialect/OpenACC/acc-if-clause-lowering.mlir
Log Message:
-----------
[OpenACC][MLIR] clone private operands during ACCIfClauseLowering (#177458)
Clone the private operands into the compute region side. This also fixes
an issue where references to acc.private remain on the host side.
Commit: f010621809b3fab9f3d64fa39699ea5c0c11e699
https://github.com/llvm/llvm-project/commit/f010621809b3fab9f3d64fa39699ea5c0c11e699
Author: Luke Hutton <luke.hutton at arm.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/test/Dialect/Tosa/canonicalize.mlir
Log Message:
-----------
[mlir][tosa] Add a canonicalization to optimize cast cast sequences (#176904)
This commit introduces a new canonicalization over a sequence of cast
operations. cast->cast sequences can be simplified to a single cast when
no narrowing is performed inbetween. This optimization is limited to
integer types, since floating point casts may impact numerical
behaviour.
Commit: a3ebe650d3f3751786af10b4d6b17a3a59b9a332
https://github.com/llvm/llvm-project/commit/a3ebe650d3f3751786af10b4d6b17a3a59b9a332
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M libcxx/include/__vector/vector.h
Log Message:
-----------
[libc++][NFC] Clang-format <vector> and remove unused __self alias (#177021)
These changes were extracted out of the size-based vector patch.
Co-authored-by: Christopher Di Bella <cjdb at google.com>
Commit: 17a17fa81c48ad2c1cd36f27c317d964e86ecf1b
https://github.com/llvm/llvm-project/commit/17a17fa81c48ad2c1cd36f27c317d964e86ecf1b
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/include/llvm/Transforms/Utils/PredicateInfo.h
M llvm/lib/Transforms/Scalar/NewGVN.cpp
M llvm/lib/Transforms/Utils/PredicateInfo.cpp
A llvm/test/Transforms/SCCP/assume-operand-bundles.ll
A llvm/test/Transforms/Util/PredicateInfo/assume-operand-bundles.ll
Log Message:
-----------
[PredicateInfo] Extract information from assume operand bundles (#177349)
Commit: afec4c28d55acc81315a4ef4fb7bcf319da7c830
https://github.com/llvm/llvm-project/commit/afec4c28d55acc81315a4ef4fb7bcf319da7c830
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[LangRef] Normalize IEEE 754 spelling (#174721)
We currently use three spellings, "IEEE754", "IEEE-754" and "IEEE 754".
Normalize to the latter.
Commit: 0df9098c2563a7c2cf2a78b1514492f057bec1c8
https://github.com/llvm/llvm-project/commit/0df9098c2563a7c2cf2a78b1514492f057bec1c8
Author: Prathamesh Tagore <63031630+meshtag at users.noreply.github.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
M mlir/test/Dialect/Linalg/roundtrip-linalg-named-ops.mlir
M mlir/test/Dialect/Linalg/specialize-generic-ops.mlir
Log Message:
-----------
[mlir][linalg] Preserve cast semantics during generic to matmul (#174757)
Infer signed/unsigned cast intent from cast ops in linalg.generic bodies
and propagate it via the matmul cast attribute. This could otherwise lead
to silent overflow/underflow errors in e2e execution.
TODO: Extend this to other named ops that support cast attribute.
Fixes #174517
Commit: 6e738e187055bbd33b6c3d203b6b55904dfcb624
https://github.com/llvm/llvm-project/commit/6e738e187055bbd33b6c3d203b6b55904dfcb624
Author: Vikram Hegde <Vikram.Hegde at amd.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
Log Message:
-----------
[CodeGen][NPM] Add "PhysicalRegisterUsageAnalysis" once (#173489)
Commit: a71ca9b27c675a6b37c64089f6d742206ad7e8d0
https://github.com/llvm/llvm-project/commit/a71ca9b27c675a6b37c64089f6d742206ad7e8d0
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/utils/profcheck-xfail.txt
Log Message:
-----------
[ProfCheck] Add new tests to xfail list
PhaseOrdering fixes are likely to be coincidental and are probably in
passes we have not gotten to yet. We have not started working on any of
the coroutine passes.
Commit: 0145a643ccaf55adf33f117e50ff587a4d2b8d9c
https://github.com/llvm/llvm-project/commit/0145a643ccaf55adf33f117e50ff587a4d2b8d9c
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
M llvm/test/Transforms/DeadStoreElimination/simple.ll
Log Message:
-----------
[DSE] Make DSE eliminate stores to objects with a sized dead_on_return
dead_on_return is made optionally sized in #171712. This patch adds
handling in DSE so that we can actually eliminate stores to pointer
parameters marked with a sized dead_on_return attribute. We do not
eliminate stores where the store may overlap with bytes that are not
known to be dead after return.
Reviewers: nikic, antoniofrighetto, alinas, aeubanks
Pull Request: https://github.com/llvm/llvm-project/pull/173694
Commit: a10062d675128fc03476ea01cb42d723701a6677
https://github.com/llvm/llvm-project/commit/a10062d675128fc03476ea01cb42d723701a6677
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
Log Message:
-----------
DAG: Use poison in more vector legalization contexts (#177580)
Commit: b74e1bca6d77b3de5c05822d1631006ce2a30cc6
https://github.com/llvm/llvm-project/commit/b74e1bca6d77b3de5c05822d1631006ce2a30cc6
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/test/Transforms/InstCombine/assume-loop-align.ll
M llvm/test/Transforms/InstCombine/assume.ll
M llvm/test/Transforms/InstCombine/assume_inevitable.ll
Log Message:
-----------
[InstCombine] Always fold alignment assumptions into operand bundles (#177597)
Commit: 70ee6e4427c8f55a910193bbda2eadf75e8a75f2
https://github.com/llvm/llvm-project/commit/70ee6e4427c8f55a910193bbda2eadf75e8a75f2
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Support/Windows/Process.inc
M llvm/lib/Support/Windows/Threading.inc
Log Message:
-----------
[Support] Move loadSystemModuleSecure into Process.inc. NFC. (#177598)
Move Windows-specific function
`llvm::sys::windows::loadSystemModuleSecure` from
`lib/Support/Windows/Threading.inc` into
`lib/Support/Windows/Process.inc`.
This is to fix link problems on Windows, see
https://github.com/llvm/llvm-project/pull/169224#issuecomment-3790350128
Commit: 48fb51b14cdbbfe99abcef9bce0ba7e042b35bf5
https://github.com/llvm/llvm-project/commit/48fb51b14cdbbfe99abcef9bce0ba7e042b35bf5
Author: Valeriy Savchenko <vsavchenko at apple.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
A llvm/test/Transforms/VectorCombine/AArch64/fold-signbit-reduction-cmp.ll
A llvm/test/Transforms/VectorCombine/X86/fold-signbit-reduction-cmp.ll
Log Message:
-----------
[VectorCombine] Fold vector sign-bit checks (#175194)
Fold patterns that extract sign bits, reduce them, and compare against
boundary values into direct sign checks on the reduced vector.
```
icmp pred (reduce.{add,or,and,umax,umin}(lshr X, BitWidth-1)), C
-> icmp slt/sgt (reduce.{or,umax,and,umin}(X)), 0/-1
```
When the comparison is against 0 or MAX (1 for boolean reductions,
NumElts for add), the pattern reduces to one of four quantified
predicates:
- ∀x: x < 0 (AllNeg)
- ∀x: x ≥ 0 (AllNonNeg)
- ∃x: x < 0 (AnyNeg)
- ∃x: x ≥ 0 (AnyNonNeg)
The transform eliminates the shift and selects between
reduce.or/reduce.umax or reduce.and/reduce.umin based on cost modeling.
## The matrix of Alive2 proofs for every pair of {reduction,
comparison}:
| Reduction | == 0 | != 0 | == MAX | != MAX |
|-----------|------|------|--------|--------|
| or | [proof](https://alive2.llvm.org/ce/z/_BWxJW) |
[proof](https://alive2.llvm.org/ce/z/k3EiK6) |
[proof](https://alive2.llvm.org/ce/z/a8cAjp) |
[proof](https://alive2.llvm.org/ce/z/ci-HMt) |
| umax | [proof](https://alive2.llvm.org/ce/z/dWt28G) |
[proof](https://alive2.llvm.org/ce/z/_MqxXC) |
[proof](https://alive2.llvm.org/ce/z/KQebnF) |
[proof](https://alive2.llvm.org/ce/z/mixEgN) |
| and | [proof](https://alive2.llvm.org/ce/z/JgYrLj) |
[proof](https://alive2.llvm.org/ce/z/FZuPLy) |
[proof](https://alive2.llvm.org/ce/z/bYCa8V) |
[proof](https://alive2.llvm.org/ce/z/9fsLsN) |
| umin | [proof](https://alive2.llvm.org/ce/z/YnaSL-) |
[proof](https://alive2.llvm.org/ce/z/rGrgoM) |
[proof](https://alive2.llvm.org/ce/z/pb-ezQ) |
[proof](https://alive2.llvm.org/ce/z/JkoqEi) |
| add | [proof](https://alive2.llvm.org/ce/z/d5w5CF) |
[proof](https://alive2.llvm.org/ce/z/GUgQ2Z) |
[proof](https://alive2.llvm.org/ce/z/HnstY8) |
[proof](https://alive2.llvm.org/ce/z/j8z_3C) |
### Other test cases
| Test | Proof |
|------|-------|
| or_slt_1 (slt 1 ≡ eq 0) | [proof](https://alive2.llvm.org/ce/z/Wdb_uN)
|
| umax_sgt_0 (sgt 0 ≡ ne 0) |
[proof](https://alive2.llvm.org/ce/z/nw6NZc) |
| and_slt_max (slt 1 ≡ ne 1) |
[proof](https://alive2.llvm.org/ce/z/ZDMSXZ) |
| umin_sgt_max_minus_1 (sgt 0 ≡ eq 1) |
[proof](https://alive2.llvm.org/ce/z/Uynf8P) |
| add_ult_max (ult 4 ≡ ne 4) |
[proof](https://alive2.llvm.org/ce/z/pyDgTg) |
| add_ugt_max_minus_1 (ugt 3 ≡ eq 4) |
[proof](https://alive2.llvm.org/ce/z/mHVXJk) |
| ashr_add_eq_0 (ashr instead of lshr) |
[proof](https://alive2.llvm.org/ce/z/oa9Kgo) |
### or/umax and and/umin equivalence
| Check | Equivalence | Proof |
|-----------------|-------------|-------|
| AnyNeg | or slt 0 ≡ umax slt 0 |
[proof](https://alive2.llvm.org/ce/z/Do2tNQ) |
| AllNonNeg | or sgt -1 ≡ umax sgt -1 |
[proof](https://alive2.llvm.org/ce/z/N4kZ8Z) |
| AllNeg | and slt 0 ≡ umin slt 0 |
[proof](https://alive2.llvm.org/ce/z/4mNpMk) |
| AnyNonNeg | and sgt -1 ≡ umin sgt -1 |
[proof](https://alive2.llvm.org/ce/z/2pVnyg) |
Commit: 2357408dd2c7700d8153f26bb081bb1065287c41
https://github.com/llvm/llvm-project/commit/2357408dd2c7700d8153f26bb081bb1065287c41
Author: Artem Kroviakov <71938912+akroviakov at users.noreply.github.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
M mlir/test/Dialect/XeGPU/propagate-layout.mlir
Log Message:
-----------
[MLIR][XeGPU] Add layout propagation for `xegpu.store_matrix` (#174952)
Commit: 60a108bcc8a47f6b4091a6291636fbe4dec9615f
https://github.com/llvm/llvm-project/commit/60a108bcc8a47f6b4091a6291636fbe4dec9615f
Author: lonely eagle <2020382038 at qq.com>
Date: 2026-01-24 (Sat, 24 Jan 2026)
Changed paths:
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
M mlir/lib/Analysis/DataFlow/SparseAnalysis.cpp
M mlir/lib/Interfaces/ControlFlowInterfaces.cpp
Log Message:
-----------
[mlir][interface] Add getNonSuccessorInputs API to RegionBranchOpInterface (#175212)
Add getNonSuccessorInputs API to RegionBranchOpInterface.It is used to
return the non-forwarded arguments or results.
Commit: daa98ac40a010d19150d0256827075eb3b6eb45e
https://github.com/llvm/llvm-project/commit/daa98ac40a010d19150d0256827075eb3b6eb45e
Author: Lily Gorsheneva <bgorshenev at google.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Utils/PredicateInfo.cpp
Log Message:
-----------
inline assert-only variable from 17a17fa (#177602)
Commit: 168ccaebf0b0ed6c216edd54271f1cf57f45cc3b
https://github.com/llvm/llvm-project/commit/168ccaebf0b0ed6c216edd54271f1cf57f45cc3b
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M lldb/include/lldb/Host/windows/ProcessLauncherWindows.h
M lldb/include/lldb/Host/windows/PseudoConsole.h
M lldb/source/Host/windows/ProcessLauncherWindows.cpp
M lldb/source/Host/windows/PseudoConsole.cpp
M lldb/source/Plugins/Process/Windows/Common/ProcessWindows.cpp
M lldb/test/Shell/Settings/TestFrameFormatColor.test
M lldb/test/Shell/Settings/TestFrameFormatNoColor.test
Log Message:
-----------
Revert "[lldb][windows] add STDIN and STDOUT forwarding support (#175812)" (#177610)
Commit: 3a1288c0fbe113834dfa8835223bd8f1830ceb0d
https://github.com/llvm/llvm-project/commit/3a1288c0fbe113834dfa8835223bd8f1830ceb0d
Author: Nick Kreeger <nick.kreeger at gmail.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M mlir/include/mlir/Dialect/Utils/VerificationUtils.h
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/Utils/VerificationUtils.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/MemRef/invalid.mlir
M mlir/test/Dialect/Vector/invalid.mlir
Log Message:
-----------
[mlir][Utils] Add verifyElementTypesMatch helper (NFC) (#176668)
This change builds on #174336 and #175880, which introduced shared
VerificationUtils with verifyDynamicDimensionCount() and
verifyRanksMatch() methods.
This patch adds a new verifyElementTypesMatch() verification utility
that checks if two shaped types have matching element types and emits
consistent error messages. The utility is applied to several ops across
the MemRef and Vector dialects.
Commit: 45abb3027d183dd009c8f64d50d0ff8de24d3f1e
https://github.com/llvm/llvm-project/commit/45abb3027d183dd009c8f64d50d0ff8de24d3f1e
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
Log Message:
-----------
[PowerPC] Fix instruction sizes / branch relaxation (#175556)
For PowerPC, having accurate (or at least not too small) instruction
sizes is critical, because the PPCBranchSelector pass relies on them.
Underestimating the size of an instruction can result in the wrong
branch kind being chosen, which will result in an MC error.
This patch introduces validation that the instruction size reported by
TII matches the actually emitted instruction size, and fixes various
cases where this was not the case.
Fixes https://github.com/llvm/llvm-project/issues/175190.
Commit: 284d6d6c4973f6887258bfedca96867d78c63e5a
https://github.com/llvm/llvm-project/commit/284d6d6c4973f6887258bfedca96867d78c63e5a
Author: Alexey Bader <alexey.bader at intel.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M libsycl/Maintainers.md
Log Message:
-----------
[libsycl][NFC] Assign lead maintainers for the project (#176769)
To align with https://llvm.org/docs/DeveloperPolicy.html#maintainers
libsycl project must explicitly list lead maintainers.
Commit: c28c8a0056110dfd4689b7c0f0a2d034a6e5b2ab
https://github.com/llvm/llvm-project/commit/c28c8a0056110dfd4689b7c0f0a2d034a6e5b2ab
Author: Sang Ik Lee <sang.ik.lee at intel.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
Log Message:
-----------
[MLIR][XeGPU] Add two 8bit float types F8E4M3FN and F8E5M2 to valid XeGPU float type. (#169420)
These float types are already part of MLIR built in types.
This PR just adds them as valid float types for XeGPU dialect.
For bit format of the two float types, see
https://onnx.ai/onnx/technical/float8.html
Commit: 32ce22f9939a793e5ffde112e974617229e2c1e2
https://github.com/llvm/llvm-project/commit/32ce22f9939a793e5ffde112e974617229e2c1e2
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
A .github/workflows/prune-branches.yml
A .github/workflows/prune-unused-branches.py
Log Message:
-----------
[Github] Add initial workflow to prune unused user branches
This patch starts implementing the long requested feature of a workflow
to automatically prune user branches that are not tied to a PR. For now
this just consists of a script that finds user branches not attached to
a PR and prints them out. Future patches will add support for dumping
the diff between the branches and main (to persist to artifact storage
so people can recover if they intended to use the branch) and actually
deleting the branches.
Reviewers: cmtice, tstellar, petrhosek, vbvictor
Pull Request: https://github.com/llvm/llvm-project/pull/175693
Commit: 77ebdad20a1701f30b0610a6df01ea66693ce4cf
https://github.com/llvm/llvm-project/commit/77ebdad20a1701f30b0610a6df01ea66693ce4cf
Author: Zinovy Nis <zinovy.nis at gmail.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M clang-tools-extra/clang-tidy/modernize/CMakeLists.txt
M clang-tools-extra/clang-tidy/modernize/ModernizeTidyModule.cpp
A clang-tools-extra/clang-tidy/modernize/UseStringViewCheck.cpp
A clang-tools-extra/clang-tidy/modernize/UseStringViewCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
A clang-tools-extra/docs/clang-tidy/checks/modernize/use-string-view.rst
A clang-tools-extra/test/clang-tidy/checkers/modernize/use-string-view-custom-view.cpp
A clang-tools-extra/test/clang-tidy/checkers/modernize/use-string-view-cxx20.cpp
A clang-tools-extra/test/clang-tidy/checkers/modernize/use-string-view-ignored.cpp
A clang-tools-extra/test/clang-tidy/checkers/modernize/use-string-view.cpp
Log Message:
-----------
[clang-tidy] Add a new check 'modernize-use-string-view' (#172170)
Looks for functions returning `std::[w|u8|u16|u32]string` and suggests
to change it to `std::[...]string_view` if possible and profitable.
Example:
```cpp
std::string foo(int i) { // <---- can be replaced to `std::string_view foo(...) {`
switch(i) {
case 1:
return "case1";
case 2:
return "case2";
default:
return {};
}
}
```
Commit: e044ad99fed982e953c702dcc9067d156c6e37c5
https://github.com/llvm/llvm-project/commit/e044ad99fed982e953c702dcc9067d156c6e37c5
Author: Roy Shi <royitaqi at users.noreply.github.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M lldb/source/Host/macosx/objcxx/PosixSpawnResponsible.h
Log Message:
-----------
[lldb] Unconditionally setup posix spawn responsible flag (#177451)
# Problem
The TCC support in LLDB was added by
https://github.com/llvm/llvm-project/commit/041c7b84a4b925476d1e21ed302786033bb6035f.
However, on newer macOS machines, when launching and debugging an
Catalyst app on macOS (see
[Host.mm](https://github.com/llvm/llvm-project/blob/1286de408cc4a3ba1bd6cb6fed7d9517c0429462/lldb/source/Host/macosx/objcxx/Host.mm#L1208-L1219)),
the TCC doesn't work as expected. This is because, even though the
launch info doesn't specify `eLaunchFlagInheritTCCFromParent`, the app
is still launched to inherit TCC from its parent (the LLDB). This
prevents the user from granting privacy access to the Catalyst app,
which is usually reflected in macOS' "Privacy & Security" settings.
For example, in the following screenshot (see PR), even when the microphone
access has already been granted to WhatsApp, trying to use it will still
cause a prompt (as if it's not granted already).
# Fix
On newer macOS versions, the code which was originally inside the `#if
__has_include(<responsibility.h>)` actually works. So the fix is to
unwrap them from the `#if`.
Also, since we already forward declare the type and dlsym the symbol,
the `#include <responsibility.h>` can be removed. Same for the
`@available` check, since the original code handles `dlsym` failure.
See test and screenshots in PR.
Commit: a521774217437ef87576ff275c80a92fd6e25cc0
https://github.com/llvm/llvm-project/commit/a521774217437ef87576ff275c80a92fd6e25cc0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/X86/x86-interleaved-access.ll
Log Message:
-----------
DAG: Use poison for unused shuffle operands in legalizer (#177578)
Commit: 69eac707ed87c9f2a08dcea5947be2c4f4eec6aa
https://github.com/llvm/llvm-project/commit/69eac707ed87c9f2a08dcea5947be2c4f4eec6aa
Author: Eugene Epshteyn <eepshteyn at nvidia.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Options/Options.td
M clang/lib/Driver/ToolChains/Flang.cpp
M flang/include/flang/Frontend/CodeGenOptions.def
M flang/include/flang/Lower/LoweringOptions.def
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/test/Driver/fast-math.f90
A flang/test/Driver/protect-parens.f90
A flang/test/Lower/HLFIR/protect-parens-arrays.f90
A flang/test/Lower/HLFIR/protect-parens.f90
Log Message:
-----------
[flang] Support -f(no-)protect-parens (#170505)
Driver/compiler option plumbing to get -f(no-)protect-parens supported
on flang. (This option was already supported in clang, so extended the
option config to enable it in flang.)
In the compiler, support it in code gen options and in lowering options.
Hooked up lowering options with the code by @alexey-bataev that turns
off reassociation transformations.
Co-authored-by: Alexey Bataev <a.bataev at outlook.com>
Commit: 296f5a75bd72bc9342bd21010f8134ecc5ec78a3
https://github.com/llvm/llvm-project/commit/296f5a75bd72bc9342bd21010f8134ecc5ec78a3
Author: Steven Perron <stevenperron at google.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
A llvm/test/CodeGen/SPIRV/hlsl-resources/Sample.ll
Log Message:
-----------
[SPIR-V] Implement sample and sample_clamp intrinsics for HLSL resources (#177234)
This patch implements the `sample` and `sample_clamp` intrinsics for
HLSL
resources in the SPIR-V backend. It adds the necessary intrinsic
definitions
in `IntrinsicsDirectX.td` and `IntrinsicsSPIRV.td`, and implements the
instruction selection logic in `SPIRVInstructionSelector.cpp`.
Key changes:
- Added `int_dx_resource_sample` and `int_dx_resource_sample_clamp`
intrinsics.
- Added `int_spv_resource_sample` and `int_spv_resource_sample_clamp`
intrinsics.
- Implemented `selectSampleIntrinsic` to handle
`OpImageSampleImplicitLod` generation.
- Added `ResourceDimension` enum in `DXILABI.h` and `HLSLResource.h`.
- Added a new test case
`llvm/test/CodeGen/SPIRV/hlsl-resources/Sample.ll` to verify the
implementation.
Commit: 63e7070cbc6547aa16396a8721e8b5a97dc014c4
https://github.com/llvm/llvm-project/commit/63e7070cbc6547aa16396a8721e8b5a97dc014c4
Author: David Zbarsky <dzbarsky at gmail.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
[bazel] Add filegroup for builtin_headers (#67757)
I'd like to package these files into a distribution tar as part of
https://github.com/dzbarsky/static-clang. I'm currently applying patches
to the llvm repo but figured this bit could be upstreamed.
(Also open to ideas what to do about the `config.bzl` change in
https://github.com/dzbarsky/static-clang/blob/master/llvm.patch - it's
needed to link with musl libc)
Commit: 12cea04988d67f940bec567b04fe76e9c9da3d1b
https://github.com/llvm/llvm-project/commit/12cea04988d67f940bec567b04fe76e9c9da3d1b
Author: Dave Lee <davelee.com at gmail.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/lldbtest.py
Log Message:
-----------
[lldb] Improve filecheck() by replacing assertTrue with assertEqual (#177212)
Commit: 5b4a5cf51f37cb42c5e0bdb22b43acde137281c8
https://github.com/llvm/llvm-project/commit/5b4a5cf51f37cb42c5e0bdb22b43acde137281c8
Author: Sam Elliott <aelliott at qti.qualcomm.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/docs/CommandGuide/llvm-objdump.rst
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
A llvm/test/MC/RISCV/symbolize-operands.s
M llvm/tools/llvm-objdump/llvm-objdump.cpp
Log Message:
-----------
[RISCV][llvm-objdump] Support --symbolize-operands (#166656)
This adds support for `--symbolize-operands`, so that local references
are turned back into labels by objdump, which makes it easier to tell
what is going on with a linked object.
When using `--symbolize-operands`, branch target addresses are not
printed, only the referenced symbol is printed, and the address is
elided:
```
# Without --symbolize-operands
0: 04a05263 blez a0, 0x44 <.text+0x44>
...
40: fd1ff06f j 0x10 <.text+0x10>
44: 00000613 li a2, 0x0
# With --symbolize-operands
0: 04a05263 blez a0, <L3>
...
40: fd1ff06f j <L0>
<L3>:
44: 00000613 li a2, 0x0
```
Commit: 4237e74e52b0def565141937637cac35d635fd90
https://github.com/llvm/llvm-project/commit/4237e74e52b0def565141937637cac35d635fd90
Author: Kavin Gnanapandithan <kavin.balag at gmail.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops.ll
Log Message:
-----------
[VectorCombine] foldShuffleOfBinops - failure to track OperandValueInfo (#171934)
Resolves #170500.
Implemented mergeInfo static helper to return common
TTI::OperandValueInfo data .
Added common OperandValueInfo `Op0Info` && `Op1Info` to NewCost
calculation.
Commit: 6cf189acae1c54003db38ad43197b26aa0817d54
https://github.com/llvm/llvm-project/commit/6cf189acae1c54003db38ad43197b26aa0817d54
Author: NagaChaitanya Vellanki <pnagato at protonmail.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M clang/test/CodeGen/builtin-rotate.c
Log Message:
-----------
[clang][test] Fix builtin-rotate.c failure on ARM32 (#177290)
Replace unsigned __int128 with unsigned _BitInt(128) since __int128 is
not supported on ARM 32-bit targets.
Fixes https://lab.llvm.org/buildbot/#/builders/79/builds/2754
Commit: fef6a14b0293469786677d55a37dcb906c0a37f1
https://github.com/llvm/llvm-project/commit/fef6a14b0293469786677d55a37dcb906c0a37f1
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
Log Message:
-----------
[NFCI][AMDGPU] Fix the predicate `HasDsSrc2Insts` (#177621)
I'm not sure why the predicate has a `!`, and more surprisingly,
removing it doesn't change anything.
Commit: 9109c603a88f6ae1ab914cf2064bb5ad05970918
https://github.com/llvm/llvm-project/commit/9109c603a88f6ae1ab914cf2064bb5ad05970918
Author: Artem Kroviakov <71938912+akroviakov at users.noreply.github.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/uArch/IntelGpuXe2.h
M mlir/include/mlir/Dialect/XeGPU/uArch/uArchBase.h
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
Log Message:
-----------
[MLIR][XeGPU] Add uArch limitation to scatter load store (#172845)
Commit: 09685b79ed937ab956acd40a43eb1531165b4454
https://github.com/llvm/llvm-project/commit/09685b79ed937ab956acd40a43eb1531165b4454
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmax_legacy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmin_legacy.ll
Log Message:
-----------
[AMDGPU][GlobalISel] Add RegBankLegalize rules for fmin/fmax_legacy (#177520)
Commit: 9f3d143d96ecde0162ce0ee0585f4adee8007278
https://github.com/llvm/llvm-project/commit/9f3d143d96ecde0162ce0ee0585f4adee8007278
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
Log Message:
-----------
AMDGPU: Remove dead code configuring f16 is_fpclass (#177626)
isTypeLegal can never be true here. The register classes
are registered at the end of the target lowering constructor,
and in the subclasses.
Commit: 41567d8ec21b79e16c9f1223e2df23c65c1bc195
https://github.com/llvm/llvm-project/commit/41567d8ec21b79e16c9f1223e2df23c65c1bc195
Author: Amy Kwan <amy.kwan1 at ibm.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
M llvm/include/llvm/MC/MCGOFFAttributes.h
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.h
A llvm/test/CodeGen/SystemZ/zos_sinit.ll
Log Message:
-----------
[SystemZ] Implement ctor/dtor emission via @@SQINIT and .xtor sections (#171476)
This patch implements support for constructors/destructors by
introducing the
`@@SQINIT` section and emitting `.xtor.<priority>` sections within the
SystemZ
AsmPrinter and in the GOFF object lowering layer.
Commit: e67f934c12bf2a3dd6ed90b212ff40a96a074b3f
https://github.com/llvm/llvm-project/commit/e67f934c12bf2a3dd6ed90b212ff40a96a074b3f
Author: Jin Huang <jinhuang1102 at gmail.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/include/llvm/IR/ProfDataUtils.h
M llvm/lib/IR/ProfDataUtils.cpp
M llvm/lib/Transforms/Utils/IntegerDivision.cpp
M llvm/test/CodeGen/RISCV/idiv_large.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
M llvm/test/CodeGen/X86/pr38539.ll
M llvm/test/Transforms/ExpandIRInsts/X86/sdiv129.ll
M llvm/test/Transforms/ExpandIRInsts/X86/srem129.ll
M llvm/test/Transforms/ExpandIRInsts/X86/udiv129.ll
M llvm/test/Transforms/ExpandIRInsts/X86/urem129.ll
M llvm/test/Transforms/ExpandIRInsts/X86/vector.ll
Log Message:
-----------
[profcheck] Fix profle metatdata propagation for Large Integer operations (#175862)
This PR improves the propagation of profile metadata within the
ExpandIRInsts pass. When lowering large integer division operations, the
pass now ensures that branch weights are correctly attached to the
generated control flow, preventing the loss of profile data during IR
expansion.
This PR improves signed and unsigned division/remainder for non-native
bit widths (e.g., `sdiv/udiv i129`, `srem/urem i129`) and implemented
Heuristic-Based Branch Weights labeling using established heuristics for
edge cases e.g., `Division-by-zero guards` and `Magnitude comparisons
between dividends and divisors`.
It also adds detailed comments within the expansion logic to explain the
rationale behind specific branch weight choices and the underlying
mathematical invariants.
Please refer to the implementation details in the source code for the
specific branch weight values and the logic governing their application.
Co-authored-by: Jonas Devlieghere <jonas at devlieghere.com>
Commit: 7edf4e15ffbfb0ee7bd1b34fce85a3fb9c6c4872
https://github.com/llvm/llvm-project/commit/7edf4e15ffbfb0ee7bd1b34fce85a3fb9c6c4872
Author: Ryan Mitchell <Ryan.Mitchell at amd.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/include/llvm/MC/MCRegisterInfo.h
M llvm/include/llvm/Target/Target.td
A llvm/test/TableGen/regunit-intervals-impossible.td
A llvm/test/TableGen/regunit-intervals.td
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.h
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.h
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
Log Message:
-----------
[TableGen] Allow targets to enforce regunits assignment as intervals (#175823)
General tablegen infrastructure for #174888
Commit: 98b55bcdec90b7f948ab16a8d82ab40f3e0e0a1b
https://github.com/llvm/llvm-project/commit/98b55bcdec90b7f948ab16a8d82ab40f3e0e0a1b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Log Message:
-----------
AMDGPU: Move f16 legality configuration to SITargetLowering (#177629)
f16 is never legal for R600 so this should not be in the common
base class.
Commit: 1f8ae28e22bbb521db7cac4eb468d97e4f55fba5
https://github.com/llvm/llvm-project/commit/1f8ae28e22bbb521db7cac4eb468d97e4f55fba5
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M clang/include/clang/Driver/ToolChain.h
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/lib/Driver/ToolChains/Linux.h
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/lib/Driver/ToolChains/MSVC.h
M clang/test/Driver/hip-runtime-libs-linux.hip
M clang/test/Driver/hipstdpar.c
M clang/test/Driver/rocm-detect.hip
Log Message:
-----------
[HIP] Pass HIP library directly and refactor (#176019)
Summary:
Currently we pass `-L` and `-l` to get the HIP library. Because we are
attached to a single HIP installation it's far better to pass it by
filename. This is because the `-L` could be out of order with other user
libraries and those could override it. If someone uses HIP with a
specific ROCm installation they most likely want that library, otherwise
incompatibilities can occur. This is still overridable with command line
flags if users want to pass a different one for some reason.
This PR also refactors the handling to be more generic for future
additions.
Commit: c45684f037d206ef2fb631ea2fae121c1f2f6b00
https://github.com/llvm/llvm-project/commit/c45684f037d206ef2fb631ea2fae121c1f2f6b00
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll
Log Message:
-----------
AMDGPU: Ignore type legality in isFAbsFree (#177630)
This treats it as free on targets without legal f16. This
matches the existing logic in fneg, and they should be the same.
The test changes are mostly neutral with a few improvements.
Commit: 0d0249e543c91bf2f55c4e123ae8c31d3fabb77a
https://github.com/llvm/llvm-project/commit/0d0249e543c91bf2f55c4e123ae8c31d3fabb77a
Author: Patrick Simmons <patrick.simmons at amd.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
A llvm/test/CodeGen/AMDGPU/inlineasm-sgmask.ll
Log Message:
-----------
Try To Guess SGMasks for Inline Asm Instructions (#155491)
Addresses SWDEV-549227
Commit: f6f5ad3e0bd49c61d75a249ba00294eb20af56b3
https://github.com/llvm/llvm-project/commit/f6f5ad3e0bd49c61d75a249ba00294eb20af56b3
Author: David Green <david.green at arm.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/test/Analysis/CostModel/AArch64/arith.ll
Log Message:
-----------
[AArch64] Add some basic i128 arithmetic cost test cases. NFC
Commit: f7361efc07737d83d2b74ee49ccfac71a465bfba
https://github.com/llvm/llvm-project/commit/f7361efc07737d83d2b74ee49ccfac71a465bfba
Author: Jessica Clarke <jrtc27 at jrtc27.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Support/Threading.cpp
M llvm/lib/Support/Unix/Threading.inc
M llvm/lib/Support/Windows/Threading.inc
Log Message:
-----------
[Support] Avoid misguided FreeBSD hack (#177508)
FreeBSD doesn't do anything wrong here, it just happens to define and
use a struct thread in its own headers. The problems arise because here
in LLVM we have using namespace llvm prior to including system headers,
which is bad practice for precisely this reason. If we instead play by
the rules and defer our using namespace llvm until after we've included
the system headers then we no longer need this hack.
This hack is particularly problematic by being conditional on
__FreeBSD__ as of 9093ba9f7ee5 ("[Support] Include Support/thread.h
before api implementations (#111175)"), since on non-FreeBSD
Threading.inc can reference anything in Support/thread.h, only causing
errors on FreeBSD, which is precisely what happened in 64be34c562a2
("Enable using threads on z/OS (#171847)").
By deferring the using namespace llvm until after Threading.inc is
included there may be build failures introduced on untested platforms
due to needing to replace unqualified identifiers with qualified ones by
prepending llvm::.
Commit: 8b00b1d928861397301506e7768575e58d7e20ee
https://github.com/llvm/llvm-project/commit/8b00b1d928861397301506e7768575e58d7e20ee
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/Maintainers.md
Log Message:
-----------
Fix formatting in `Maintainers.md` (#177498)
Commit: 7c8a13ab79c713071b93ee4660c94133430091c2
https://github.com/llvm/llvm-project/commit/7c8a13ab79c713071b93ee4660c94133430091c2
Author: Justin Fargnoli <jfargnoli at nvidia.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/include/llvm/Transforms/Utils/LoopPeel.h
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/lib/Transforms/Utils/LoopPeel.cpp
Log Message:
-----------
[LoopPeel] change `peelLoop`'s return type from `bool` to `void` (#177488)
Commit: b94c5e097b4c69e58140d494bbb21265fc0df1a6
https://github.com/llvm/llvm-project/commit/b94c5e097b4c69e58140d494bbb21265fc0df1a6
Author: vangthao95 <vang.thao at amd.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f64.ll
Log Message:
-----------
[AMDGPU][GlobalISel] Add RegBankLegalize support for G_STRICT_FLDEXP (#177525)
Commit: ff97d1a5e349ec7409e82d7208f69144e3a92257
https://github.com/llvm/llvm-project/commit/ff97d1a5e349ec7409e82d7208f69144e3a92257
Author: Madhur Kumar <152476790+MadhurKumar004 at users.noreply.github.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M libc/shared/math.h
A libc/shared/math/dfmaf128.h
M libc/src/__support/math/CMakeLists.txt
A libc/src/__support/math/dfmaf128.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/dfmaf128.cpp
M libc/test/shared/CMakeLists.txt
M libc/test/shared/shared_math_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc][math] Refactor dfmaf128 to Header Only (#176480)
Closes https://github.com/llvm/llvm-project/issues/175315, Part of
https://github.com/llvm/llvm-project/issues/175344
Commit: fdb05bbf62b8d4fc8dc7ce1f1cfa570f3265a8ae
https://github.com/llvm/llvm-project/commit/fdb05bbf62b8d4fc8dc7ce1f1cfa570f3265a8ae
Author: cmtice <cmtice at google.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
Log Message:
-----------
[LLVM] Update assert to removed unused variable warning. (#177632)
Remove the variable definition and move the function call directly into
the assert statement. Otherwise builds with -Werror that don't use
asserts would fail.
Commit: e7e2c2b5655991c5a2f9f4a1bfcd8203f17893e9
https://github.com/llvm/llvm-project/commit/e7e2c2b5655991c5a2f9f4a1bfcd8203f17893e9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
M llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
Log Message:
-----------
[RISCV] Select (clmul (zext_inreg X, i32), (zext_inreg X, i32)) as (clmulh (slli X, 32), (slli X, 32)). (#177429)
Without Zba. We do the same for MUL->MULHU without Zba.
Commit: 896a6674730b678f73ad884264c785236fd1a04c
https://github.com/llvm/llvm-project/commit/896a6674730b678f73ad884264c785236fd1a04c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/include/llvm/Support/KnownBits.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/Support/KnownBits.cpp
M llvm/unittests/Support/KnownBitsTest.cpp
Log Message:
-----------
[KnownBits][SelectionDAG] Add KnownBits::clmul. Support trailing bits. NFC (#177517)
Borrow the known trailing bits logic from KnownBits::mul, but using
APIntOps::clmul.
Commit: 4435083c268db1dc2bc86595102ff1df9cc98e96
https://github.com/llvm/llvm-project/commit/4435083c268db1dc2bc86595102ff1df9cc98e96
Author: Prajwal <fasfasmag at proton.me>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M libc/shared/math.h
A libc/shared/math/f16fmal.h
M libc/src/__support/math/CMakeLists.txt
A libc/src/__support/math/f16fmal.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/f16fmal.cpp
M libc/test/shared/CMakeLists.txt
M libc/test/shared/shared_math_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc][math] Refactor f16fmal to header-only (#176576)
closes #175324
part of #175313
Commit: 852649d3ee567add0f2d09bd2f640b643d1f2a32
https://github.com/llvm/llvm-project/commit/852649d3ee567add0f2d09bd2f640b643d1f2a32
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
Log Message:
-----------
AMDGPU: Remove an unnecessary lookup of the AMDGPUSubtarget (#177646)
Commit: df3aa0d16b2311bfe5087eec09f2a6909db89157
https://github.com/llvm/llvm-project/commit/df3aa0d16b2311bfe5087eec09f2a6909db89157
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/ctlz.ll
Log Message:
-----------
AMDGPU: Use generic legality checks instead of checking subtarget feature (#177656)
Commit: 7638c1df0e50b42087260a95dc9ee890ab6ca594
https://github.com/llvm/llvm-project/commit/7638c1df0e50b42087260a95dc9ee890ab6ca594
Author: Sean Perry <perry at ca.ibm.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/TokenKinds.def
M clang/include/clang/Parse/Parser.h
M clang/include/clang/Sema/Sema.h
M clang/lib/Driver/ToolChains/ZOS.cpp
M clang/lib/Parse/ParsePragma.cpp
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaAttr.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
A clang/test/CodeGen/pragma-export.c
A clang/test/CodeGen/pragma-export.cpp
A clang/test/CodeGen/zos-pragmas.c
A clang/test/CodeGen/zos-pragmas.cpp
A clang/test/Parser/pragma-export.c
A clang/test/Parser/pragma-export.cpp
A clang/test/Sema/pragma-export-failing.c
A clang/test/Sema/pragma-export-failing.cpp
Log Message:
-----------
[SystemZ][z/OS] Implement #pragma export (#141671)
Implement the export pragma that is used in the z/OS XL C/C++ compiler
to indicate that an external symbol is to be exported from the shared
library. The syntax for the pragma is:
```
'#pragma' 'export' '(' name ')'
```
For C++ if `name` is a function it needs to be declared `extern "C"`.
See the following for the XL documentation:
- https://www.ibm.com/docs/en/zos/3.1.0?topic=descriptions-pragma-export
This code was originally in PR
https://github.com/llvm/llvm-project/pull/111035. I have split it out
into separate PRs so the code for #pragma export is in one PR and the
code for _Export keyword is in another. See that original PR for earlier
comments.
Commit: 537276af2d0e242679e0e4af42ab5db76dede07d
https://github.com/llvm/llvm-project/commit/537276af2d0e242679e0e4af42ab5db76dede07d
Author: Vikram Hegde <Vikram.Hegde at amd.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
Log Message:
-----------
[AMDGPU][NPM] Complete fast regalloc pipeline (#174096)
Commit: 8206c81433e32c89059cb829a4a8e11e7891ce1f
https://github.com/llvm/llvm-project/commit/8206c81433e32c89059cb829a4a8e11e7891ce1f
Author: google-yfyang <yfyang at google.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M libc/src/string/memory_utils/inline_memcpy.h
M libc/src/string/memory_utils/inline_memmove.h
M libc/src/string/memory_utils/inline_memset.h
Log Message:
-----------
[libc] Use generic/builtin.h for Emscripten in memory utils (#177474)
WASM supports bulk memory operations and can benefit from using
generic/builtin.h.
Commit: 6aedf1cfd0d245901dff71b664f0d35ccb939276
https://github.com/llvm/llvm-project/commit/6aedf1cfd0d245901dff71b664f0d35ccb939276
Author: Sang Ik Lee <sang.ik.lee at intel.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
Log Message:
-----------
[MLIR][XeGPU] Add more OCP micro scaling format types. (#177613)
Add fp4 - e2m1 and fp8 - e8m0 data type.
Commit: bfd8f6cf3b8db52f1efd1f2218328e6a468985fb
https://github.com/llvm/llvm-project/commit/bfd8f6cf3b8db52f1efd1f2218328e6a468985fb
Author: Utkarsh Saxena <usx at google.com>
Date: 2026-01-23 (Fri, 23 Jan 2026)
Changed paths:
A .github/workflows/prune-branches.yml
A .github/workflows/prune-unused-branches.py
M SECURITY.md
M bolt/test/X86/lit.local.cfg
M bolt/test/lit.local.cfg
M clang-tools-extra/clang-tidy/llvm/UseRangesCheck.cpp
M clang-tools-extra/clang-tidy/modernize/CMakeLists.txt
M clang-tools-extra/clang-tidy/modernize/ModernizeTidyModule.cpp
A clang-tools-extra/clang-tidy/modernize/UseStringViewCheck.cpp
A clang-tools-extra/clang-tidy/modernize/UseStringViewCheck.h
M clang-tools-extra/clangd/FindSymbols.cpp
M clang-tools-extra/clangd/FindSymbols.h
M clang-tools-extra/clangd/Protocol.cpp
M clang-tools-extra/clangd/Protocol.h
M clang-tools-extra/clangd/SemanticHighlighting.cpp
A clang-tools-extra/clangd/test/symbol-tags.test
M clang-tools-extra/clangd/test/symbols.test
M clang-tools-extra/clangd/unittests/FindSymbolsTests.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
M clang-tools-extra/docs/clang-tidy/checks/llvm/use-ranges.rst
A clang-tools-extra/docs/clang-tidy/checks/modernize/use-string-view.rst
M clang-tools-extra/test/clang-tidy/checkers/llvm/use-ranges.cpp
A clang-tools-extra/test/clang-tidy/checkers/modernize/use-string-view-custom-view.cpp
A clang-tools-extra/test/clang-tidy/checkers/modernize/use-string-view-cxx20.cpp
A clang-tools-extra/test/clang-tidy/checkers/modernize/use-string-view-ignored.cpp
A clang-tools-extra/test/clang-tidy/checkers/modernize/use-string-view.cpp
M clang/Maintainers.rst
M clang/bindings/python/clang/cindex.py
M clang/bindings/python/tests/cindex/test_code_completion.py
M clang/bindings/python/tests/cindex/test_enums.py
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/TokenKinds.def
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Driver/ToolChain.h
M clang/include/clang/Options/Options.td
M clang/include/clang/Parse/Parser.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ByteCode/Compiler.cpp
M clang/lib/AST/ByteCode/Function.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpFrame.h
M clang/lib/AST/ByteCode/Opcodes.td
M clang/lib/CIR/CodeGen/CIRGenCoroutine.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CodeGen/CGObjC.cpp
M clang/lib/CodeGen/CGOpenMPRuntime.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/Linux.cpp
M clang/lib/Driver/ToolChains/Linux.h
M clang/lib/Driver/ToolChains/MSVC.cpp
M clang/lib/Driver/ToolChains/MSVC.h
M clang/lib/Driver/ToolChains/ZOS.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Parse/ParsePragma.cpp
M clang/lib/Parse/ParseStmt.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/Sema/Sema.cpp
M clang/lib/Sema/SemaAttr.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/TreeTransform.h
M clang/test/AST/ByteCode/c.c
M clang/test/AST/ByteCode/cxx23.cpp
M clang/test/AST/ByteCode/functions.cpp
M clang/test/AST/ast-dump-decl-stmts.cpp
M clang/test/AST/ms-constexpr-new.cpp
M clang/test/CIR/CodeGen/coro-task.cpp
M clang/test/CodeGen/builtin-rotate.c
A clang/test/CodeGen/pragma-export.c
A clang/test/CodeGen/pragma-export.cpp
A clang/test/CodeGen/zos-pragmas.c
A clang/test/CodeGen/zos-pragmas.cpp
M clang/test/CodeGenHLSL/builtins/atan2-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/ceil-overloads.hlsl
M clang/test/CodeGenHLSL/builtins/cos-overloads.hlsl
M clang/test/CodeGenObjC/arc-arm.m
M clang/test/CodeGenObjC/arc-foreach.m
M clang/test/CodeGenObjC/arc-property.m
M clang/test/CodeGenObjC/arc-related-result-type.m
M clang/test/CodeGenObjC/arc-unopt.m
M clang/test/CodeGenObjC/arc-unsafeclaim.m
M clang/test/CodeGenObjC/arc-with-atthrow.m
M clang/test/CodeGenObjC/ns_consume_null_check.m
M clang/test/CodeGenObjC/objc-arc-container-subscripting.m
M clang/test/CodeGenObjC/os_log.m
M clang/test/CodeGenObjCXX/auto-release-result-assert.mm
M clang/test/CodeGenObjCXX/inheriting-constructor-cleanup.mm
M clang/test/Driver/hip-runtime-libs-linux.hip
M clang/test/Driver/hipstdpar.c
M clang/test/Driver/rocm-detect.hip
M clang/test/OpenMP/declare_mapper_codegen.cpp
M clang/test/OpenMP/target_map_array_of_structs_with_nested_mapper_codegen.cpp
M clang/test/OpenMP/target_map_array_section_of_structs_with_nested_mapper_codegen.cpp
A clang/test/Parser/pragma-export.c
A clang/test/Parser/pragma-export.cpp
A clang/test/PlatformSpecific/xrOS/Sema/Inputs/XROS.sdk/SDKSettings.json
A clang/test/PlatformSpecific/xrOS/Sema/infer-ios-availability.c
A clang/test/PlatformSpecific/xrOS/Sema/infer-unavailable-from-missing-ios-availability-mapping.c
A clang/test/Sema/pragma-export-failing.c
A clang/test/Sema/pragma-export-failing.cpp
M clang/test/SemaCXX/cxx2c-fold-exprs.cpp
M clang/test/SemaCXX/ms-constexpr-invalid.cpp
M clang/test/SemaCXX/ms-constexpr-new.cpp
M clang/test/SemaCXX/ms-constexpr.cpp
M flang/include/flang/Evaluate/real.h
M flang/include/flang/Frontend/CodeGenOptions.def
M flang/include/flang/Lower/LoweringOptions.def
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/test/Driver/fast-math.f90
A flang/test/Driver/protect-parens.f90
A flang/test/Lower/HLFIR/protect-parens-arrays.f90
A flang/test/Lower/HLFIR/protect-parens.f90
M libc/config/linux/app.h
M libc/shared/math.h
A libc/shared/math/dfmaf128.h
A libc/shared/math/f16fmal.h
M libc/src/__support/CPP/limits.h
M libc/src/__support/CPP/type_traits/is_integral.h
M libc/src/__support/CPP/type_traits/is_unsigned.h
M libc/src/__support/math/CMakeLists.txt
A libc/src/__support/math/dfmaf128.h
A libc/src/__support/math/f16fmal.h
M libc/src/__support/threads/fork_callbacks.cpp
M libc/src/__support/wchar/character_converter.h
M libc/src/math/generic/CMakeLists.txt
M libc/src/math/generic/dfmaf128.cpp
M libc/src/math/generic/f16fmal.cpp
M libc/src/string/memory_utils/inline_memcpy.h
M libc/src/string/memory_utils/inline_memmove.h
M libc/src/string/memory_utils/inline_memset.h
M libc/test/shared/CMakeLists.txt
M libc/test/shared/shared_math_test.cpp
M libcxx/include/__vector/vector.h
M libsycl/Maintainers.md
M lldb/include/lldb/Core/Debugger.h
M lldb/include/lldb/Core/ModuleList.h
M lldb/include/lldb/Host/FileSystem.h
M lldb/packages/Python/lldbsuite/test/lldbtest.py
M lldb/source/Commands/CommandObjectApropos.cpp
M lldb/source/Commands/CommandObjectProcess.cpp
M lldb/source/Core/CoreProperties.td
M lldb/source/Core/Debugger.cpp
M lldb/source/Core/ModuleList.cpp
M lldb/source/Host/common/FileSystem.cpp
M lldb/source/Host/macosx/objcxx/PosixSpawnResponsible.h
M lldb/source/Symbol/Variable.cpp
A lldb/test/API/commands/apropos/formatting/TestAproposFormatting.py
M lldb/test/API/commands/expression/diagnostics/TestExprDiagnostics.py
M lldb/test/API/commands/settings/TestSettings.py
M lldb/test/API/functionalities/process_save_core/TestProcessSaveCore.py
M llvm/Maintainers.md
M llvm/docs/CommandGuide/llvm-objdump.rst
M llvm/docs/LangRef.rst
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/Analysis/TargetTransformInfo.h
A llvm/include/llvm/CAS/CASNodeSchema.h
A llvm/include/llvm/CAS/NamedValuesSchema.h
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
M llvm/include/llvm/CodeGen/MachineInstrBuilder.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/Metadata.h
M llvm/include/llvm/IR/ProfDataUtils.h
M llvm/include/llvm/MC/MCGOFFAttributes.h
M llvm/include/llvm/MC/MCRegisterInfo.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Support/KnownBits.h
M llvm/include/llvm/Target/Target.td
M llvm/include/llvm/Transforms/Scalar/MemCpyOptimizer.h
M llvm/include/llvm/Transforms/Utils/LoopPeel.h
M llvm/include/llvm/Transforms/Utils/PredicateInfo.h
M llvm/lib/Analysis/LazyValueInfo.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
A llvm/lib/CAS/CASNodeSchema.cpp
M llvm/lib/CAS/CMakeLists.txt
A llvm/lib/CAS/NamedValuesSchema.cpp
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/PeepholeOptimizer.cpp
M llvm/lib/CodeGen/RenameIndependentSubregs.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SplitKit.cpp
M llvm/lib/CodeGen/TailDuplicator.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/IR/ProfDataUtils.cpp
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/Support/KnownBits.cpp
M llvm/lib/Support/Threading.cpp
M llvm/lib/Support/Unix/Threading.inc
M llvm/lib/Support/Windows/Process.inc
M llvm/lib/Support/Windows/Threading.inc
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64FastISel.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
M llvm/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp
M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/R600Processors.td
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
M llvm/lib/Target/ARC/ARCRegisterInfo.cpp
M llvm/lib/Target/ARM/A15SDOptimizer.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
M llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp
M llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
M llvm/lib/Target/AVR/AVRISelLowering.cpp
M llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
M llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
M llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
M llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
M llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
M llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
M llvm/lib/Target/Hexagon/HexagonGenMemAbsolute.cpp
M llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
M llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
M llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
M llvm/lib/Target/Hexagon/HexagonQFPOptimizer.cpp
M llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
M llvm/lib/Target/M68k/M68kAsmPrinter.cpp
M llvm/lib/Target/M68k/M68kAsmPrinter.h
M llvm/lib/Target/Mips/Mips16InstrInfo.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
M llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
M llvm/lib/Target/Mips/MipsSEISelLowering.cpp
M llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
M llvm/lib/Target/PowerPC/PPCFastISel.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCInstr64Bit.td
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.td
M llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
M llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.h
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/X86AsmPrinter.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
M llvm/lib/Target/X86/X86TileConfig.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/Instrumentation/MemProfUse.cpp
M llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
M llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp
M llvm/lib/Transforms/Scalar/LoopFuse.cpp
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/lib/Transforms/Scalar/NewGVN.cpp
M llvm/lib/Transforms/Utils/IntegerDivision.cpp
M llvm/lib/Transforms/Utils/LoopPeel.cpp
M llvm/lib/Transforms/Utils/PredicateInfo.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VectorCombine.cpp
M llvm/test/Analysis/CostModel/AArch64/arith.ll
A llvm/test/CodeGen/AArch64/GlobalISel/pr166541.ll
M llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
A llvm/test/CodeGen/AArch64/arm64-vcvt-fptoi.ll
M llvm/test/CodeGen/AArch64/call-rv-marker.ll
A llvm/test/CodeGen/AArch64/clmul.ll
A llvm/test/CodeGen/AArch64/fptoi-256.ll
M llvm/test/CodeGen/AArch64/round-conv.ll
M llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll
M llvm/test/CodeGen/AArch64/round-fptoui-sat-scalar.ll
M llvm/test/CodeGen/AArch64/sve-load-store-legalisation.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmax_legacy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmin_legacy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
M llvm/test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/ctlz.ll
A llvm/test/CodeGen/AMDGPU/default-flat-work-group-size-overrides-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
M llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fp-classify.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/frem.ll
A llvm/test/CodeGen/AMDGPU/inlineasm-sgmask.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf.ll
M llvm/test/CodeGen/AMDGPU/optimize-compare.mir
M llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/s_cmp_0.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f64.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-or.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vgpr-limit-gfx1250.ll
R llvm/test/CodeGen/AMDGPU/waves-per-eu-hints-lower-occupancy-target.ll
A llvm/test/CodeGen/PowerPC/ppc64-patchpoint-size-check.ll
M llvm/test/CodeGen/RISCV/clmul.ll
A llvm/test/CodeGen/RISCV/combine-clmul.ll
M llvm/test/CodeGen/RISCV/idiv_large.ll
M llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
M llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
A llvm/test/CodeGen/SPIRV/hlsl-resources/Sample.ll
A llvm/test/CodeGen/SystemZ/zos_sinit.ll
A llvm/test/CodeGen/X86/asm-dialect-directive.ll
M llvm/test/CodeGen/X86/clmul-vector-256.ll
M llvm/test/CodeGen/X86/clmul-vector-512.ll
M llvm/test/CodeGen/X86/clmul-vector.ll
M llvm/test/CodeGen/X86/coal-sections.ll
M llvm/test/CodeGen/X86/combine-pclmul.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
M llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
M llvm/test/CodeGen/X86/pclmulqdq.ll
M llvm/test/CodeGen/X86/pr38539.ll
M llvm/test/CodeGen/X86/x86-interleaved-access.ll
R llvm/test/CodeGen/fptoi-256.ll
A llvm/test/MC/RISCV/symbolize-operands.s
M llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td
M llvm/test/TableGen/GlobalISelEmitter/DefaultOpsGlobalISel.td
M llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td
M llvm/test/TableGen/GlobalISelEmitter/RegSequence.td
M llvm/test/TableGen/GlobalISelEmitter/Subreg.td
M llvm/test/TableGen/GlobalISelEmitter/dead-def.td
M llvm/test/TableGen/GlobalISelEmitter/gisel-physreg-input.td
M llvm/test/TableGen/GlobalISelEmitter/input-discard.td
M llvm/test/TableGen/GlobalISelEmitter/multiple-output-discard.td
M llvm/test/TableGen/GlobalISelEmitter/multiple-output.td
M llvm/test/TableGen/GlobalISelEmitter/nested-subregs.td
M llvm/test/TableGen/GlobalISelEmitter/optional-def.td
M llvm/test/TableGen/GlobalISelEmitter/output-discard.td
M llvm/test/TableGen/GlobalISelEmitter/undef-tied-input.td
A llvm/test/TableGen/regunit-intervals-impossible.td
A llvm/test/TableGen/regunit-intervals.td
M llvm/test/Transforms/Attributor/IPConstantProp/openmp_parallel_for.ll
A llvm/test/Transforms/Coroutines/coro-split-tbaa-md-neg-2.ll
A llvm/test/Transforms/Coroutines/coro-split-tbaa-md-neg.ll
A llvm/test/Transforms/Coroutines/coro-split-tbaa-md.ll
M llvm/test/Transforms/DeadStoreElimination/simple.ll
M llvm/test/Transforms/ExpandIRInsts/X86/sdiv129.ll
M llvm/test/Transforms/ExpandIRInsts/X86/srem129.ll
M llvm/test/Transforms/ExpandIRInsts/X86/udiv129.ll
M llvm/test/Transforms/ExpandIRInsts/X86/urem129.ll
M llvm/test/Transforms/ExpandIRInsts/X86/vector.ll
M llvm/test/Transforms/InstCombine/assume-loop-align.ll
M llvm/test/Transforms/InstCombine/assume.ll
M llvm/test/Transforms/InstCombine/assume_inevitable.ll
A llvm/test/Transforms/LoopFusion/pr115279.ll
M llvm/test/Transforms/LoopVectorize/AArch64/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/AArch64/early_exit_costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-avoid-scalarization.ll
M llvm/test/Transforms/LoopVectorize/X86/conditional-scalar-assignment.ll
M llvm/test/Transforms/LoopVectorize/find-last.ll
R llvm/test/Transforms/MemCpyOpt/stack-move-offset.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/std-find.ll
A llvm/test/Transforms/SCCP/assume-operand-bundles.ll
A llvm/test/Transforms/Util/PredicateInfo/assume-operand-bundles.ll
A llvm/test/Transforms/VectorCombine/AArch64/fold-signbit-reduction-cmp.ll
A llvm/test/Transforms/VectorCombine/X86/fold-signbit-reduction-cmp.ll
M llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops.ll
M llvm/test/tools/llvm-exegesis/AArch64/debug-gen-asm.s
M llvm/tools/llvm-exegesis/lib/Assembler.cpp
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
M llvm/tools/llvm-reduce/deltas/ReduceRegisterDefs.cpp
M llvm/unittests/CAS/CMakeLists.txt
A llvm/unittests/CAS/NamedValuesSchemaTest.cpp
M llvm/unittests/Support/KnownBitsTest.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
M llvm/utils/TableGen/Common/CodeGenRegisters.h
M llvm/utils/TableGen/Common/CodeGenTarget.cpp
M llvm/utils/TableGen/Common/CodeGenTarget.h
M llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
M llvm/utils/gn/secondary/llvm/lib/CAS/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/CAS/BUILD.gn
M llvm/utils/profcheck-xfail.txt
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVOps.h
A mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.h
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVTosaTypes.td
M mlir/include/mlir/Dialect/Shard/IR/ShardOps.td
M mlir/include/mlir/Dialect/Shard/Transforms/Transforms.h
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/include/mlir/Dialect/Tosa/IR/TosaShapeOps.td
M mlir/include/mlir/Dialect/Utils/VerificationUtils.h
M mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td
M mlir/include/mlir/Dialect/XeGPU/uArch/IntelGpuXe2.h
M mlir/include/mlir/Dialect/XeGPU/uArch/uArchBase.h
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
M mlir/include/mlir/Transforms/RegionUtils.h
M mlir/lib/Analysis/DataFlow/SparseAnalysis.cpp
M mlir/lib/Conversion/ShardToMPI/ShardToMPI.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Dialect/Linalg/Transforms/ShardingInterfaceImpl.cpp
M mlir/lib/Dialect/Linalg/Transforms/Specialize.cpp
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/lib/Dialect/MLProgram/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCIfClauseLowering.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVTosaOps.cpp
M mlir/lib/Dialect/Shard/Transforms/Transforms.cpp
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Utils/VerificationUtils.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPropagateLayout.cpp
M mlir/lib/Interfaces/ControlFlowInterfaces.cpp
M mlir/lib/Transforms/Utils/RegionUtils.cpp
M mlir/test/Conversion/ShardToMPI/convert-shard-to-mpi.mlir
M mlir/test/Dialect/GPU/invalid.mlir
M mlir/test/Dialect/Linalg/roundtrip-linalg-named-ops.mlir
M mlir/test/Dialect/Linalg/specialize-generic-ops.mlir
M mlir/test/Dialect/Linalg/vectorization/insert-slice.mlir
M mlir/test/Dialect/MLProgram/one-shot-bufferize.mlir
M mlir/test/Dialect/MemRef/invalid.mlir
M mlir/test/Dialect/OpenACC/acc-if-clause-lowering.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
M mlir/test/Dialect/SPIRV/IR/tosa-ops.mlir
M mlir/test/Dialect/Tosa/canonicalize.mlir
M mlir/test/Dialect/Tosa/constant_folding.mlir
M mlir/test/Dialect/Vector/invalid.mlir
M mlir/test/Dialect/XeGPU/propagate-layout-inst-data.mlir
M mlir/test/Dialect/XeGPU/propagate-layout-subgroup.mlir
M mlir/test/Dialect/XeGPU/propagate-layout.mlir
M mlir/test/Target/LLVMIR/omptarget-llvm.mlir
M mlir/test/Target/SPIRV/tosa-ops.mlir
M mlir/test/Transforms/move-operation-deps.mlir
M mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
M offload/libomptarget/omptarget.cpp
A offload/test/mapping/declare_mapper_target_checks.cpp
M openmp/device/src/Configuration.cpp
M orc-rt/lib/executor/Session.cpp
M orc-rt/unittests/SessionTest.cpp
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/usx95/01-23-fix_issue_with_references_to_fields
Compare: https://github.com/llvm/llvm-project/compare/fc31d53c40d2...bfd8f6cf3b8d
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